JPH06275064A - Dynamic ram - Google Patents

Abstract

PURPOSE:To secure the stable operation of a sense amplifier e.g. even at the time of obtaining the large capacity of 256Mbit by reducing the parasitic resistance of a sense amplifier driving signal line related to a DRAM. CONSTITUTION:A sense amplifier driving circuit 46(i+1)/2 generating a sense amplifier driving signal NSA and the sense amplifier driving circuit 49(i+1)/2 generating the sense amplifier driving signal PSA are arranged to face each other. A sense amplifier driving signal bus 50(i+1)/2 supplying the sense amplifier driving signal NSA to sense amplifier driving signal lines 441, 44i+1 and the sense amplifier driving signal bus 51(i+1)/2 supplying the sense amplifier driving signal PSA to the sense amplifier driving signal lines 45i, 45i+1 are prolonged in linear.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (dy) which is a semiconductor memory device which requires a memory holding operation, a so-called refresh operation, and which can be written / read at any time.
namic random access memory), so-called DRAM.

[0002]

2. Description of the Related Art Conventionally, as a DRAM, for example, a DRAM having a memory capacity of 64 Mbits, one having a schematic plan view thereof is proposed in FIG.

In the figure, 1 is a main body of a DRAM, 2 to 5 are row decoders for decoding row addresses, 6 to 13 are memory areas having a memory capacity of 8 Mbits, generally called a memory cell array, 14 ~ 21
Is a sense amplifier drive circuit array in which sense amplifier drive circuits that generate a sense amplifier drive signal and drive the sense amplifiers are arranged.

FIG. 8 is a schematic plan view showing the structure of the memory cell arrays 6 and 7. In FIG. 8, the subscripts of symbols are so-called hexadecimal numbers, and the matrix of the elements to which the symbols are attached. It is described to indicate the position of the shape.

In the figure, 22A _{0 to} 22A _F , 22B _{0 to} 22
B _F , 23A _{0 to} 23A _F , 23B _{0 to} 23B _F are 256K
A memory area generally called a memory cell block having a memory capacity of bits (256 rows × 1024 columns),
Numerals 24 _{0 to} 24 _F and 25 _{0 to} 25 _F are sense amplifier rows in which sense amplifiers are arranged, and the other memory cell array 8
.. to 13 are similarly configured.

FIG. 9 is a schematic plan view showing the configuration of the memory cell array 6 and the sense amplifier drive circuit array 14, and in FIG. 9, each subscript of a symbol is a hexadecimal number. It is shown and is shown to indicate the matrix-like position of the numbered elements.

In the figure, 26 ₀₀₀ to 260 _FF , 26 ₁₀₀ to 26
_1FF is a fixed memory area generally called a memory cell segment, and 27 _{00 to} 270 _0F and 27 _{10 to} 27 _1F are sense amplifiers for the sense amplifier drive signal NSA to be supplied to the nMOS transistors forming the sense amplifier. It is a drive signal line.

_{Further, 28 00 ~28 0F, 28 10} ~28 1F is a sense amplifier drive signal line for the sense amplifier driving signals PSA to be supplied to the pMOS transistor constituting the sense amplifier.

[0009] In addition, 29 ₀₀ ~29 _0F the sense amplifier drive signal NSA _O0, PSA ₀₀ ~NSA _0F, the sense amplifier driving circuit for driving the sense amplifier generates a PSA _0F, 29
_{10 to} 29 _1F are sense amplifier drive signals NSA ₁₀ and PSA ₁₀
To NSA _1F and PSA _1F to drive the sense amplifier.

Also, 30₀₀~ 30_0FDrive sense amplifier
Signal line 27₀₀~ 27_0FSense amplifier drive signal NSA₀₀
~ NSA_0FFor supplying sense amplifier drive signal bus, 30
_Ten~ 30_1FIs a sense amplifier drive signal line 27_Ten~ 27_1FTo
Sense amplifier drive signal NSA _Ten~ NSA_1FSupply
It is a sense amplifier drive signal bus.

Also, 31₀₀~ 31_0FDrive sense amplifier
Signal line 28₀₀~ 28_0FSense amplifier drive signal PSA₀₀
~ PSA_0FFor supplying sense amplifier drive signal bus, 31
_Ten~ 31_1FIs a sense amplifier drive signal line 28_Ten~ 28_1FTo
Sense amplifier drive signal PSA _Ten~ PSA_1FSupply
It is a sense amplifier drive signal bus.

Sense amplifier drive signal bus 30 _00-
30 _0F , 30 ₁₀ to 30 _1F , 31 _{00 to} 31 _0F , 31 _{10 to} 3
1 _1F is a sense amplifier drive signal line 27 _{00 to} 27 _0F , 27
It is extended at the top of _{10 ~27 1F, 28 00 ~28 0F} , 28 10 ~28 1F.

FIG. 10 is a circuit diagram showing a portion of the memory cell segment 26 ₀₀₀ and the sense amplifier drive circuit _{2900. In} the memory cell segment 26 ₀₀₀ , WL ₀ , WL _n , WL _{n + 1} , WL _2n is a word line for selecting a memory cell, BL ₀ , / BL ₀ , BL _m , /
BL _m is a bit line for writing and reading information.

Further, 32 ₀₀ , 32 _{0 m} , 32 _n0 , 32 _nm ,
32 _{(n + 1) 0} , 32 _{(n + 1) m} , 32 _{(2n) 0} , 32 _{(2n) m} are memory cells for storing information, and 33, 34 are memory cell blocks for selecting memory cell blocks. Selection circuit, 3
5 _0, 35 _m is a sense amplifier for amplifying the read-out information.

36 ₀ and 36 _m are column gates for selecting columns (bit line pairs), DB and / DB are data buses commonly provided for a plurality of bit line pairs,
CL ₀ and CL _m are ON and OF of the column gates 36 ₀ and 36 _m.
A column selection signal line for controlling F.

Further, in the sense amplifier driving circuit 29 _00, 38 and 39 pMOS transistors, 40, 41 nMOS transistor, phi, / phi sense amplifier driving circuit activating signal in inverted relationship, R, / R is inverted The related reset signal, VPR, is the precharge voltage (1/2 V
CC).

In this DRAM, at the time of reading, any one of the memory cell arrays 6 to 9 or the memory cell arrays 10 to 13 is selected. For example, the memory cell arrays 6 to 9 are selected.
If the reading is performed from, for example, in the memory cell array 6, the memory cell blocks 22A _k, 22
A _{k + 1} , 23A _k , 23A _{k + 1} or 22B _k , 22B _{k + 1} ,
23B _k and 23B _{k + 1} are selected. However, k = even.

Therefore, in this case, for example, in the memory cell array 6, the sense amplifier drive circuit 29 _0k supplies the sense amplifier drive signal lines 27 _0k and 28 _0k with the sense amplifier drive signals NSA _0k and PSA _0k , respectively. From the amplifier drive circuit 29 _{0 (k + 1)} , the sense amplifier drive signal lines 27 _{0 (k + 1)} and 28 _{0 (k + 1)} are connected to the sense amplifier drive signal N.
SA _{0 (k + 1)} and PSA _{0 (k + 1)} are supplied.

The sense amplifier drive circuit 29 _1k supplies the sense amplifier drive signal lines 27 _1k and 28 _1k with the sense amplifier drive signals NSA _1k and PSA _1k , respectively, and the sense amplifier drive circuit 29 _{1 (k + 1).} Are connected to the sense amplifier drive signal lines 27 _{1 (k + 1)} and 28 _{1 (k + 1).}
A _{1 (k + 1)} and PSA _{1 (k + 1)} are supplied.

[0020]

Generally, in a DRAM, in order to ensure stable operation of sense amplifiers, it is necessary to operate all sense amplifiers at substantially the same drive voltage. It is necessary to reduce the parasitic resistance of the sense amplifier drive signal line.

However, in recent years, in the DRAM, the size of the sense amplifier has become finer with the increase in capacity and miniaturization. Therefore, the sense amplifier drive signal line is
There is a problem that it is inevitable that the sense amplifier drive signal line has a large parasitic resistance, and it is difficult to ensure stable operation of the sense amplifier.

Therefore, in the DRAM shown in FIG. 7, for example, as shown in FIG. 9 as a representative of the portion of the memory cell array 6, each memory cell array portion has 16 rows,
It is divided into two groups of 16 rows of memory cell segments (in the memory cell array 6, a group of memory cell segments 26 ₀₀₀ to 260 _{FF and} a group of memory cell segments).
Divided into groups of segments 26 ₁₀₀ ~26 _1FF), 2 is divided in the extending direction of the sense amplifier drive signal line, by shortening a wiring length, so that to reduce the parasitic resistance.

However, the parasitic resistance of the sense amplifier drive signal line is still large and it is required to be smaller. In this case, connect the sense amplifier drive signal line to
If, for example, eight divisions can be made in the extending direction, the parasitic resistance of the sense amplifier drive signal line can be further reduced.

Here, the sense amplifier drive signal bus 30 ₀₀
~ 30 _0F , 30 ₁₀ ~ 30 _1F , 31 ₀₀ ~ 31 _0F , 31 ₁₀ ~
If the line width of 31 _1F can be made thinner than that of the present time, the sense amplifier drive signal line is extended in the extending direction by, for example, 8
It can be divided.

However, in order to supply a sufficient drive current to the sense amplifier, the sense amplifier drive signal bus lines 30 _00-
30 _0F , 30 ₁₀ to 30 _1F , 31 _{00 to} 31 _0F , 31 _{10 to} 3
The line width of 1 _1F cannot be made narrower than that of the present, and therefore, it is impossible to divide the sense amplifier drive signal line in its extending direction into, for example, eight divisions.

The problem of increasing the parasitic resistance of the sense amplifier drive signal line becomes a serious problem when a DRAM having a capacity of 64 Mbits or more, for example, a 256 Mbit DRAM is constructed. Has been requested.

In view of the above point, the present invention can reduce the parasitic resistance of the sense amplifier drive signal line, and assures stable operation of the sense amplifier even when the capacity is increased to 256 Mbits, for example. It is an object of the present invention to provide a DRAM that can be used.

[0028]

FIG. 1 is a diagram for explaining the principle of the present invention. A DRAM according to the present invention has a first sense amplifier drive signal extending in the Y-axis direction, for example, a sense amplifier drive signal NSA. Sense amplifier drive signal line 4 for supplying
4 and a second sense amplifier drive signal, for example, a sense amplifier drive signal line pair 43 including a sense amplifier drive signal line 45 for supplying a sense amplifier drive signal PSA is arranged in the X-axis direction orthogonal to the Y-axis direction. Memory cell array 4
The present invention is to improve DRAM in which the i-th and i + 1-th (where i = 1 and an odd number of i = 1 or more) sense amplifier drive signal line pairs 43 _i and 43 _{i + 1} are simultaneously selected.

In the DRAM according to the present invention, the outer portion 47 closer to the sense amplifier driving signal line 44 than the sense amplifier driving signal line 45 of the sense amplifier driving signal line pair 43 of the memory cell array 42 and orthogonal to the X-axis direction and the memory cell array. 42 of the sense amplifier drive signal line pair 43 than the sense amplifier drive signal line 44 of the sense amplifier drive signal line pair 43
To the outer portion 48 close to 5 and orthogonal to the X-axis direction,
The i-th and (i + 1) th sense amplifier drive signal line pairs 43 _i , 4
A sense amplifier drive circuit 46 _{(i + 1) / 2} for generating a sense amplifier drive signal NSA corresponding to 3 _{i + 1} and a sense amplifier drive circuit 49 for generating a sense amplifier drive signal PSA.
_{(i + 1) / 2} are arranged facing each other.

Then, again, the sense amplifier drive signal NS
The sense amplifier drive circuit 46 _{(i + 1) / 2} for generating A and the sense amplifier drive circuit 49 _{(i + 1) / 2} for generating the sense amplifier drive signal PSA are respectively located at the i-th and the i-th positions. Sense amplifier drive signal line pair 43 _i , 43
A sense amplifier drive signal bus 50 _{(i + 1) / 2} for supplying a sense amplifier drive signal NSA to the _{i + 1} sense amplifier drive signal lines 44 _i and 44 _{i + 1} and the i th and i + 1 th sense amplifier drive signal lines Sense amplifier drive signal line 4 of pair 43 _i , 43 _{i + 1}
A sense amplifier drive signal bus 51 _{(i + 1) / 2} for supplying the sense amplifier drive signal PSA to 5 _i and 45 _{i + 1} extends in parallel to the X-axis direction.

Numeral 52 is a sense amplifier drive signal bus 5
0 _{(i + 1) / 2} and the connection portion of the sense amplifier drive signal line 44 _i ,
Reference numeral 53 is a connection portion between the sense amplifier drive signal bus 50 _{(i + 1) / 2} and the sense amplifier drive signal line 44 _{i + 1} .

Further, 54 is a sense amplifier drive signal bus 5
Connection portion between 1 _{(i + 1) / 2} and the sense amplifier drive signal line 45 _i ,
Reference numeral 55 is a connection portion between the sense amplifier drive signal bus 51 _{(i + 1) / 2} and the sense amplifier drive signal line 45 _{i + 1} .

[0033]

In the present invention, the outer portion 4 of the memory cell array 42 is
A sense amplifier drive circuit 46 _{(i + 1) / 2} for generating a sense amplifier drive signal NSA and a sense amplifier drive circuit 49 _{(i + 1) / 2} for generating a sense amplifier drive signal PSA are opposed to 7 and 48, respectively. The sense amplifier driving circuits 46 _{(i + 1) / 2} and 49 _{(i + 1) / 2 from} the facing positions, respectively, and sense amplifier driving signal lines 44 _i and 44 _{i + 1} , respectively.
To the sense amplifier drive signal bus 50 _{(i + 1) / 2} for supplying the sense amplifier drive signal NSA and the sense amplifier drive signal bus 51 for supplying the sense amplifier drive signal PSA to the sense amplifier drive signal lines 45 _i and 45 _{i + 1. (i + 1) / 2} is extended in parallel with the X-axis direction, and these sense amplifier drive signal bus lines 50
_{(i + 1) / 2} and 51 _{(i + 1) / 2} are arranged to face each other in a straight line.

As a result, more sense amplifier drive signal buses can be arranged on the memory cell array 42 than in the conventional case. Therefore, the sense amplifier drive signal lines are divided into shorter lengths than in the conventional case, and the sense amplifier drive signal lines are divided. The parasitic resistance of the line can be reduced.

Further, as shown in FIG. 2, in addition to the sense amplifier drive circuits 46 _{(i + 1) / 2} and 49 _{(i + 1) / 2} , the outside portions 47 and 48 of the memory cell array 42 are respectively provided. Sense amplifier drive circuit 56 for generating sense amplifier drive signal NSA
_{(i + 1) / 2} and the sense amplifier drive circuit 57 _{(i + 1) / 2} for generating the sense amplifier drive signal PSA are arranged to face each other,
These sense amplifier drive circuits 46 _{(i + 1) / 2} , 49 _{(i + 1) / 2}
From opposing positions, respectively, a sense amplifier drive signal line 44 _i, 44 _i + ₁ and supplies the sense amplifier drive signal NSA to the sense amplifier drive signal bus 58 _{(i + 1) / 2} and the sense amplifier drive signal line 45 _i , 45 _{i + 1} to supply the sense amplifier drive signal PSA to the sense amplifier drive signal bus 59
_{(i + 1) / 2} can be configured to extend in parallel with the X-axis direction. In such a configuration, the sense amplifier drive signal lines 44 _i , 44 _{i + 1} , 45 _i , The voltage drop of the sense amplifier drive signal at 45 _{i + 1} can be made smaller than that shown in FIG.

In FIG. 2, reference numeral 60 denotes the sense amplifier drive signal bus 58 _{(i + 1) / 2} and the sense amplifier drive signal line 4.
4 _i is a connecting portion, 61 is a sense amplifier drive signal bus 58
_{(i + 1) / 2} is a connection portion between the sense amplifier drive signal line 44 _{i + 1} .

Further, 62 is a sense amplifier drive signal bus 5
9 _{(i + 1) / 2} and the connection portion of the sense amplifier drive signal line 45 _i ,
Reference numeral 63 is a connection portion between the sense amplifier drive signal bus 59 _{(i + 1) / 2} and the sense amplifier drive signal line 45 _{i + 1} .

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 3 to 6 by taking the case where the present invention is applied to a 64-Mbit DRAM as in the conventional DRAM shown in FIG. To do.

FIG. 3 is a schematic plan view showing an embodiment of the present invention, in which 64 is a chip body constituting a DRAM, and 65 is a chip body.
68 are row decoders, and 69 to 76 are memory cell arrays having a scale of 8 Mbits.

Numerals 77 to 84 are sense amplifier driving circuit rows in which sense amplifier driving circuits for generating the sense amplifier driving signal NSA are arranged, and 85 to 92 are arranged in the sense amplifier driving circuit for generating the sense amplifier driving signal PSA. It is a sense amplifier drive circuit array formed by.

FIG. 4 is a schematic plan view showing the configuration of the memory cell array 69 and the sense amplifier drive circuit rows 77 and 85, which are 86 _{000 to} 86 00 _F and 86 _{030 to} 86.
_03F , 86 _{700 to} 86 _70F , 86 _{730 to} 86 _73F are memory cell segments, and in this embodiment also, memory cell segments of 32 rows and 16 columns are provided for each memory cell array.

Also in FIG. 4, each subscript of the reference numeral represents each character in hexadecimal notation, and as in the case of FIG. 9, it indicates the matrix-like position of the element to which the reference numeral is attached. It has been described in.

Further, 87 _{00 to} 870 _0F , 87 _{70 to} 87 _7F are sense amplifier drive signal lines for the sense amplifier drive signal NSA, and 88 _{00 to} 880 _0F , 88 _{70 to} 88 _7F are sense amplifier drive signal PSA senses. It is an amplifier drive signal line.

89 _{00 to} 89 ₀₇ and 89 _{70 to} 89 ₇₇ are sense amplifier drive signals NSA ₀₀ to NSA ₀₇ and NSA ₇₀ to.
Sense amplifier drive circuit for generating NSA ₇₇ , 90 _00-9
0 ₀₇ , 90 _{70 to} 90 ₇₇ are sense amplifier drive signals PSA ₀₀
˜PSA ₀₇ , PSA ₇₀ ˜PSA ₇₇ .

Also, 91₀₀~ 91₀₇Drive sense amplifier
Signal line 87₀₀~ 87_0FSense amplifier drive signal NSA₀₀
~ NSA₀₇For supplying a sense amplifier drive signal bus, 91
₇₀~ 91₇₇Is a sense amplifier drive signal line 87₇₀~ 87_7FTo
Sense amplifier drive signal NSA ₇₀~ NSA₇₇Supply
It is a sense amplifier drive signal bus.

Also, 92₀₀~ 92₀₇Drive sense amplifier
Signal line 88₀₀~ 88_0FSense amplifier drive signal PSA₀₀
~ PSA₀₇92 for supplying a sense amplifier drive signal bus
₇₀~ 92₇₇Is a sense amplifier drive signal line 88₇₀~ 88_7FTo
Sense amplifier drive signal PSA ₇₀~ PSA₇₇Supply
It is a sense amplifier drive signal bus.

The sense amplifier drive signal bus 91 _00-
91 ₀₇ , 91 _{70 to} 91 ₇₇ , 92 _{00 to} 92 ₀₇ , 92 _{70 to} 9
2 ₇₇ is a sense amplifier drive signal line 87 _{00 to} 870 _0F , 87 _{70
~87 7F, 88 00 ~88 0F,} 88 70 ~88 are extended at the top of _7F.

Here, the sense amplifier drive circuits 89 ₀₀ to 8
9 ₀₇ , 89 _{70 to} 89 ₇₇ and sense amplifier drive circuit 90 ₀₀
˜90 ₀₇ and 90 ₇₀ ˜90 ₇₇ are arranged so as to face each other with the memory cell array 69 interposed therebetween.

Further, the sense amplifier drive signal bus 91 _00-
91 ₀₇ , 91 _{70 to} 91 ₇₇ and sense amplifier drive signal buses 92 _{00 to} 92 ₀₇ , 92 _{70 to} 92 ₇₇ are respectively sense amplifier drive circuits 89 _{00 to} 89 ₀₇ , 89 _{70 to} 89 ₇₇ and sense amplifier drive circuit 90. _{00 to} 90 ₀₇ and 90 _{70 to} 90 ₇₇ are linearly extended so as to face each other from the facing positions.

In addition, sense amplifier drive circuits 89 _{00 to} 89
₀₇ , 89 _{70 to} 89 ₇₇ are configured, for example, as shown in FIG. In the figure, 93 is a precharge voltage line for supplying a precharge voltage VPR, 94 is an nMOS transistor whose ON / OFF is controlled by a reset signal R, 9
5 is turned on and off by the sense amplifier drive circuit activation signal φ
It is an nMOS transistor whose FF is controlled.

Further, the sense amplifier drive circuits 90 _{00 to} 90
₀₇ , 90 _{70 to} 90 ₇₇ are configured as shown in FIG. 6, for example. In the figure, reference numeral 96 is V for supplying the power supply voltage VCC
CC power line, 97 is ON and OF by reset signal / R
F is a pMOS transistor controlled by F, 98 is a pMOS transistor whose ON / OFF is controlled by a sense amplifier drive circuit activation signal / φ, and 99 is a precharge voltage line for supplying a precharge voltage VPR.

Here, in this embodiment, the sense amplifier is
Sense amplifier drive circuit 89 for generating a drive signal NSA
₀₀~ 89₀₇, 89₇₀~ 89₇₇And sense amplifier drive signal
Sense amplifier drive circuit 90 for generating PSA₀₀~ 9
0₀₇, 90₇₀~ 90₇₇The memory cell array
These are opposed to each other with the 69 interposed therebetween,
9 ₀₀~ 89₀₇, 89₇₀~ 89₇₇And sense amplifier drive times
Road 90₀₀~ 90₀₇, 90₇₀~ 90₇₇Opposite position
Respectively, the sense amplifier drive signal bus 91₀₀~ 91
₀₇, 91₇₀~ 91₇₇And sense amplifier drive signal bus 92
₀₀~ 92₀₇, 92₇₀~ 92₇₇Straight to face
Memory cells in 32 rows and 16 columns.
Figure showing the number of sense amplifier drive signal buses in a segment
It can be doubled in the case of the DRAM shown in FIG.

As a result, 8 memory cell segments are provided.
The sense amplifier drive signal line can be divided into eight groups of rows and 16 columns, and the sense amplifier drive signal line can also be divided into eight in the extending direction, and the parasitic resistance of the sense amplifier drive signal line can be reduced.

By the way, in the case of the DRAM shown in FIG. 7, the length of one sense amplifier drive signal line is 1075.2 μm,
If the line width is 5 μm and the sheet resistance is 0.35Ω / □,
The parasitic resistance is 1075.2 × 0.35 / 5 = 75.2
It becomes 64Ω.

On the other hand, in the case of the DRAM of this embodiment, the length of one sense amplifier drive signal line is 1075.
2/4 = 268.8 μm, so if the line width is 5 μm and the sheet resistance is 0.35Ω / □, the parasitic resistance is
268.8 × 0.35 / 5 = 18.816Ω, which is shown in FIG.
It is 1/4 that of the conventional DRAM shown in FIG.

The length of one sense amplifier drive signal bus bar is 9000 μm, the line width is 10 μm, and the sheet resistance is 0.9 μm.
If it is 04Ω, its parasitic resistance is 9000 × 0.04.
/ 10 = 36Ω.

Therefore, the total parasitic resistance of the sense amplifier drive signal bus and the sense amplifier drive signal line is 75.264 + 36 = 111.264 in the case of the DRAM shown in FIG.
Ω, in the case of this embodiment, 18.816 + 36 = 54.816
.OMEGA., Which is half that of the DRAM shown in FIG. 7 in the case of the present embodiment.

As described above, according to this embodiment, the total parasitic resistance of the sense amplifier drive signal line can be reduced to 1/4 of that of the DRAM shown in FIG. 7, and the sense amplifier having a uniform voltage can be used. The drive signals NSA and PSA can be supplied, and stable operation can be ensured.

[0059]

As described above, according to the present invention, the i-th,
The i + 1th sense amplifier drive signal line pair (43_iFour
Three_{i + 1}) First sense amplifier drive signal line (44_i, 44
_{i + 1}) Supplies the first sense amplifier drive signal (NSA)
Sense amplifier drive signal bus (50 _{(i + 1) / 2}) And the first
i, i + 1th sense amplifier drive signal line pair (43_iFour
Three_{i + 1}) Second sense amplifier drive signal line (45_i, 45
_{i + 1}) To the second sense amplifier drive signal (PSA)
Sense amplifier drive signal bus (51_{(i + 1) / 2}) Opposed
Because it is made to extend in a straight line like
On the memory cell array (42) as compared with the conventional case.
You can arrange many sense amplifier drive signal busbars.
Therefore, the sense amplifier drive signal line is shorter than in the past.
To reduce the parasitic resistance of the sense amplifier drive signal line
It is possible to increase the capacity, for example, 256 Mbit
Stabilize the sense amplifier even when increasing the capacity.
It is possible to secure the desired operation.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating the principle of the present invention.

FIG. 3 is a schematic plan view showing a main part of an embodiment of the present invention.

FIG. 4 is a schematic plan view showing a configuration of a memory cell array and a sense amplifier drive circuit row that constitute an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a sense amplifier drive circuit that generates a sense amplifier drive signal NSA.

FIG. 6 is a circuit diagram showing a configuration example of a sense amplifier drive circuit that generates a sense amplifier drive signal PSA.

FIG. 7 is a schematic plan view of an example of a conventional DRAM.

FIG. 8 is a schematic plan view showing a configuration of a memory cell array forming the conventional DRAM shown in FIG.

9 is a schematic plan view showing a configuration of a memory cell array and a sense amplifier drive circuit which form the conventional DRAM shown in FIG. 7. FIG.

10 is a circuit diagram showing a configuration of a memory cell segment that constitutes the conventional DRAM shown in FIG. 7. FIG.

[Explanation of symbols]

42 memory cell array 43 _i , 43 _{i + 1} sense amplifier drive signal line pair 44 _i , 44 _{i + 1} , 45 _i , 45 _{i + 1} sense amplifier drive signal line 46 _{(i + 1) / 2} , 49 _{(i + 1) ) / 2} sense amplifier drive circuit 50 _{(i + 1) / 2} , 51 _{(i + 1) / 2} sense amplifier drive signal bus

Claims (2)

[Claims] 1. A first sensor extending in a first direction (Y).
The first sense amplifier that supplies the amplifier drive signal (NSA).
Drive signal line (44) and second sense amplifier drive signal
Signal (PSA) for supplying the second sense amplifier drive signal line
The sense amplifier drive signal line pair (43) consisting of (45)
In a second direction (X) orthogonal to the first direction (Y),
A memory cell array (42) arranged in rows,
The (i + 1) th (where i = 1 or more odd number) sense amplifier drive
Motion signal line pair (43_i, 43_{i + 1}) At the same time, the first and second
The sense amplifier drive signals (NSA, PSA) of
Dynamic RAM, the memory cell array
(42) The sense amplifier drive signal line pair (43)
The first sensor is connected to the second sense amplifier drive signal line (45).
The second direction closer to the amplifier drive signal line (44)
A first outer portion (47) orthogonal to (X) and said memory
The sense amplifier drive signal line pair of the cell array (42)
From the first sense amplifier drive signal line (44) of (43)
Also in front of the side close to the second sense amplifier drive signal line (45)
A second outer portion (48) orthogonal to the second direction (X).
To the i-th and i + 1-th sense amplifier drive signals, respectively.
Line pair (43_i, 43_{i + 1}) Corresponding to the first sense
Drive circuit for generating a drive signal (NSA)
(46_{(i + 1) / 2}) And the second sense amplifier drive signal (P
Sense amplifier drive circuit (4)
9_{(i + 1) / 2}) Are arranged to face each other, and the first sense
Drive circuit for generating a sense amplifier that generates a pump drive signal (NSA)
Road (46_{(i + 1) / 2}) And the second sense amplifier drive signal
Signal (PSA) generating sense amplifier drive circuit (49
_{(i + 1) / 2}), The i-th and
The i + 1th sense amplifier drive signal line pair (43_iFour
Three_{i + 1}) First sense amplifier drive signal line (44 _i, 44
_{i + 1}) To the first sense amplifier drive signal (NSA)
Supply sense amplifier drive signal bus (50_{(i + 1) / 2}) And
And the i-th and (i + 1) th sense amplifier drive signal line pairs (4
Three_i, 43_{i + 1}) Second sense amplifier drive signal line (45
_i, 45_{i + 1}) To the second sense amplifier drive signal (PS
A) for supplying a sense amplifier drive signal bus (51)
_{(i + 1) / 2}) Extending parallel to the second direction (X)
Dynamic RAM that is characterized by 2. A first sense amplifier drive signal line (44) for supplying a first sense amplifier drive signal (NSA) extending in a first direction (Y) and a second sense amplifier drive signal (44). The sense amplifier drive signal line pair (43) including the second sense amplifier drive signal line (45) for supplying PSA) is arranged in the second direction (X) orthogonal to the first direction (Y). The memory cell array (42) is provided, and the first and second sense amplifier drive signal line pairs (43 _i , 43 _{i + 1} ) of the i-th and the i + 1-th (where i = 1 or more odd numbers) are simultaneously provided.
In the dynamic RAM to which the sense amplifier drive signal (NSA, PSA) is supplied, the second sense amplifier drive signal line (45) of the sense amplifier drive signal line pair (43) of the memory cell array (42) The sense amplifier drive signal line pair (43) of the memory cell array (42) and the first outer portion (47) orthogonal to the second direction (X) on the side closer to the first sense amplifier drive signal line (44). Second outer portion (48) orthogonal to the second direction (X) closer to the second sense amplifier drive signal line (45) than the first sense amplifier drive signal line (44).
And the first and second sense amplifiers that generate the first sense amplifier drive signal (NSA) corresponding to the i-th and i + 1th sense amplifier drive signal line pairs (43 _i , 43 _{i + 1} ) respectively. Drive circuit (46 _{(i + 1) / 2} , 56 _{(i + 1) / 2} ) and first and second generating second sense amplifier drive signal (PSA)
Sense amplifier drive circuit (49 _{(i + 1) / 2} , 57 _{(i + 1) / 2} )
Are arranged so as to face each other, and a first sense amplifier drive circuit (46 _{(i + 1) / 2} ) for generating the first sense amplifier drive signal (NSA) and a second sense amplifier drive signal (PSA). ) From the first sense amplifier drive circuit (49 _{(i + 1) / 2} ) facing each other from the i-th and _{(i + 1)} th sense amplifier drive signal line pairs (43 _i ,
43 _{i + 1} ) of the first sense amplifier drive signal lines (44 _i , 4
4 _{i + 1} ) to the first sense amplifier drive signal (NSA)
For supplying a first sense amplifier drive signal bus (50
_{(i + 1) / 2} ) and the second sense amplifier drive signal line (45 _i , 45 _{i + 1} ) of the _{i- th} and ( _{i + 1} ) _th sense amplifier drive signal line pair (43 _i , 43 _{i + 1} ). The first sense amplifier drive signal bus line (51 _{(i + 1) / 2} ) for supplying the second sense amplifier drive signal (PSA) is extended in parallel to the second direction (X), and A second sense amplifier drive circuit (5) for generating a first sense amplifier drive signal (NSA).
6 _{(i + 1) / 2} ) and the second sense amplifier drive signal (P
Second sense amplifier drive circuit (57) for generating SA)
_{(i + 1) / 2} ) from the opposite positions,
The i + 1th sense amplifier drive signal line pair (43 _i , 4
3 _{i +1} ) first sense amplifier drive signal lines (44 _i , 44)
_{i + 1} ) to the second sense amplifier drive signal bus (58 _{(i + 1} ) which supplies the first sense amplifier drive signal (NSA) to
_{) / 2} ) and the second sense amplifier drive signal line (45 _i , 45 _{i + 1} ) of the _{i- th} and ( _{i + 1} ) _th sense amplifier drive signal line pair (43 _i , 43 _{i + 1} ) to the second A second sense amplifier drive signal bus line (59 _{(i + 1) / 2} ) for supplying a sense amplifier drive signal (PSA) is extended in parallel to the second direction (X). Dynamic RAM.