JPH06274318A - High speed arithmetic unit - Google Patents

Abstract

PURPOSE:To simultaneously execute an arithmetic operation including the arithmetic operator of more than two on a high speed arithmetic unit in a processor in a computer system. CONSTITUTION:Registers 21, 22, 22,..., and 2n temporarily hold numerical data D1, D2,..., and Dm constituting bit data of four bits and the like, for example, received from a storage means 10. An allocation means 30 allocates bit data BD for respective pieces of numerical data D1, D2,..., and D, outputted from the registers 21, 22,... and 2n. An addition means 40 executes addition at every bit data BD allocated to the allocation means 30, and outputs an arithmetic result AD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed arithmetic unit for a computer system, and more particularly to a high speed arithmetic unit for performing arithmetic operations in a central processing unit (CPU) at high speed.

In computer systems such as workstations and personal computers, arithmetic operations such as relative address operations are required not only in numerical calculation processing but also in various processing.

Among such arithmetic operations, there are many cases where two or more arithmetic operators (+,-, x, ÷) appear.
In order to increase the speed of the entire computer system, it is required to increase the speed of arithmetic operations including two or more arithmetic operators.

[0004]

2. Description of the Related Art An arithmetic unit in a processor in a conventional computer system can perform only one arithmetic operation at a time. Therefore, when performing an arithmetic operation including two or more four arithmetic operators, the microprogram of the control device
Arithmetic operations were performed by dividing each of the four arithmetic operators.

For example, when performing an arithmetic operation "a + b + c + d" including three addition operators, first "a + b" is performed to "e", then "e + c" is performed to "f", and finally "f + d". To obtain the result of the arithmetic operation.

[0006]

However, in the method of performing arithmetic operations by dividing each of the four arithmetic operators, it takes time as the number of arithmetic operators increases, so that the speed of the entire computer system cannot be increased. There was a point.

Further, the large-scale parallel computer system has a problem that it is expensive although it can perform arithmetic operations including two or more arithmetic operators at once. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-speed arithmetic device that is inexpensive and speeds up by simultaneously performing arithmetic operations including two or more four arithmetic operators. .

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention for achieving the above object. The high-speed arithmetic device of the present invention comprises a storage means 10, registers 21, 22, ..., 2
n, allocation means 30 and addition means 40.

Registers 21, 22, ..., 2n receive numerical data D1, D2 ,.
Hold Dm temporarily. The allocating means 30 allocates the bit data BD to each of the numerical data D1, D2, ..., Dm output from the registers 21, 22 ,. The adding means 40 performs addition for each bit data BD allocated by the allocating means 30 and outputs the arithmetic result AD.

If necessary, a memory management means is provided between the storage means 10 and the registers 21, 22, ..., 2n, and the registers 21, 22 ,.
A complement circuit or a partial product calculation means may be further provided between 0 and 0.

The memory management means are registers 21, 22,
... Numerical data D1, D2, ... according to the number of 2n
, Dm, and manages the input / output of data necessary for arithmetic operations such as storing the arithmetic result AD output from the adding means 40 in the storage means 10. The complement circuit obtains a two's complement corresponding to each of the registers 21, 22, ..., 2n. The partial product calculation method is Booth's method (Booth
algorithm)) to obtain the partial product.

[0012]

Operation: Numerical data D1, D received from the storage means 10
2, ..., Dm to registers 21, 22, ..., 2n
Is temporarily held, and the allocating means 30 sets the numerical data D1, D
Bit data BD is allocated to each of 2, ..., Dm. After that, the adding means 40 performs addition for each bit data BD allocated by the allocating means 30 and outputs the arithmetic result AD.

The memory management means is composed of the registers 21 and 2.
2, ..., 2n according to the number of numerical data D1, D2
, Dm are output, and the input / output of data necessary for arithmetic operation such as storing the arithmetic result AD output from the adding means 40 in the storage means 10 is managed. For this reason,
The arithmetic operation can be performed according to the number of numerical data D1, D2, ..., Dm without being limited by the number of registers 21, 22 ,.

The complement circuit is composed of registers 21, 22, ...
.., 2n is calculated corresponding to every 2n, so that desired arithmetic operation can be performed even when the numerical data D1, D2, ..., Dm are negative numbers. Since the partial product calculating means obtains the partial product by Booth's method, the product-sum calculation can be performed at high speed.

The booth method will be described below.
First, regarding two variables X and Y whose numerical values are represented by two's complements, the variable X is a multiplicand and the variable Y is a multiplier. Note that m = 2n (n is a natural number) and y _i is “0”.
Alternatively, an integer value of “1” (0 <i ≦ m), y _i = 0 (i ≦ m
0) and y _i = 1 (i> m), the variable Y is defined in the following formulas (1a) to (1c).

[0016]

[Equation 1]

Here, the expression (1a) is an expression when the bit string of a binary number is represented, the expression (1b) is an expression when the expression (1a) is represented by a decimal number, and the expression (1c) is an expression of the expression (1b). The following shows the formula when expressed by the symbol sigma (Σ).

At this time, the variable Y in the equation (1c) is
The equations can be transformed into the following equations (2a) to (2c).

[0019]

[Equation 2]

When i = j-1 in the equation (2c), the following equation (3) is established.

[0021]

[Equation 3]

Further, in the equation (3), y _i = 0 (i
Considering ≦ 0, the equations can be transformed into the following equations (4a) to (4c).

[0023]

[Equation 4]

Therefore, the multiplication result of the variable X and the variable Y is expressed by the following equations (5a) and (5b).

[0025]

[Equation 5]

Thus, the result of putting the integer value of "0" or "1" into each of the variables (y _2k-1 , y _2k , y _{2k + 1} ) in the above equation (5b) is shown in FIG. 15 (B). The truth table is based on the booth method shown in.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the basic configuration of the processor in the computer system that implements the present invention. The processor is roughly composed of a control device 100 and a high speed arithmetic device 200.

The control device 100 includes a sequencer.
r) 101, micro program memory (micro progra
m memory) 102 and micro instruction register (micro in
(struction resister) 103. The sequencer 101 receives the command data CD from the main storage device as the storage means 10 shown in FIG. 1 connected to the data bus DB and other various devices, and the operation result AD from the high-speed operation device 200 described later, and the microprogram It is a functional module that generates the address signal of the memory 102 in synchronization with the clock signal CLK. The storage capacity of the microprogram memory 102 is restricted by the bit width of the address signal generated by the sequencer 101. Further, the micro program memory 102 receiving the address signal outputs a micro instruction (that is, data of a memory address corresponding to the address signal). Further, the microinstruction register 103 that has received the microinstruction changes the clock signal CL.
The control signal CS1 for the next control processing is sent to the sequencer 101 in synchronization with K, and the control signal CS2 for the arithmetic operation and the control bus C are sent to the high-speed arithmetic device 200 described later.
It outputs a control signal CS3 to various devices connected to B.

The high-speed arithmetic unit 200 includes a register group 20.
1, an allocating unit 202 and an adding unit 203. The register group 201 is the registers 21 and 2 shown in FIG.
2, ..., 2n, a predetermined data bit width of, for example, 4 bits for the numerical data received via the data bus DB, and a predetermined data bit width of, for example, 2 bits for the control signal CS2 from the control device 100. Control bit width and hold temporarily. The allocating means 202 corresponds to the allocating means 30 shown in FIG. 1, receives the data held in the register group 201, and allocates bit data for each bit of the data. Further, the adding means 203 corresponds to the adding means 40 shown in FIG. 1, performs addition for each bit data allocated by the allocating means 202, and outputs the arithmetic result to a desired device via the address bus AB and the data bus DB. Output.

Next, a specific structure and operation of the high speed arithmetic device of the present invention will be described. In order to simplify the explanation, the number of registers in the register group 201 shown in FIG.
Numerical data received via the data bus DB is 4
The description will be given assuming that the data bit width of the bit is set, and the control signal CS2 received from the control device 100 is the control bit width of 2 bit.

FIG. 3 is a diagram showing a first embodiment of the present invention. In the figure, the high-speed arithmetic unit is shown as a register 21a,
22a, 23a, 24a, allocation means 30a, and addition means 40a.

The register 21a is the register 21 shown in FIG.
And numerical data D1 having a data bit width of 4 bits
a and a control signal CS21 having a control bit width of 2 bits are temporarily held. Similarly, registers 22a, 23a,
Reference numeral 24a corresponds to the registers 22, 23 and 24 shown in FIG. 1 and has numerical data D2a and D having a data bit width of 4 bits.
3a, D4a and a control signal C having a control bit width of 2 bits
Each of S22, CS23, and CS24 is temporarily held.

The allocating means 30a is the allocating means 30 shown in FIG.
Corresponding to the registers 21a, 22a, 23a, 24
Each of the numerical data D1a, D2a, held in a
D3a, D4a and control signals CS21, CS22, CS
Numerical data D1 in response to data such as 23 and CS24
Eight bit data BD1, BD2, ..., BD8 are allocated for each bit of a, D2a, D3a, and D4a. The specific configuration of the allocating means 30a will be described in detail with reference to FIG.

The adding means 40a is the adding means 40 shown in FIG.
, BD8, which is allocated by the allocating means 30a, is added for each of the 8 bit data BD1, BD2, ..., BD8, and arithmetic results AD1, AD2 each consisting of 9 bits are added.
..., AD9 is output. The specific configuration of the adding means 40a will be described in detail with reference to FIG.

FIG. 4 is a diagram showing the structure of the allocating means 30a shown in FIG. In the figure, the allocating means 30a is a MUX.
(MUltipleXer; Multiplexer) 31, 32, 33, 3
4 elements. In addition, MUX 31, 32,
Since both 33 and 34 have the same structure, M is used here.
The UX31 will be described.

The MUX 31 receives the numerical data D1a and the control signal CS21 and allocates eight bit data BD1, BD2, ..., BD8 having a data bit width of 4 bits.

Specifically, for the numerical data D1a having a data bit width of 4 bits, the numerical data D1a4 whose upper 4 bits are "0", the upper 2 bits are "0", and the numerical data D1a is in the upper bit direction. Numerical data D1a6 shifted by 2 bits to and numerical data D1a8 obtained by shifting numerical data D1a by 4 bits in the upper bit direction
Receive. For example, if the numerical data D1a is "1101", the numerical data D1a4 is "000011".
01 ”, the numerical data D1a6 is“ 00110100 ”
In addition, the numerical data D1a8 becomes “11010000”.

Further, the control signal CS21 having a control bit width of 2 bits is received, and the numerical data D1a4, the numerical data D1a6 and the numerical data D are received in accordance with the control signal CS21.
One of the numerical data is selected from 1a8 and 1 bit of each of the 8 bit data BD1, BD2, ..., BD8 is output.

Thus, each of the MUXs 31, 32, 33, 34 has eight bit data BD1, BD2, ...
.., each one bit of BD8 is output, and bit data BD1, BD2, ..
., Output as BD8. For example, MUX31,3
The least significant bits of 2, 33 and 34 are combined and output as bit data BD1, and the second least significant bits are combined and output as bit data BD2. Thereafter, similarly, the most significant bits are combined and output as bit data BD8.

Next, the adding means 40a shown in FIG. 3 will be described with reference to FIGS. FIG. 5 shows addition means 4
It is a figure which shows the structure of 0a. FIG. 6 is a diagram showing the relationship between the number of input bits and the number of 1-bit full adders. Figure 7
7A and 7B are diagrams showing connection relations of 1-bit full adders corresponding to the number of input bits in FIG. 6, where 3-bit input is shown in FIG. 7A and 4-bit input is shown in FIG. 7B. 7C, 6-bit input is shown in FIG. 7C, and 7-bit input is shown in FIG. 7D.
In the case of bit input, FIG. 7E shows the case of 9-bit input, and FIG. 7F shows the case of 10-bit input. FIG. 8 is a diagram showing a truth table of the 1-bit full adder.

In FIG. 5, the adding means 40a is composed of the elements of the adder arrays 41 and 42 and the carry lookahead adder 43. The adder string 41 is bit data B of 4 bits each.
Eight bit adders 411, 41 that receive D1, BD2, ..., BD8 and perform 1-bit full addition to output 2-bit first addition data and 1-bit first carry data
2, ..., 418.

The adder train 42 includes eight bit adders 42.
1, 422, ..., 428. Specifically, the bit adder 421 receives the 2-bit first addition data output from the bit adder 411, performs 1-bit full addition, and performs the 1-bit second addition data and the 1-bit second addition data.
Output carry data. The bit adder 42
The 1-bit second addition data output from 1 becomes the 1-bit arithmetic result AD1.

The bit adder 422 receives the 3-bit data of the 1-bit first carry data output from the bit adder 411 and the 2-bit first addition data output from the bit adder 412. 1-bit full addition is performed and 1-bit second addition data and 1-bit second carry data are output. Further, the bit adder 423 receives the 3-bit data of the 1-bit first carry data output from the bit adder 412 and the 2-bit first addition data output from the bit adder 413, and receives the entire 1-bit data. Addition is performed and 1-bit second addition data and 1-bit second addition data
Output carry data.

Similarly, the bit adders 424, 425, ...
.., 428 are respectively bit adders 413, 41
, ..., 417 1-bit first carry data and bit adders 414, 415 ,.
It receives 3-bit data from the 2-bit first addition data output from 8 and performs 1-bit full addition, and outputs 1-bit second addition data and 1-bit second carry data.

The carry look-ahead adder 43 receives the 1-bit addition data and the 1-bit carry data output from the adder array 42 and performs bit slicing to obtain 8-bit arithmetic results AD2, AD3 ,. ., Outputs AD9. Specifically, the 1-bit second carry data output from the bit adder 421 and the 1-bit second addition data output from the bit adder 422 are bit-sliced to obtain a 1-bit arithmetic result. Output AD2. Further, it receives the 1-bit second carry data output from the bit adder 422 and the 1-bit second addition data output from the bit adder 423, performs bit slicing, and outputs a 1-bit arithmetic result AD3. To do.

Similarly, the bit adders 423, 424, ...
.., 428, 1-bit second carry data and 1-bit second adder data output from bit adders 423, 424 ,. Bit arithmetic result AD4, A
D5, ..., AD9 are output.

As described above, by using the carry look-ahead adder 43 composed of the logic circuit, the propagation time for carry is shortened, and thus the arithmetic operation can be performed at higher speed.

In FIG. 6, the relationship table 400 is shown in FIG.
6 is a table showing the relationship between the number of input bits in the 16 bit adders 411 to 428 and the like shown in FIG. 1, the number of 1-bit full adders, the number of addition data bits, and the number of carry bits.

In the relationship table 400, from the left side of the drawing, the number of input bits 401 is shown in the first column, the number of 1-bit full adders 402 is shown in the second column, and the number of bits of added data 403 is shown in the third column. The number of carry bits 404 is shown in the fourth column.

For example, the 2-bit input bit adder 421 shown in FIG. 5 corresponds to 405 rows, and the 3-bit input bit adders 422, 423, ..., 428 correspond to 400a row. In both cases, the number of 1-bit full adders 402 is "1", the number of bits 403 of addition data is "1", and the number of carry bits 404 is "1".

Similarly, the 4-bit input bit adders 411, 412, ..., 418 shown in FIG. 5 correspond to the 400b row, and the number 402 of 1-bit full adders is "1". The number of bits 403 of is "2", and the number of carry bits 404 is "1". In this way, the relation table 400 shows the number of output bits of the bit adder corresponding to the number of input bits.

FIG. 7 shows 400 of the relationship table 400.
Row a, 400b, 400c, 400d, 400e
It is a figure which shows the connection relation of the 1-bit full adder corresponding to a row and 400f row. Hereinafter, each drawing of FIGS. 7A to 7F will be described.

In FIG. 7A, 4 of the relation table 400 is used.
The 1-bit full adder 501 is connected corresponding to the 00a row. Specifically, the bit data i0, i1, i2
1-bit full adder 501 receives the 3-bit data of
The sum data s and the carry data co are output. If the number of input bits is 2 bits, for example, the bit data i2
Forcibly enter "0".

In FIG. 7B, 4 in the relation table 400
The 1-bit full adder 502 is connected corresponding to the 00b row. Specifically, the bit data i0, i1, i2
1-bit full adder 502 receives the 3-bit data of
The sum data s0 and the carry data c0 are output, and the bit data i3 is output as it is as the sum data s1.

In FIG. 7C, 4 of the relation table 400 is used.
1-bit full adders 503 and 504 corresponding to row 00c
Is connected. Specifically, the bit data i0, i
The 1-bit full adder 503 receives the 3-bit data 1 and i2 and outputs the sum data s0 and the carry data c0. The 1-bit full adder 504 receives the 3-bit data i3, i4 and i5. The sum data s1 and the carry data c1 are output. When the number of input bits is 5, for example, “0” may be forcibly input to the bit data i5.

In FIG. 7D, 4 of the relation table 400 is used.
1-bit full adders 505 and 506 corresponding to row 00d
Is connected. Specifically, the bit data i0, i
The 1-bit full adder 505 receives the 3-bit data 1 and i2 and outputs the sum data s0 and the carry data c0, and the 1-bit full adder 506 receives the 3-bit data i3, i4 and i5. The sum data s1 and the carry data c1 are output, and the bit data i7 is output as it is as the sum data s2.

In FIG. 7E, 4 of the relation table 400 is used.
1-bit full adders 507 and 50 corresponding to row 00e
8,509 connections are made. Specifically, the 1-bit full adder 507 receives the 3-bit data of the bit data i0, i1, i2, outputs the sum data s0 and the carry data c0, and outputs the 3-bit data of the bit data i3, i4, i5. The 1-bit full adder 508 receives the sum data s1 and the carry data c1, and outputs the bit data i6, i7,
The 1-bit full adder 509 receives the 3-bit data of i8 and outputs the sum data s2 and the carry data c2. When the number of input bits is 8 bits, for example, “0” may be forcibly input to the bit data i8.

In FIG. 7F, 4 of the relationship table 400 is used.
1-bit full adders 510, 51 corresponding to 00f row
1, 512 connections are made. Specifically, the 1-bit full adder 510 receives the 3-bit data of the bit data i0, i1, i2, outputs the sum data s0 and the carry data c0, and outputs the 3-bit data of the bit data i3, i4, i5. The 1-bit full adder 511 receives the sum data s1 and the carry data c1, and outputs the bit data i6, i7,
The 1-bit full adder 512 receives the 3-bit data of i8 and outputs the sum data s2 and the carry data c2. The bit data i9 is directly output as the sum data s3.

FIG. 8 shows the 1-bit full adder 50 shown in FIG.
A truth table 600 of 1,502, ..., 512 is shown.
The truth table 600 includes an input 601 in the left column of the drawing and an output 602 in the right column of the drawing. Input 601 is first from the left side of the drawing.
The column shows the bit data inputted to the input terminal a, the second column shows the bit data inputted to the input terminal b, and the third column shows the bit data inputted to the input terminal ci. In the output 602, the bit data of the sum data s is shown in the first column from the left side of the drawing, and the bit data of the carry data co is shown in the second column.

For example, in line 603, bit data "0" is input to the input terminal a, and the input terminal b and the input terminal c are input.
When bit data “1” is input to i, sum data s
Bit data "0" of the carry data co is output.

FIG. 9 is a diagram showing another configuration of the adding means 40 shown in FIG. 5, which is a pipeline register (pipeline r).
It is a figure which shows the structure at the time of providing egister). In the figure, the adding means 40a includes adder strings 41 and 42, a carry look-ahead adder 43, pipeline registers 51 and 52,
It is composed of 53 and 54 elements. The same elements as those in FIGS. 3 and 5 are designated by the same reference numerals, and the description thereof will be omitted.

Here, the pipeline register 51 is, as shown in the figure, the allocating means 30a and the adder array 41 shown in FIG.
Connect between and. Similarly, the pipeline register 52
Is connected between the adder train 41 and the adder train 42, the pipeline register 53 is connected between the adder train 42 and the look-ahead adder 43, and the pipeline register 54 is connected to the look-ahead adder 43 and the output end. Connect between and.

In this way, the pipeline registers 51,
By providing 52, 53, and 54 between the adder arrays or the like, pipeline processing can be performed, and the arithmetic operation can be further speeded up.

In the above description, regarding the high-speed arithmetic device of the present invention, the number of registers of the register group 201 shown in FIG. 2 is 4, and the numerical data received via the data bus DB has a data bit width of 4 bits. The control signal CS2 received from 100 has a control bit width of 2 bits, but the number of registers in the register group 201, the data bit width of numerical data, and the control bit width of the control signal CS2 may be increased or decreased according to the target of the arithmetic operation. it can. In this case, the relationship between the number of numerical data and the number of addition stages is as shown in FIG.

That is, in the above description, as shown in row 701 of the relationship table 700 of FIG. 10, when the number of numerical data in the right column of the drawing is “4”, the number of addition stages in the left column of the drawing is “2”. That is, the adder arrays 41 and 42 shown in FIG.
become. For example, if the number of numerical data is "8", 7
As shown in line 02, the number of addition stages is required to be four.

Next, another embodiment of the present invention will be described. FIG. 11 is a diagram showing a second embodiment of the present invention.
The difference from FIG. 1 is that the storage means 10 and the registers 21, 2 are
2, ..., 2n between the memory management means 60
That is the point. The same elements as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, the memory management means 60 outputs numerical data D1, D2, ..., Dm according to the number of registers 21, 22 ,. It manages the input / output of data required for arithmetic operations such as storing the arithmetic result AD in the storage means 10.

For example, the registers 21a, 22a,
The arithmetic operation "D1 + D2 + D3 + D4" which has four registers like 23a and 24a and includes six addition operators.
+ D5 + D6 + D7 ”, the memory management means 60
Performs the above arithmetic operation according to the following processing procedure.

First, of the numerical data D1, D2, D3, D4, D5, D6, D7 stored in the storage means 10, the numerical data D1 is stored in the register 21a and the register 22 is stored.
The numerical data D2 is stored in a and the numerical data D is stored in the register 23a.
3 is output to the register 24a, and the numerical data D4 is output to the arithmetic operation "D1 + D2 + D3 + D4". Then, the obtained arithmetic result AD1 is stored in the storage means 10.

Next, the arithmetic result A stored in the storage means 10
Upon receiving D, the numerical data AD1 is newly added to the register 21a.
To output the numerical data D5 to the register 22a, the numerical data D6 to the register 23a, and the numerical data D7 to the register 24a.
5 + D6 + D7 ”. Arithmetic result A thus obtained
D is the desired arithmetic operation "D1 + D2 + D3 + D4 + D5
+ D6 + D7 ”.

Therefore, by repeating the above processing procedure, the numerical data D1, D2, ..., Dm are not limited to the numbers of the registers 21, 22 ,.
Arithmetic operations can be performed according to the number of.

FIG. 12 is a diagram showing a third embodiment of the present invention. The difference from FIG. 1 is that the registers 21, 22, ...
.., 2n and the allocating means 30 between the register 2
Complement circuits 71 and 7 corresponding to 1, 2 ...
2, ..., 7n are provided. The same elements as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The complement circuits 71, 72, ..., 7n obtain the two's complement corresponding to each of the registers 21, 22, .., 2n, so that the numerical data D1, D2 ,. The desired arithmetic operation can be performed even with the number of.

FIG. 13 is a diagram showing a fourth embodiment of the present invention. The difference from FIG. 1 is that the registers 21, 22, ...
.., 2n and the allocating means 30 are further provided with a partial product calculating means 80. The same elements as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

For example, for the numerical data D1, D2, D3, D4, D5, D6 having a bit data width of 4 bits, an arithmetic operation "D1.times.D2 + D3.times.D4" including a product sum operation is performed.
+ D5 × D6 ”, the partial product calculating means 80 uses“ D
The partial product ZD of 1 × D2 ”,“ D3 × D4 ”, and“ D5 × D6 ”is obtained and output.

The allocating means 30 receiving the partial product ZD allocates the bit data BD for each bit data of the partial product ZD, and the adding means 40 performs addition for each bit data BD, thereby performing an arithmetic operation including a product-sum operation. "D1 x D2 + D
The arithmetic result AD of “3 × D4 + D5 × D6” is output.

FIG. 14 is a diagram showing a configuration of the partial product calculating means 80, which is an arithmetic operation "D1 × D2 +" including a product sum operation.
D3 × D4 + D5 × D6 ”, the arithmetic operation“ D1 × D
2 ”is shown. The numerical data D1 is the multiplicand and the numerical data D2 is the multiplier.

In the figure, the booth circuits 81 and 82 include
Numerical data D1 having a 4-bit bit data width is input in parallel. The upper 3 bits of the numerical data D2 having a 4-bit bit data width are input to the booth circuit 81, and the lower 2 of the numerical data D2 are input to the booth circuit 81.
Bit is input. The booth circuit 81 outputs the partial product z1 and the carry data c1, and the booth circuit 82 outputs the partial product z2 and the carry data c2. In addition, other arithmetic operations “D3 × D4”, “D5 × D”
6 "also has the same configuration, whereby the arithmetic operation" D1 × D2 + D3 × D4 + D5 × D "including the product-sum operation is performed.
6 ”can be performed simultaneously.

Therefore, since the partial product calculating means 80 obtains the partial product ZD, the arithmetic operation including the product-sum operation can be performed at high speed. As the method of obtaining this partial product ZD, the above-mentioned Booth method is known, and FIG. 15 shows a block diagram of the Booth circuit and a truth table.

FIG. 15 is a diagram showing the configuration of the booth circuit. FIG. 15A shows a block diagram and FIG. 15B shows a truth table. In FIG. 15A, the Booth circuit 80a has a multiplicand x forming a predetermined data bit width data of, for example, 4 bits, and a multiplier of 3 bits (y _2k-1 ,
y _2k , y _{2k + 1} ) and outputs a partial product z and a 2-bit carry c (0,0), c (1,1).

In FIG. 15B, the input / output table 8
00 is a truth table of the booth circuit 80a. For example, the multiplier is 801 rows _{(y 2k-1, y 2k} , y 2k + 1) when the (0,1,1) booth circuit 80a receives, -1 times the -x partial product z, multiplicand x , Carry c (0,0) outputs "0", and carry c (1,1) outputs "1".

In the above description, the main storage device connected via the address bus AB or the like is applied to the storage means 10, but a cache memory configured in the processor may be applied. Since the bus access is eliminated by using the cache memory, the arithmetic operation can be performed at a higher speed.

Further, although the allocating means 30 is composed of one or more multiplexers, it may be composed so as to allocate bit data by direct connection. in this case,
Since a clock for driving the multiplexer is unnecessary, it is possible to perform arithmetic operation at higher speed.

[0084]

As described above, according to the present invention, the register temporarily holds the numerical data received from the storage means,
Since the allocating means allocates bit data for each bit of the numerical data and the adding means performs addition for each allocated bit data, arithmetic operations including two or more arithmetic operators can be simultaneously performed. Therefore, the arithmetic operation can be speeded up.

By using a processor equipped with a high-speed arithmetic unit having such a configuration in a computer system, it is possible to simultaneously perform arithmetic operations including two or more four arithmetic operators at a low cost.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a processor in a computer system.

FIG. 3 is a diagram showing a first embodiment.

FIG. 4 is a diagram showing a configuration of an allocation unit.

FIG. 5 is a diagram showing a configuration of an addition unit.

FIG. 6 is a diagram showing a relationship between the number of input bits and the number of 1-bit full adders and the like.

7 is a diagram showing a connection relationship of 1-bit full adders corresponding to the number of input bits in FIG. 7, where (A) shows a case of 3-bit input, and (B) shows a case of 4-bit input. , (C) for 6-bit input, (D) for 7-bit input, (E) for 9-bit input, and (F) for 1
The case of 0-bit input is shown.

FIG. 8 is a diagram showing a truth table of a 1-bit full adder.

FIG. 9 is a diagram showing another configuration of the adding means.

FIG. 10 is a diagram showing a relationship between the number of numerical data and the number of addition stages.

FIG. 11 is a diagram showing a second embodiment.

FIG. 12 is a diagram showing a third embodiment.

FIG. 13 is a diagram showing a fourth embodiment.

FIG. 14 is a diagram showing a configuration of a partial product calculating means.

FIG. 15 is a diagram showing a configuration of a Booth circuit, in which (A) is a block diagram and (B) is a truth table.

[Explanation of symbols]

 10 storage means 21, 22, ..., 2n register 30 allocation means 40 addition means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Fumihiro Maruyama 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (8)

[Claims] 1. A high-speed arithmetic device for high-speed arithmetic operation in a computer system, comprising: numerical data (D1, D2, D2) received from a storage means (10)
..., Dm) are temporarily stored in the registers (21, 2).
2, ..., 2n), and for each of the numerical data (D1, D2, ..., Dm) output from the registers (21, 22, ..., 2n),
Allocation means (30) for allocating bit data (BD)
And an addition unit (4) for performing addition for each of the allocated bit data (BD) and outputting an arithmetic result (AD).
0), and a high-speed arithmetic device characterized by the following. 2. The high-speed arithmetic unit according to claim 1, wherein said storage means (10) is composed of a cache memory. 3. The storage means (10) and the registers (21, 22, ..., 2n) are provided between the storage means (10) and the registers (21, 22 ,. For arithmetic operations such as outputting the numerical data (D1, D2, ..., Dm) and storing the arithmetic result (AD) output from the adding means (40) in the storage means (10). The high-speed arithmetic unit according to claim 1, further comprising a memory management unit that manages input / output of necessary data. 4. The registers (21, 22, ..., 2)
n) and the allocating means (30), and 2 corresponding to each of the registers (21, 22, ..., 2n).
2. The high-speed arithmetic device according to claim 1, further comprising a complement circuit for obtaining the complement of the. 5. The registers (21, 22, ..., 2)
n) and the allocating means (30), further comprising a partial product calculating means for calculating a partial product by Booth's method (Booth algorithm).
The described high speed computing device. 6. The allocating means (30) includes numerical data (D1, D2, ..., Dm) output from the registers (21, 22, ..., 2n) and the numerical data (D1). , D2, ..., Dm) having at least one numerical value data shifted by a predetermined bit width, and selecting and outputting any one of the numerical value data according to the selection signal. The high-speed arithmetic device according to claim 1. 7. The high-speed arithmetic unit according to claim 1, wherein said adding means (40) has a pipeline register. 8. The high-speed arithmetic unit according to claim 1, wherein the adding means (40) has a carry look ahead adder.