JPH06268610A - Digital signal processor - Google Patents

Abstract

PURPOSE:To reduce power consumption by stopping one part of the entire part of a processing circuit corresponding to an input signal or decelerating the operating speed at the signal processor for recording/reproducing or transmitting/receiving a compressed digital audio signal. CONSTITUTION:An analog audio signal AIN from an input terminal 60 is supplied through a low-pass filter 61 to an A/D converter 62, the signal AIN is quantized here, and this is supplied to an ATCPCM encoder 63. On the other hand, a digital audio signal DIN from an input terminal 67 is also supplied through a digital input interface circuit 68 to the encoder 63, and the signal DIN is quantized here as well. ATC data supplied from the encoder 63 are temporarily stored in a memory 64, and the transfer speed of compressed data extracted as needed is set to 1/4 speed as high as the transfer speed of a standard CD-DA format. Thus, the entire data transfer speed is decelerated while including a recording standstill term.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus for recording and / or reproducing or transmitting and / or receiving compressed data obtained by bit-compressing a digital audio signal or the like, and more particularly to a digital signal processing apparatus adapted to an input signal for processing. The present invention relates to a digital signal processing device that suspends a part and / or the entire circuit.

[0002]

2. Description of the Related Art The applicant of the present invention has previously disclosed a technique for bit-compressing an input digital audio signal and burst-recording a predetermined data amount as a recording unit, for example, Japanese Patent Application No. 2-221364. , Japanese Patent Application No. 2-22136
No. 5, Japanese Patent Application No. 2-222821, Japanese Patent Application No. 2-2228
No. 23 specification, drawings, etc.

This technique uses a magneto-optical disk as a recording medium, and records and reproduces AD (adaptive difference) PCM audio data defined in audio data formats of so-called CD-I (CD-interactive) and CD-ROM XA. For example, 32 sectors of this ADPCM data and several sectors for linking for interleaving processing are recorded as a recording unit on the magneto-optical disk in a burst manner.

Several modes can be selected for the ADPCM audio in the recording / reproducing apparatus using this magneto-optical disk, and for example, the compression is twice as long as the reproducing time of an ordinary CD (compact disk). Rate, sampling frequency is 37.8 kHz level A, 4 times compression rate and sampling frequency is 37.8 kHz level B,
A level C of 8 times compression rate and a sampling frequency of 18.9 kHz is defined. That is, for example, in the case of the above level B, the digital audio data is approximately 1
The reproduction time (play time) of the disc compressed in / 4 and recorded in this level B mode is four times as long as that in the standard CD format (CD-DA format). This means that the recording / reproducing time of the standard 12 cm can be obtained with a smaller disc, and the device can be miniaturized.

However, the rotation speed of the disk is standard C
Since it is the same as D, for example, in the case of the above level B, compressed data for a reproduction time that is four times that of the predetermined time is obtained. Therefore, for example, the same compressed data is read four times in a time unit such as a sector or a cluster, and only the compressed data for one time is sent to the audio reproduction. Specifically, when scanning (tracking) a spiral recording track,
A reproduction operation is performed in such a form that a track jump is performed to return to the original track position for each rotation, and the same track is repeatedly tracked four times. This means that normal compressed data only needs to be obtained at least once out of, for example, four times of redundant reading, is resistant to errors due to disturbances, etc., and is particularly preferable when applied to a portable small device.

[0006] Further, the applicant of the present invention has filed Japanese Patent Laid-Open No. 53232/1983.
In Japanese Patent Laid-Open No. Hei 3 (1999) -263926, etc.,
It discloses a technique for improving the temporal resolution and responsiveness of a processing system by making a processing block of a compression process variable in response to a large amplitude change of an input signal.

This technique improves the adaptability to the input signal by changing the mutually contradictory characteristics of the processing system, that is, the time resolution and the frequency resolution, according to the property of the input signal, and obtains a good sound quality for the sense of hearing. It is a thing. Among many known high-efficiency compression methods, the so-called transform coding, which uses orthogonal transform, is a particularly effective method for pre-echo generated when a signal with a large amplitude change is input.

Here, the term "pre-echo" means that when compression and expansion are performed in a state where a large amplitude change occurs in an orthogonal transform block, temporally uniform quantization noise occurs in the orthogonal transform block, and In the part where the amplitude of the signal is small, the above-mentioned quantization noise is a phenomenon which causes a problem in hearing.

[0009]

By the way, when the digital signal processing apparatus is constructed by using the above-mentioned technique, as described above, the recording / reproducing equivalent to the conventional one is performed by using the smaller recording medium. Since the time can be secured, it is preferable to be applied to a small portable device. However, when data compression is performed by applying various techniques in order to further improve the quality of recorded signals, the circuit scale of the digital signal processing device tends to increase. In particular, in a portable device, power consumption increases due to an increase in circuit scale, so that a battery as a main power source becomes large in size, and the size and weight of the entire device further increase.

The present invention has been made in view of the above situation, and adapts to an input signal to suspend a part and / or the whole of the processing circuit or reduce the operating speed, thereby making the apparatus. The present invention provides a digital signal processing device that reduces the power consumption of the device.

[0011]

DISCLOSURE OF THE INVENTION In a digital signal processing apparatus of the present invention for information compression and / or expansion of a digital signal for recording and / or reproduction or transmission and / or reception, compression and / or expansion of the digital signal. The power consumption of the device is reduced by suspending a part and / or the whole of the processing circuit in the processing time in the processing circuit which performs the processing. This margin time is generated after the actual compression processing is performed, or is calculated in advance before the actual compression processing is performed.

Further, in the digital signal processing apparatus of the present invention, when the compression processing is performed by adapting to the input signal, the time required for this compression processing is calculated, and a part of the processing circuit and / Or reduce the overall operation speed or adapt to the input signal
Alternatively, the power consumption of the device is reduced by omitting and / or simplifying the whole. When this input signal is zero or below a certain amplitude, a part and / or the whole compression process is stopped and a zero code and / or a specific pattern is output.

Further, the digital signal processing apparatus of the present invention suspends a part and / or the whole of the processing circuit in the processing margin in the processing circuit for compressing and / or expanding the digital signal. , When performing the compression process by adapting to the input signal, calculate the time required for this compression process, reduce the operation speed of a part and / or the whole of the processing circuit so as to eliminate the margin time, and The power consumption of the device may be reduced by additionally omitting and / or simplifying a part and / or the whole of the compression process depending on the signal.

Here, the ratio of combining the respective functions for reducing the power consumption of the digital signal processing device of the present invention as described above is fixed or used in combination with the ratio adapted to the input signal, or used alone. Further, the main power source of the digital signal processing device is composed of a battery, and the respective functions for reducing the power consumption are selected and / or used in combination according to the type of the battery, the load characteristics, and the remaining capacity.

The digital signal processing apparatus of the present invention makes the length of the compression / expansion processing block variable in accordance with the input signal, changes the input signal of the processing block, and inputs the other processing blocks. Based on signal changes and / or power, or energy or peak information,
Based on the function of determining the length of the processing block and the change information of the input signal of the processing block and the change information of the input signal obtained by the input signal having a time width longer than the maximum of the processing block in terms of time, Has the function of determining the length. In addition, the above two functions are combined, and the ratios involved in the determination of the elements that determine the length of the processing block are fixed or used in combination at a ratio adapted to the input signal, or used alone.

Further, the input signal is an audio signal, and the frequency width of the quantization noise generation control block for controlling the generation of at least most of the quantization noise is widened in the higher frequency range, and the frequency is changed from the time axis signal to the frequency. Performing division into a plurality of bands on the axis and using orthogonal transformation for the division, and / or performing conversion from a plurality of bands on the frequency axis to a time axis signal, and using inverse orthogonal transformation for the transformation, And, the shape of the window function used at the time of orthogonal transformation is also changed together with the variable size of the orthogonal transformation, and when dividing from the time axis signal into a plurality of bands on the frequency axis, first divide into a plurality of bands, A block composed of a plurality of samples is formed for each of the divided bands, coefficient data is obtained by performing orthogonal transform for each block of each band, and / or time is obtained from the plurality of bands on the frequency axis. When performing the conversion into signals, performs inverse orthogonal transformation to each block of each band to obtain a time axis on the composite signal by combining the inverse orthogonal transform output.

In addition, in the division from the time axis signal before the orthogonal transformation into a plurality of bands on the frequency axis and / or in the synthesis from the plurality of bands on the frequency axis after the inverse orthogonal transformation to the time axis signal. A composite frequency width from a plurality of bands is widened in a substantially higher range, and the divided frequency width and / or the composite frequency width are the same in two continuous bands of the lowest range,
The main information and / or the sub information of the compression code is not assigned to the signal component in the band substantially above the signal pass band.

Here, Q is used for division into the plurality of bands and / or conversion into a signal on the time axis composed of the plurality of bands.
An MF filter is used and a modified discrete cosine transform is used as the orthogonal transform.

It is more effective to use the methods as described above in combination and select them according to the characteristics of the input signal and / or the application. At this time, even better results can be obtained by selecting and / or using a power consumption reduction method in consideration of the type of battery of the main power source of the digital signal processing device, load characteristics, remaining capacity, and the like.

[0020]

In the digital signal processing apparatus according to the present invention, when the compression adapted to the input signal is performed, the operation can be performed with the minimum circuit operation, and the power consumption of the apparatus can be reduced. Further, when a battery is used as the main power source of the device, the device can be operated for a longer time.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a schematic configuration of an embodiment of a digital signal processing apparatus of the present invention.

The magneto-optical disk recording / reproducing apparatus of the digital signal processing apparatus of FIG. 1 uses a magneto-optical disk 1 which is rotationally driven by a spindle motor 51. At the time of recording data on the magneto-optical disk 1, for example, so-called magnetic field modulation recording is performed by applying a modulation magnetic field according to the recording data with the magnetic head 54 while irradiating the optical head 53 with laser light, thereby performing so-called magnetic field modulation recording. Data is recorded along the recording track of. During reproduction, the recording track of the magneto-optical disc 1 is traced with laser light by the optical head 53 to perform magneto-optical reproduction.

The optical head 53 includes, for example, a laser light source such as a laser diode, a collimator lens, an objective lens,
It is composed of a polarization beam splitter, an optical component such as a cylindrical lens, and a photodetector having a light receiving portion of a predetermined pattern. The optical head 53 is provided at a position facing the magnetic head 54 through the magneto-optical disk 1. When recording data on the magneto-optical disk 1, a magnetic head 54 is driven by a head driving circuit 66 of a recording system to be described later to apply a modulation magnetic field according to the recording data, and the optical head 53 is used for the purpose of the magneto-optical disk 1. By irradiating the track with laser light, thermomagnetic recording is performed by the magnetic field modulation method. The optical head 53 also detects the reflected light of the laser light applied to the target track, detects a focus error by, for example, a so-called astigmatism method, and detects a tracking error by, for example, a so-called push-pull method. When reproducing data from the magneto-optical disk 1, the optical head 53 detects the focus error and the tracking error, and at the same time, detects the difference in the polarization angle (Kerr rotation angle) of the reflected light of the laser light from the target track and reproduces it. Generate a signal.

The output of the optical head 53 is supplied to the RF circuit 55. The RF circuit 55 extracts the focus error signal and the tracking error signal from the output of the optical head 53 and supplies them to the servo control circuit 56.
The reproduction signal is binarized and supplied to a reproduction system decoder 71 described later.

The servo control circuit 56 is composed of, for example, a focus servo control circuit, a tracking servo control circuit, a spindle motor servo control circuit, a sled servo control circuit, and the like. The focus servo control circuit controls the focus of the optical system of the optical head 53 so that the focus error signal becomes zero. Further, the tracking servo control circuit controls the tracking of the optical system of the optical head 53 so that the tracking error signal becomes zero. Further, the spindle motor servo control circuit controls the spindle motor 51 so as to rotate the magneto-optical disk 1 at a predetermined rotation speed (for example, a constant linear speed). Further, the sled servo control circuit moves the optical head 53 and the magnetic head 54 to the target track position of the magneto-optical disk 1 designated by the system controller 57. The servo control circuit 56 that performs such various control operations sends information indicating the operating state of each unit controlled by the servo control circuit 56 to the system controller 57.

A key input operation section 58 and a display section 59 are connected to the system controller 57. The system controller 57 controls the recording system and the reproducing system in the operation mode designated by the operation input information from the key input operation unit 58. The system controller 7 also uses the optical head 53 and the magnetic head 54 based on the address information in sector units reproduced from the recording track of the magneto-optical disk 1 by the header time, the Q data of the subcode, or the like.
Manages the recording position and the reproducing position on the recording track traced by the. Further system controller 57
Controls the display unit 59 to display the reproduction time based on the data compression rate and the reproduction position information on the recording track.

This reproduction time display is the reciprocal of the data compression rate (absolute time information) with respect to the sector unit address information (absolute time information) reproduced from the recording track of the magneto-optical disk 1 by so-called header time or so-called sub-code Q data. For example, in the case of 1/4 compression, the actual time information is obtained by multiplying by 4), and this is displayed on the display unit 59. Even at the time of recording, when absolute time information is recorded (pre-formatted) in advance on a recording track of a magneto-optical disk or the like, the pre-formatted absolute time information is read to determine the data compression rate. It is also possible to display the current position at the actual recording time by multiplying by the reciprocal.

Next, in the recording system of this magneto-optical disk recording / reproducing apparatus, the analog audio input signal AIN from the input terminal 60 is A / D via the low pass filter 61.
The A / D converter 62 is supplied to the converter 62, which quantizes the analog audio input signal AIN. The digital audio signal obtained from the A / D converter 62 is A
TC (Adaptive Transform Coding) PCM encoder 6
3 is supplied. Further, the digital audio input signal DIN from the input terminal 67 is supplied to the ATC encoder 63 via the digital input interface circuit 68. The ATC encoder 63 performs a bit compression (data compression) process on the digital audio PCM data of a predetermined transfer rate obtained by quantizing the input signal AIN by the A / D converter 62. Although the compression rate will be described as 4 times here, this embodiment does not depend on this magnification and can be arbitrarily selected.

Next, in the memory 64, the writing and reading of data are controlled by the system controller 57, the ATC data supplied from the ATC encoder 63 is temporarily stored, and recorded on the disk as needed. It is used as a buffer memory for That is, for example, the compressed audio data supplied from the ATC encoder 63 has a data transfer rate ¼ of the standard CD-DA format data transfer rate (75 sectors / second), that is, 18.75 sectors / second. The compressed data is continuously written to the memory 64. As for this compressed data (ATC data), it is sufficient to record one sector for every four sectors as described above. However, since recording every four sectors is practically impossible, the continuous sectors described below will be used. I try to keep a record. This recording bursts at a data transfer rate (75 sectors / second) same as that of the standard CD-DA format by using a cluster composed of a plurality of predetermined sectors (for example, 32 sectors + several sectors) as a recording unit through a pause period. Is done in a regular manner.

That is, in the memory 64, ATC audio data continuously written at a low transfer rate of 18.75 (= 75/4) sectors / second corresponding to the bit compression rate is recorded as the recording data of the 75 sectors. It is read in bursts at a transfer rate of / sec. The overall data transfer rate of the read and recorded data, including the recording pause period, is as low as 18.75 sectors / sec, but within the time of the recording operation performed in bursts. The instantaneous data transfer rate in the above is the standard 75 sectors / sec. Therefore, when the disk rotation speed is the same as the standard CD-DA format (constant linear speed), the same recording density and storage pattern as the CD-DA format are recorded.

The ATC audio data, that is, the recording data, which is burst-read from the memory 64 at the (instantaneous) transfer rate of 75 sectors / second, is recorded by the encoder 65.
Is supplied to. Here, from the memory 64 to the encoder 65
In the data string supplied to the above, the unit to be continuously recorded in one recording is a cluster composed of a plurality of sectors (for example, 32 sectors) and several sectors for cluster connection arranged at the front and rear positions of the cluster. This cluster connection sector is set to be longer than the interleave length in the encoder 65 so that interleaved data will not affect the data of other clusters.

The encoder 65 uses the recording data supplied from the memory 64 in bursts as described above.
Encoding processing for error correction (parity addition and interleave processing), EFM encoding processing, and the like are performed. The recording data encoded by the encoder 65 is supplied to the magnetic head drive circuit 66. The magnetic head drive circuit 66 is connected to the magnetic head 54,
The magnetic head 54 is driven so as to apply the modulation magnetic field according to the recording data to the magneto-optical disk 1.

The system controller 57 controls the memory 64 as described above, and at the same time,
By this memory control, the recording position is controlled so that the recording data read out in burst from the memory 64 is continuously recorded on the recording track of the magneto-optical disk 1.
The recording position is controlled by controlling the recording position of the recording data which is burst-read from the memory 64 by the system controller 57 and outputting a control signal for designating the recording position on the recording track of the magneto-optical disk 1 to the servo control circuit. By feeding 56.

Next, the reproducing system of this magneto-optical disk recording / reproducing apparatus will be described. This reproducing system is for reproducing the record data continuously recorded on the recording track of the magneto-optical disk 1 by the above-mentioned recording system, and the recording track of the magneto-optical disk 1 is laser-driven by the optical head 53. The decoder 71 is provided with a reproduction output obtained by tracing with light, which is binarized and supplied by the RF circuit 55. At this time, not only the magneto-optical disc 1 but also a so-called compact disc (CD: Compact D
The same read-only optical disc as isc) can be read.

The decoder 71 corresponds to the encoder 65 in the above-mentioned recording system, and performs the above-mentioned decoding processing for error correction and EFM decoding on the reproduction output binarized by the RF circuit 55. Processing such as processing is performed to reproduce the ATC audio data at a transfer rate of 75 sectors / second, which is faster than the normal transfer rate. The reproduced data obtained by the decoder 71 is supplied to the memory 72.

In the memory 72, writing and reading of data are controlled by the system controller 57, and reproduction data supplied from the decoder 71 at a transfer rate of 75 sectors / second is written in bursts at the transfer rate of 75 sectors / second. Be done. The reproduction data written in bursts at the transfer rate of 75 sectors / second is continuously read out from the memory 72 at the regular transfer rate of 18.75 sectors / second.

The system controller 57 writes the reproduction data in the memory 72 at a transfer rate of 75 sectors / second, and also reproduces the reproduction data from the memory 72 in the above 18.7.
Memory control is performed so that data is continuously read at a transfer rate of 5 sectors / second. Further, the system controller 57 performs the above-mentioned memory control on the memory 72, and continuously reproduces the above-mentioned reproduction data written in burst from the memory 72 from the recording track of the magneto-optical disk 1 by the memory control. Controls the playback position. This playback position is controlled by the system controller 5
By controlling the reproduction position of the reproduction data which is read out from the memory 72 in burst by 7 and supplying a control signal for designating the reproduction position on the recording track of the magneto-optical disk 1 or the optical disk 1 to the servo control circuit 56. Done.

ATC audio data obtained as reproduction data continuously read from the memory 72 at a transfer rate of 18.75 sectors / second is supplied to the ATC decoder 73. The ATC decoder 73 reproduces 16-bit digital audio data by expanding the ATC audio data four times (bit expanding).
The digital audio data from the ATC decoder 73 is supplied to the D / A converter 74.

The D / A converter 74 is the ATC decoder 73.
The digital audio data supplied from the converter is converted into an analog signal to form an analog audio output signal AOUT. The analog audio signal AOUT obtained by the D / A converter 74 is output from the output terminal 76 via the low pass filter 75.

Next, the power supply system of this digital signal processing device will be described. The power supply control circuit 3 generates and stabilizes a necessary voltage in each of the circuits described above, and monitors the voltage of the battery 2. Also, this battery 2
However, in the case of a rechargeable secondary battery such as a nickel-cadmium battery, the current input from the external power supply terminal 4 when the battery 2 is charged is also managed. The system controller 57, based on the information from the power supply control circuit 3,
The display unit 59 displays a display of the remaining battery level, a warning of insufficient capacity, a display of battery replacement time, and the like. Further, a low power consumption mode in a power down detection circuit, which will be described later, is selected according to the remaining battery level or the type of the battery 2.

Next, the high-efficiency compression coding used in the digital signal processing apparatus of this embodiment will be described in detail. That is, an input digital signal such as an audio PCM signal is
Band division coding (SBC), adaptive transform coding (ATC)
A technique for high-efficiency coding using each technique of adaptive bit allocation and adaptive bit allocation will be described with reference to FIG.

In the concrete high-efficiency coding apparatus shown in FIG. 2, the input digital signal is divided into a plurality of frequency bands, and the bandwidths of the two adjacent lowest bands are the same, and are higher in the higher frequency bands. The wider the frequency band, the wider the bandwidth is selected, and the spectrum data on the frequency axis that is obtained by performing orthogonal transformation for each frequency band is used in the low frequency range. ), In the high and middle frequency band, the critical bandwidth is subdivided in consideration of the block floating efficiency, and each bit is adaptively bit-assigned and coded. Usually, this block is the quantization noise generation block. Furthermore, in the embodiment of the present invention, the block size (block length) is adaptively changed according to the input signal before the orthogonal transformation, and the floating process is performed for each block.

That is, in FIG. 2, for example, when the sampling frequency is 44.1 kHz, 0 to 2 are applied to the input terminal 10.
A 2 kHz audio PCM signal is supplied. This input signal is supplied to a band dividing filter 11 such as a so-called QMF filter for 0 to 11 kHz band and 11 kHz.
The signal in the 0 to 11 kHz band is divided into the z to 22 kHz band and the 0 to 5.5 kHz band and the 5.5 kHz band by the band dividing filter 12 such as a so-called QMF filter.
.About.11 kHz band. Band division filter 1
The signal in the 11 kHz to 22 kHz band from 1 is sent to the MDCT circuit 13 which is an example of an orthogonal transformation circuit, and the signal in the 5.5 kHz to 11 kHz band from the band division filter 12 is sent to the MDCT circuit 14 and the band division filter 12
The signal in the 0 to 5.5 kHz band from the MDCT circuit 15
And the MDCT processing is performed on each of them.
Further, the respective outputs from the respective band division filters 11 and 12 are the power down detection circuits 31 and 32 for the respective bands.
Connected to 33.

As a method of dividing the above-mentioned input digital signal into a plurality of frequency bands, there is, for example, a QMF filter, and 1976 RECrochiere Digital Coding o
fSpeech in Subbands Bell Syst.Tech. J. Vol.55, No.8
1976. Also, ICASSP 83, Boston Poly
phase Quadrature Filters-A New Subband CodingTechn
ique Joseph H. Rothweiler describes a technique for partitioning filters with equal bandwidth. Here, as the above-mentioned orthogonal transform, for example, an input audio signal is divided into blocks in a predetermined unit time (frame), and fast Fourier transform (FFT), cosine transform (DCT), modified DCT transform (MDCT), etc. are performed for each block. There is an orthogonal transformation in which the time axis is transformed into the frequency axis by performing it. MDC
For T, ICASSP 1987 Subband / Transform Coding U
sing Filter Bank DesignsBased on Time Domain Alias
ing Cancellation JPPrincen ABBradley Univ.of S
urrey Royal Melbourne Inst. of Tech.

Next, each MDC for the standard input signal
FIG. 3 shows a specific example of blocks for each band supplied to the T circuits 13, 14, and 15. In the specific example of FIG. 3, 3 from each of the band division filters 11 and 12 in FIG.
Each filter output signal has a plurality of orthogonal transform block sizes independently for each band, and the time resolution can be switched according to the time characteristics and frequency distribution of the signal. If this signal is quasi-stationary in time, then
The orthogonal transform block size is increased to 11.6 mS as shown in the long mode of FIG. 3A, and when the signal is non-stationary, the orthogonal transform block size is further divided into two, four, ...・ And For example, the orthogonal transform block size is equally divided into four as shown in the short mode of FIG. 3B to be 2.9 ms, or (c) of FIG.
As shown in the middle mode A of (1) and the middle mode B of (d), a part is divided into two to make 5.8 ms, and the remaining part is divided into 4 parts.
By dividing into 2.9 ms, it is possible to adapt to a complicated signal. Further, it is possible to perform the orthogonal transform more effectively by performing a more complicated division of the orthogonal transform block size according to the scale of the signal processing device. This orthogonal transform block size is determined by each block size determination circuit 19, 20, 21 in FIG.
The data is sent to the CT circuits 13, 14, 15 and output from the output terminals 28, 29, 30 as block size information.

Next, a concrete block size determining circuit is shown in FIG. For example, the block size determination circuit 1 in FIG.
9 is specifically shown in FIG. 4, 11 kHz to 2 of the output signals from the band division filter 11 in FIG.
The output signal in the 2 kHz band is sent to the power calculation circuit 304 via the input terminal 301 in FIG. 4, and 5.5 kHz to 1 out of the output signals from the band division filter 12 in FIG.
The output signal in the 1 kHz band is sent to the power calculation circuit 305 via the input terminal 302 in FIG. 4, and the output signal in the 0 to 5.5 kHz band is sent to the power calculation circuit 306 in the input terminal 303 in FIG. Here, when the block size determining circuits 19, 20, and 21 in FIG. 2 are specifically shown in FIG. 4, the frequency bands of the input signals to the input terminals 301, 302, and 303 are the block size determining circuits 1 respectively.
The operations of the block size determination circuits are the same, except that 9, 20, and 21 are different. Further, the respective input terminals 301, 302, 303 in each block size determination circuit 19, 20, 21 have a matrix configuration. Specifically, the input terminal 301 of the block size determination circuit 20 has the band division of FIG. 5.5 kHz of filter 12
Output signal from ~ 11kHz band is sent, input terminal 3
0 to 5.5 kHz of the band division filter 12 of FIG.
The output signal from the z band is sent. The same applies to the block size determination circuit 21.

Each power calculation circuit 304, 305, 306
Then, the power of each frequency band is obtained by integrating the input time waveform for a certain period of time. At this time, the integration time width needs to be equal to or smaller than the minimum time block of the above orthogonal transform block sizes. In addition, an absolute value of the maximum amplitude or an average value of the amplitudes within the minimum time width of the orthogonal transform block size may be used as the representative power by a calculation method other than the above calculation method. The output signal from the power calculation circuit 304 is sent to the change amount extraction circuit 308 and the power comparison circuit 309, and the power calculation circuits 305 and 30.
The output signals from 6 are sent to the power comparison circuit 309, respectively. In the change amount extraction circuit 308, the power calculation circuit 30
4. The differential coefficient of the power sent from No. 4 is obtained, and this differential coefficient of the power is sent to the memory 307 and the block size primary determination circuit 310 as the power change information. In the memory 307, the power change information sent from the change amount extraction circuit 308 is stored for the maximum time of the above orthogonal transform block size or more. This is because the temporally adjacent orthogonal transform blocks influence each other by the window processing at the time of orthogonal transform, and therefore, the power change information of the immediately preceding temporally adjacent block is calculated in the block size primary determination circuit 310. This is because it is necessary.

In the block size primary determination circuit 310, the power change information of the block sent from the change extraction circuit 308 and the power change information of the block immediately preceding the temporally adjacent block sent from the memory 307. Based on, the orthogonal transform block size of the frequency band is determined from the temporal displacement of the power within the frequency band. At this time, when a displacement equal to or larger than a certain amount is recognized, an orthogonal transform block size shorter in time is selected, but the effect can be obtained even if the displacement point is fixed. Furthermore, a block size that is proportional to the frequency, that is, a block that is short in time when the frequency is high is determined by a large displacement, and a block that is short in time with a small displacement compared to the case where the frequency is high when the frequency is low. The one decided by the size is
More effective. It is desirable that the value of the orthogonal transform block size changes smoothly, but it may be a stepwise change in a plurality of steps. The orthogonal transform block size determined as described above is the block size correction circuit 31.
1 is transmitted.

On the other hand, in the power comparison circuit 309, the power information of each frequency band sent from each power calculation circuit 304, 305, 306 is compared at the same time and on the time width in which the masking effect occurs on the time axis, The effect of another frequency band on the output frequency band of the power calculation circuit 304 is obtained and sent to the block size correction circuit 311. In the block size correction circuit 311, the power comparison circuit 309
Masking information sent from each delay 312, 3
13 and 314, the block size sent from the block size primary determination circuit 310 is modified based on the past block size information sent so as to select a longer block size, and the delay 312 and the window It is output to the shape determination circuit 317. The operation of the block size correction circuit 311 is such that even if the pre-echo becomes a problem in a frequency band, another frequency band,
In particular, when there is a signal having a large amplitude in a band lower than the frequency band, the pre-echo does not pose a hearing problem or the problem may be mitigated due to the masking effect.

The masking refers to a phenomenon in which one signal is shielded by another signal and becomes inaudible due to human auditory characteristics. The masking effect depends on the audio signal on the time axis. There are a time axis masking effect and a simultaneous time masking effect by a signal on the frequency axis. Due to these masking effects, even if there is noise in the masked portion, this noise cannot be heard. For this reason, in the actual audio signal, the noise within the masked range is regarded as acceptable noise.

Next, delay groups 312, 313, 314
Then, the past orthogonal transform block size is recorded in order, and each tap, that is, each delay 312, 313, 3 is recorded.
A block size correction circuit 31 according to the output signal from 14
Output to 1. At the same time, the output signal from the delay 312 is sent to the output terminal 315, and the output signals from the delays 312 and 313 are sent to the window shape determining circuit 317. The output signals from the delay groups 312, 313, and 314 are useful in the block size correction circuit 311 when determining a change in the block size in a longer time width as the block size of the block, for example, in the past. , Increase the selection of short time block size frequently when the short time block size is frequently selected, and increase the long time block size if the short time block size is not selected It is possible to make decisions such as increasing choices. The number of taps of the delay group except the delays 312 and 313 required for the window determination circuit 317 and the output terminal 315 may be increased or decreased depending on the actual configuration and scale of the device.

In the window shape determination circuit 317, the output from the block size correction circuit 311, that is, the block size immediately after the block that is temporally adjacent to the block,
Based on the output from the delay 312, that is, the block size of the corresponding block, and the output from the delay 313, that is, the size of the immediately preceding block adjacent to the corresponding block, the MDCT circuits 13, 14, 15 in FIG.
Determine the shape of the window used in the output terminal 31
Output to 6. The block size information from the output terminal 315 of FIG. 4 and the window shape information from the output terminal 317 are the block size determination circuits 19, 20, and 21 of FIG.
Is output to each part as output from.

Here, the window shape determined by the window shape determination circuit 317 will be described.
FIG. 5 is a diagram showing the relationship between the temporal length changes of orthogonal transform blocks that are temporally adjacent to each other and the window shape used in orthogonal transform. In FIG. 5A, the size of the orthogonal transform block is the long mode. 5B shows the case where the size of the orthogonal transform block is the long mode and the middle mode A, and FIG. 5C shows the case where the size of the orthogonal transform block is the long mode. And the short mode. 5 (a) to (c)
As shown in the relationship between the adjacent blocks and the window shape shown by the solid line and the broken line in the figure, the window used for the orthogonal transformation has a portion overlapping between the blocks temporally adjacent to each other. In the present embodiment, since the shapes overlapping the centers of the adjacent blocks are used, the shape of the window changes depending on the orthogonal transform size of the adjacent blocks.

FIG. 6 shows the detailed shape of the window. In FIG. 6, window functions f (n) and g (n +
N) is f (n) * f (L-1-n) = g (n) * g (L-1-n) ... (1) f (n) * f (n) + g (n) * g (n) = 1 ... (2) (0 ≦ n ≦ L−1) is given as a function satisfying the expressions (1) and (2).

L in the equation (1) is a conversion block length, which is used as it is when adjacent conversion block lengths are the same, and when adjacent conversion block lengths are different. , The shorter transform block length is used. K for longer conversion block length
Then, in the area where the windows do not overlap, f
When (n) = g (n) = 1, K ≦ n ≦ 3K / 2−L / 2 (3) When f (n) = g (n) = 0, 3K / 2 + L≤n≤2K (4) In this way, by making the overlapping portion of the windows as long as possible, the frequency resolution of the spectrum at the time of orthogonal transformation is made good. As is apparent from the above description, the shape of the window used for orthogonal transform is determined after the orthogonal transform block sizes for three blocks that are temporally consecutive are determined. Therefore, there is a difference of one block between the block of signals input from the input terminals 301, 302 and 303 and the block of signals output from the output terminals 315 and 317 in FIG.

Here, the power calculation circuit 305 in FIG.
Even if the 306 and the power comparison circuit 309 are omitted, the block size determination circuits 19, 20, and 21 in FIG. 2 can be configured. Further, by fixing the window shape to the smallest block size in terms of time with the orthogonal transform block size, the window shape is made one type, and the delay groups 312, 313, 314 in FIG.
The block size correction circuit 311 and the window shape determination circuit 317 can be omitted. The omission as described above results in a configuration with less delay, which is effective particularly in an application example in which delay in processing time is not desired.

In the present embodiment, in order to consider the masking state of the pre-echo, the band division before the orthogonal transformation is used as it is, but it is divided into more bands or independent orthogonal transformation is used. Even better results can be obtained by calculating the masking by using. Moreover,
The periodic time change of the input signal obtained by observing the above-mentioned longer time is shown by the delay group 31 in FIG.
2, 313, 314, that is, it is realized by storing the orthogonal transform block size of the past block. However, in the feature extraction of the input waveform, data obtained by performing an orthogonal transform different from the compression process, or more detailed data is used. Even better results can be obtained by using data or the like divided into frequency bands.

Referring again to FIG. 2, each MDCT circuit 1
The spectral data on the frequency axis obtained by MDCT processing at 3, 14, and 15 or the MDCT coefficient data are summarized in each so-called critical band in the low range, and the effectiveness of block floating in the middle-high range. In consideration of the above, the critical bandwidth is subdivided and sent to the adaptive bit allocation encoding circuits 22, 23, 24 and the bit allocation calculation circuit 18. This critical band is a frequency band divided in consideration of human auditory characteristics,
It is a band of a certain pure tone when the pure tone is masked by a narrow band noise having the same strength near the frequency of the pure tone. The critical band has a wider bandwidth in a higher frequency range, and the entire frequency band of 0 to 22 kHz is divided into, for example, 25 critical bands.

The bit allocation calculating circuit 18 masks each divided band considering the critical band and the block floating in consideration of the so-called masking effect based on the spectrum data divided in consideration of the critical band and the block floating. Then, based on the masking amount and the energy or peak value of each divided band considering the critical band and block floating, the number of allocated bits is obtained for each band, and this information is adaptive bit allocation coded. To circuits 22, 23, 24. Adaptive bit allocation encoding circuit 2
In 2, 23, and 24, each spectrum data (or MDCT coefficient data) is quantized according to the number of bits assigned to each band. The data encoded in this way is taken out via the output terminals 25, 26 and 27.

Next, FIG. 7 shows the bit allocation calculation circuit 18 described above.
It is a block circuit diagram which shows schematic structure of one specific example. In FIG. 7, each of the MDCTs is connected to an input terminal 701.
Spectral data on the frequency axis is supplied from the circuits 13, 14, and 15.

The input data on the frequency axis is sent to the energy calculation circuit 702 for each band, and the energy of each divided band considering the masking amount and the critical band and block floating is, for example, each energy in the band. It can be obtained by calculating the sum of amplitude values.
Instead of the energy for each band, a peak value, an average value, etc. of the amplitude value may be used. As the output from the energy calculating circuit 702, for example, the spectrum of the total sum value of each band is shown as SB in the drawing of FIG. However, in FIG. 8, in order to simplify the illustration, the number of division bands in consideration of the masking amount, the critical band, and the block floating is 12 bands (B1 to B12).
Is expressed in.

Here, in order to consider the influence of the so-called masking of the spectrum SB, a convolution process is performed such that the spectrum SB is multiplied by a predetermined weighting function and added. Therefore, the output of the energy calculation circuit 702 for each band, that is, each value of the spectrum SB is sent to the convolution filter circuit 703. The convolution filter circuit 703 includes, for example, a plurality of delay elements that sequentially delay input data, and a plurality of multipliers that multiply outputs from these delay elements by a filter coefficient (weighting function) (for example, 25 corresponding to each band). Number of multipliers), and a sum adder that sums the outputs of the multipliers. By this convolution processing, the total sum of the portions shown by the dotted lines in FIG. 8 is obtained.

Here, a specific example of the multiplication coefficient (filter coefficient) of each multiplier of the convolution filter circuit 703 will be described. When the coefficient of the multiplier M corresponding to an arbitrary band is 1, the multiplier is M-1 gives a coefficient of 0.15, multiplier M-2 gives a coefficient of 0.0019, and multiplier M-3 gives a coefficient of 0.0000.
086, multiplier M + 1 gives a coefficient of 0.4, multiplier M + 2
By multiplying the output of each delay element by a coefficient of 0.06 with a coefficient of 0.007 with a multiplier M + 3, the convolution processing of the spectrum SB is performed. However, M is an arbitrary integer of 1 to 25.

Next, the output of the convolution filter circuit 703 is sent to the subtractor 704. The subtractor 704 obtains a level α corresponding to an allowable noise level described later in the convoluted area. The level α corresponding to the permissible noise level (permissible noise level) is a level at which the critical noise band becomes the permissible noise level for each band by performing inverse convolution processing, as described later. is there. here,
The subtractor 704 is supplied with an allowance function (function expressing a masking level) for obtaining the level α. The level α is controlled by increasing or decreasing this allowance function. The permissible function is supplied from the (n-ai) function generating circuit 705 described below.

That is, the level α corresponding to the allowable noise level can be obtained by the following equation (5), where i is the number given in order from the low band of the critical band. α = S- (n-ai) (5) In this equation (5), n and a are constants, a> 0, and S is the intensity of the convolved Bark spectrum, and (5)
In the formula, (n-ai) is the allowable function. In this embodiment, n
= 38, a = 1, there is no sound quality deterioration at this time,
Good coding was achieved.

In this way, the level α is obtained, and this data is transmitted to the divider 706. The divider 706 is for inverse convolution of the level α in the convolved area. Therefore, the masking spectrum can be obtained from the level α by performing this inverse convolution processing. That is, this masking spectrum becomes the allowable noise spectrum. Although the above-mentioned inverse convolution processing requires a complicated calculation, in this embodiment, the inverse convolution is performed using the simplified divider 706.

Next, the masking spectrum is transmitted to the subtractor 708 via the synthesis circuit 707. Here, the subtracter 708 outputs the output from the energy detection circuit 702 for each band, that is, the spectrum S described above.
B is supplied via the delay circuit 709. Therefore, the subtractor 708 performs a subtraction operation on the masking spectrum and the spectrum SB, so that the spectrum SB is masked below the level indicated by the level of the masking spectrum MS, as shown in FIG. Become.

The output from the subtractor 708 is taken out through the allowable noise correction circuit 710 and the output terminal 711. For example, RO in which the allocated bit number information is stored in advance.
M, etc. (not shown). This ROM or the like is assigned to each band according to the output (the level of the difference between the energy of each band and the output of the noise level setting means) obtained from the subtraction circuit 708 through the allowable noise correction circuit 710. Outputs bit number information. This allocation bit number information corresponds to each adaptive bit allocation encoding circuit 22, 23, 2 in FIG.
4, the MDCT circuits 13, 1 in FIG.
Each spectrum data on the frequency axis from 4 and 15 is quantized by the number of bits assigned to each band.

In summary, in the adaptive bit allocation coding circuits 22, 23 and 24 in FIG. 2, the energy of each divided band considering the masking amount, the critical band and the block floating, and the output of the noise level setting means. The spectrum data for each band will be quantized by the number of bits assigned according to the level of the difference between and. In addition, the delay circuit 709 is the synthesis circuit 70.
It is provided to delay the spectrum SB from the energy detection circuit 702 in consideration of the delay amount in each circuit before 7.

By the way, at the time of synthesizing by the above-mentioned synthesizing circuit 707, data showing a so-called minimum audible curve RC which is a human auditory characteristic as shown in FIG. The masking spectrum MS can be combined. In this minimum audible curve, if the absolute noise level is below this minimum audible curve, the noise will not be heard. Even if the coding is the same, this minimum audible curve will be different due to the difference in reproduction volume at the time of reproduction, and in a realistic digital system, there is not much difference in how to enter music into a 16-bit dynamic range, for example. Therefore, for example, if the quantization noise in the most audible frequency band around 4 kHz is not heard, it is considered that the quantization noise below the level of the minimum audible curve is not heard in other frequency bands.

Therefore, assuming that the system is used in such a manner that noise near the word length of the system of 4 kHz cannot be heard, the minimum audible curve RC and the masking spectrum MS are combined together to obtain an allowable noise level. In this case, the allowable noise level in this case can be up to the shaded portion in FIG. In this embodiment, the level of 4 kHz of the minimum audible curve is set to the minimum level equivalent to 20 bits, for example. Further, FIG. 10 also shows the signal spectrum SS at the same time.

Further, in the allowable noise correction circuit 710,
The allowable noise level in the output from the subtractor 708 is corrected based on the information on the equal loudness curve sent from the correction information output circuit 713, for example. Here, the equal loudness curve is a characteristic curve relating to human auditory characteristics, and is obtained by, for example, obtaining the sound pressure of sound at each frequency heard at the same loudness as a pure tone of 1 kHz and connecting them with a curve. Also called sensitivity curve. Further, this equal loudness curve is the minimum audible curve R shown in FIG.
It draws a curve substantially the same as C. In this equal loudness curve, for example, in the vicinity of 4 kHz, even if the sound pressure is reduced by 8 to 10 dB from 1 kHz, it sounds as loud as 1 kHz, and conversely, in the vicinity of 50 Hz, it is not higher than the sound pressure at 1 kHz by about 15 dB. It doesn't sound the same. Therefore, it is understood that it is preferable that the noise (allowable noise level) exceeding the level of the minimum audible curve has a frequency characteristic given by a curve corresponding to the equal loudness curve. From this, it can be seen that correcting the permissible noise level in consideration of the equal loudness curve is suitable for human hearing characteristics.

Here, as the correction information output circuit 713,
Based on the information on the error between the detection output of the output information amount (data amount) at the time of quantization in the adaptive bit allocation encoding circuits 22, 23 and 24 and the bit rate target value of the final encoded data. The allowable noise level may be corrected. This is because the total number of bits obtained by performing temporary adaptive bit allocation in advance for all bit allocation unit blocks is a fixed number of bits (target value) determined by the bit rate of the final encoded output data. May have an error with respect to, and bit allocation is performed again so that the error may be zero. That is, when the total allocated bit number is smaller than the target value, the difference bit number is allocated to each unit block and added, and when the total allocated bit number is larger than the target value, the difference bit number is set in each unit. Allocate to blocks and delete.

In order to do this, the correction information output circuit 713 detects an error in the total allocation bit number from the target value and the correction data for correcting each allocation bit number in accordance with the error data. Is output. Here, when the error data indicates a bit number shortage, it can be considered that the data amount is larger than the target value because a large number of bits are used per unit block. Further, when the error data is data indicating a surplus of the number of bits, it can be considered that the number of bits per unit block is small and the amount of data is smaller than the target value. Therefore, the correction information output circuit 713 outputs the correction value for correcting the allowable noise level in the output from the subtractor 708 according to the error data, for example, based on the information data of the equal loudness curve. Data will be output. By transmitting the correction value as described above to the allowable noise correction circuit 710, the subtractor 708
The allowable noise level from is corrected. In the system as described above, the data obtained by processing the orthogonal transform output spectrum by the sub information as the main information,
As the sub information, a scale factor indicating a block floating state and a word length indicating a word length are obtained and sent from the encoder to the decoder.

On the other hand, the band division filters 11 and 1 in FIG.
The signal on the time axis of the 0 to 5.5 kHz band, which is the output from 2, is sent to the power down detection circuit 33 at 5.5 kHz to 1
The signal of 1 kHz band is sent to the power down circuit 32 by 11 kHz.
Signals in the Hz to 22 kHz band are power down detection circuit 3
Input to 1 respectively. Further, a signal synchronized with the orthogonal transform block via the input terminal 34, that is, a pulse signal having a period of 11.6 ms in the embodiment and a power down mode from the system controller 57 in FIG. The control signal is input to each power down detection circuit 31, 32, 33. In the power-down detection circuits 31, 32, 33, the compression processing time required in the compression process is calculated in advance from the input signal in the above band, and the compression processing is completed sufficiently earlier than the maximum time allowed for this compression processing. In each case, each processing circuit,
That is, a power down signal that matches the power down mode is output to the MDCT circuits 13, 14, 15 and the block decision circuits 19, 20, 21 and the adaptive bit allocation coding circuits 22, 23, 24 and the like.

In each of the processing circuits, the power-down signal is input during the compression processing, and the power-down mode mode is entered after the compression processing. For example, when the value of the input signal is 0, the values of all processing results are 0. Therefore, each processing circuit forcibly outputs 0 without performing actual processing, and shifts to the power down mode. . After this, the power down determination circuits 31, 32,
At 33, the next signal processing is detected by the block synchronization signal from the input terminal 34, and the power down mode release signal of each processing circuit is output.

FIG. 11 is a detailed block diagram of the power down detection circuits 31, 32 and 33 in FIG.
FIG. 12 is a diagram showing a timing chart showing the operation of each circuit in FIG. 11 and the timing of input / output waveforms. The processing time calculation circuit 204 calculates the signal processing time using the signal from the input terminal 201. When the calculated signal processing time is sufficiently shorter than the maximum time allowed for signal processing, the power down control signal transmitted to the power down determination circuit 206 via the input terminal 203 is the power down output control circuit. It is sent to 207. The power-down output control circuit 207 generates a power-down signal to be sent to each processing circuit according to the power-down control signal and the power-down cancellation signal from the timer circuit 205, and outputs the power-down signal from the output terminal 208 to each processing circuit.

The output from the band division filters 11 and 12 in FIG. 2, that is, the waveform on the time axis divided into each band is input to the input terminal 201, and the processing time calculation circuit 20 is input.
4 has been transmitted. In addition, the input terminal 202 is shown in FIG.
The block synchronizing signal shown in FIG. 12A is input from the input terminal 34 therein, and is transmitted to the timer circuit 205. The processing time calculation circuit 204 calculates the compression processing time required for compression using the waveform on the time axis from the input terminal 201, and transmits it to the power down determination circuit 206.

Here, the calculation processing time Tb which is the compression processing time calculated from the processing time calculation circuit 204 shown in FIG. 12C and the time length T of the processing block, that is, 11.6 ms in this embodiment. The conditions for reducing the power consumption are calculated by comparing with. When the power down cancellation signal for canceling the power down mode for each processing block based on the block synchronization signal is Ta and the margin time after the compression processing is Tc, the above processing in the case where the power consumption can be reduced The time relationship is as follows.

Ta-Tb = Tc> 0 (6)

A power-down control signal matching the power-down mode determined by the system controller 57 shown in FIG. 1 is transmitted to the power-down determination circuit 206 via the input terminal 203, and is expressed by the equation (6). When the condition shown is satisfied, the power down control signal is output from the power down determination circuit 206 to the power down output control circuit 2
It is output to 07.

In the compression processing of this embodiment, orthogonal transformation, adaptive bit allocation and coding are performed, but not all processing is necessary depending on the input signal. For example,
When the input signal is 0, it is possible to omit all the processing, and when the energy of the input signal is small, the above-mentioned orthogonal transformation and encoding are necessary, but adaptive bit allocation does not affect the compression rate. It can be omitted accordingly. Further, when the input signal is extremely small, even if the compression process is stopped and one or both of the code of the specific pattern and the zero code is output as the compression result, there is substantially no harmful effect. By omitting a part or the whole of the compression processing as described above, the power down mode can be set and controlled for each processing circuit.

The power-down mode is an intermittent operation mode in which a predetermined operation is processed at a normal speed and then the circuit function is stopped during a margin time Tc after the compression processing as shown in FIG. 12 (e). As shown in (f) of FIG. 12, there are a low-speed processing mode for reducing the operation speed of the processing circuit and an output code replacement mode for outputting a code of a specific pattern.
The system controller 57 in FIG. 1 determines which of these power-down modes to use based on the information from the power supply control circuit 3, but it is always fixed depending on the device and the nature of the input signal. There is no problem in using the operation mode described above. Further, if the power down mode adapted to the input signal is selected in the processing time calculation circuit 204 and the power down determination circuit 206, a better result can be obtained.

In the timer circuit 205, the block sync signal input from the input terminal 202 is used as a trigger to generate the power down cancellation signal Ta shown in FIG. 12B for starting the next processing block, and the power down signal Ta is output. It is sent to the output control circuit 207. The power-down cancellation signal Ta is the time in which the processing circuit is in the power-down mode state after the power-down signal is generated, and is the time for each processing circuit to shift from the power-down mode to the normal operation mode. It is shorter than the processing block time length T. Here, it is more effective if each processing circuit is configured to independently generate the power-down cancellation signal Ta.

In the power-down output control circuit 207, the power-down mode information sent from the power-down decision circuit 206 and the power-down cancellation signal Ta sent from the timer circuit 205 are used, as shown in FIG. A power down signal to be sent to each processing circuit is generated and output from the output terminal 208. The time of this power down signal is
The power-down cancellation signal Ta is the time obtained by subtracting the delay time Td by the power-down detection circuit, that is, the power-down signal output time Te. Further, the processing pause time in the intermittent operation mode and the replacement period Tf in the output code replacement mode
Is a value obtained by subtracting the calculation processing time Tb from the power down cancellation signal Ta. On the other hand, the low-speed processing period Tg is the same time as the power-down signal output time Te.

The power down detection circuits 31 and 3 in FIG.
Since 2 and 33 act independently for each frequency band, for example, when inputting only a specific band such as a 1 kHz sine wave input, or an input signal containing a lot of silent parts, for example, speech of conversation or the like. This is particularly effective when a signal is input. In the present embodiment, the power down mode is set by the two mode states of the intermittent operation mode and the low speed processing mode as described above. However, these two mode states are used together.
Alternatively, good results can be obtained even when switching is performed.
In this case, the control method according to the characteristics of the power supply, that is,
It is more effective to use the power down mode in the intermittent operation mode in the case of a power supply resistant to a large current load for a short time, and in the low speed processing mode in the case of a power supply resistant to a constant current load. Further, the effect is increased by selecting or using the above-mentioned two mode states depending on the remaining charge of the battery.

Further, it becomes more practical by constructing the entire high-efficiency coding apparatus shown in FIG. 2 using a Digital Signal Processor (DSP). FIG. 13 is a block diagram showing a schematic configuration in the case where the high-efficiency coding device is configured by a DSP. When the high-efficiency encoder shown in FIG. 2 is realized by the DSP shown in FIG. 13, the input terminals 10 and 3 shown in FIG.
5 input signal and output terminals 25, 26, 27, 2
Output signals from 8, 29 and 30 are transmitted to the data I / O controller 130 via the data input / output terminal 122 in FIG.
30 is a data memory 135 via the data buses A and B.
To send and receive signals. Further, the block sync signal from the input terminal 34 in FIG. 2 is the interrupt input terminal 1 in FIG.
25, it is input to the program interrupt controller 133 as an interrupt processing signal, and this interrupt processing signal is sent via the data buses A and B to the data I / O controller 130, the program decode controller 131, the program address controller 132, and the data ALU1.
34, data memory 135, and program memory 136.

The main clock signal of the DSP is generated by the clock signal generator 128 and input / output terminal 12
4 is sent and received. The data signal is input / output through the input / output terminal 123 by switching by the external data bus switching circuit 127, and the address signal generated by the address generating circuit 129 is transferred to the data memory 135 and the program via the address buses A and B. The data is transmitted to the memory 136 and input / output from the input / output terminal 121 by switching by the address bus switching circuit 126.

When the transition to and from the power down mode is performed by using this DSP, the control in the power down mode by the power down determination circuit 206 in FIG. 11 is also controlled by the program in the program memory 136. After the program itself shifts to the power-down mode by this program, the power-down mode is canceled at the rising edge of the block synchronization signal input from the interrupt input terminal 125.

FIG. 14 shows the ATC decoder 7 in FIG.
3, that is, a schematic configuration of a decoding circuit for recombining the high-efficiency coded signal as described above. The output signals from the output terminals 25, 26 and 27 in FIG. 2 which are the quantized MDCT coefficients of each band are input terminal 1
Decoding circuits 146, 14 via 52, 154, 156
7, 148, and output terminals 28, 29 in FIG.
Data of sub information such as used block size information, which is an output signal from 30, is input terminals 153, 155, 1
Decoding circuits 146, 147, 148 and IM via 57
It is transmitted to the DCTs 143, 144 and 145. In the decoding circuits 146, 147, 148, bit allocation is canceled using the adaptive bit allocation information, and the IMDCT circuit 14
3, 144, 145, the decoding circuits 146, 147,
MDC by the output from 148 and the data of the above sub information
By performing a process opposite to the T process (IMDCT process), the signal on the frequency axis is converted into the signal on the time axis. Above IMD
The signal on the time axis of the partial band from the CT circuit 143 is sent to a band synthesizing filter (IQMF) circuit 141 which performs a process reverse to that of the band dividing filter 11. Also, the above I
The signals on the time axis of the partial bands from the MDCT circuits 144 and 145 are sent to a band synthesizing filter (IQMF) circuit 142 that performs a process reverse to that of the band dividing filter 12, and then to the band synthesizing filter circuit 141. To be In the band synthesizing filter circuit 141, the signals divided into the respective bands are combined into a full band signal to obtain a digital audio signal, and this audio signal is output from the output terminal 140.
Will be output.

The present invention is not limited to the above embodiment, and for example, the recording / reproducing medium (magneto-optical disk 1) and the signal compressing device or decompressing device need not be integrated. It is also possible to connect between them by a data transfer line or the like. Furthermore, for example, audio P
The present invention can be applied not only to CM signals but also to signal processing devices for digital audio (speech) signals, digital video signals, and the like.

Further, the above-mentioned minimum audible curve synthesizing process may be omitted. In this case, the minimum audible curve generating circuit 712 and the synthesizing circuit 707 in FIG. 7 are unnecessary, and the output from the subtractor 704 is inversely convolved by the divider 706 and immediately transmitted to the subtractor 708. Will be done.

Further, there are various kinds of bit allocation methods, and the simplest is to use fixed bit allocation, simple bit allocation by each band energy of a signal, or bit allocation combining fixed and variable components.

[0094]

As is apparent from the above description, according to the digital signal processing device of the present invention, the processing time of the processing circuit in the processing circuit for compressing and / or expanding the digital signal can be increased in the processing circuit. When a part and / or the whole of the processing circuit is paused or when the compression processing is performed by adapting to the input signal, the time required for the processing is calculated, and a part and / or the whole of the processing circuit is reduced so as to eliminate the margin time. The power consumption of the digital signal processing device can be reduced by lowering the operation speed or by omitting and / or simplifying a part and / or the whole of the compression process by adapting to the input signal. As a result, the power supply mounted on the signal processing device can be made small, lightweight, and inexpensive, so that the entire signal processing device can be made small and inexpensive. Further, when the digital signal processing device is operated by a battery, it can be constructed at a low cost as a signal processing device capable of operating for a longer time than the conventional signal processing device.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a digital signal processing device according to the present invention.

FIG. 2 is a block circuit diagram showing a specific example of a high-efficiency compression encoding encoder that can be used for bit rate compression encoding according to the present embodiment.

FIG. 3 is a diagram showing a structure of an orthogonal transform block at the time of bit compression.

FIG. 4 is a block circuit diagram showing a schematic configuration of an orthogonal transform block size determination circuit.

FIG. 5 is a diagram showing a relationship between a change in temporal length of orthogonal transform blocks temporally adjacent to each other and a window shape used in orthogonal transform.

FIG. 6 is a diagram specifically showing the shape of a window used in orthogonal transformation.

FIG. 7 is a block circuit diagram embodying the function of a bit allocation calculation circuit.

FIG. 8 is a diagram showing spectra of bands divided in consideration of each critical band and block floating.

FIG. 9 is a diagram showing a masking spectrum.

FIG. 10 is a diagram in which a minimum audible curve and a masking spectrum are combined.

FIG. 11 is a block circuit diagram embodying the function of a power down detection circuit.

FIG. 12 is a diagram showing the timing of each signal by the power-down detection circuit.

FIG. 13 is a diagram showing a schematic configuration when the high-efficiency compression encoding apparatus according to the present embodiment is configured using a DSP.

FIG. 14 is a block circuit diagram showing a specific example of a high-efficiency compression encoding decoder that can be used for bit rate compression encoding of this embodiment.

[Explanation of symbols]

1 ................... Magneto-optical disk 2 ......... Battery 3 ..... Power supply control circuit 11, 12 ... ..... Band division filter (QM
F) 13, 14, 15 ... Orthogonal transformation circuit (MDCT) 18 ... Bit allocation calculation circuit 19, 20, 21 ... Block size determination circuit 22, 23, 24 ... Adaptive bit allocation encoding circuit 31, 32, 33 ... Power-down detection circuit 53 ..... Optical head 54 .. ··· Magnetic head 56 ···· Servo control circuit 57 ···· System controller 61, 75 ··· LPF 62, 83 ... A / D converter 63 ... ATC encoder 64, 72, 85 ... memory 65 ... Encoder 66 ... Magnetic head drive circuit 71 ... Deco DA 73 ... ATC decoder 74 ... D / A converter 146, 147, 148 ... Decoding circuit 141, 142 ...・ Band synthesis filter (IQM
F) 143, 144, 145 ... Inverse orthogonal transform circuit (IMDC
T) 204: Processing time calculation circuit 205: Timer circuit 206: Power down determination circuit 207:・ ・ ・ ・ ・ ・ Power down output control circuit 304, 305, 306 ・ ・ Power calculation circuit 307 ・ ・ ・ ・ ・ ・ Memory 308 ・ ・ ・ ・ ・ ・ Change extraction circuit 309 ・..... power comparison circuit 310 ..... block size primary determination circuit 311 ..... block size correction circuit 312, 313, 314.・ Delay circuit 317 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Window shape determining circuit 702 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Energy calculation circuit for each band 703 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Convolution filter circuit 707 ......... Combining circuit 708 ... ··· Subtractor 710 ··· Allowable noise correction circuit 712 ··· Minimum audible curve generation circuit 713 ···・ Correction information output circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Mitsuno 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (21)

[Claims] 1. A digital signal processing apparatus for recording and / or reproducing or transmitting and / or receiving a digital signal by compressing and / or expanding the information, and processing in a processing circuit for compressing and / or expanding the digital signal. A digital signal processing device, characterized in that power consumption of the device is reduced by suspending a part and / or the whole of the processing circuit in the margin time. 2. The power consumption of the device is reduced by suspending a part and / or the whole of the processing circuit when a margin time occurs after the actual compression processing. Item 1. The digital signal processing device according to Item 1. 3. The power consumption of the apparatus is calculated by calculating a processing time and / or a margin time in advance before actual compression processing and suspending a part and / or the whole of the processing circuit in the margin time. The digital signal processing device according to claim 1, wherein the digital signal processing device is reduced. 4. A digital signal processing apparatus for recording and / or reproducing or transmitting and / or receiving a digital signal by compressing and / or expanding the information, when the compression processing is performed by adapting to the input signal. A digital signal processing device, characterized in that power consumption of the device is reduced by calculating a time required for processing and reducing an operating speed of a part and / or the whole of the processing circuit so as to eliminate a margin time. 5. A digital signal processing device for recording and / or reproducing or transmitting and / or receiving a digital signal by compressing and / or decompressing a digital signal, adapting to an input signal, and / or a part of the compressing process. A digital signal processing device, characterized in that power consumption of the device is reduced by omitting and / or simplifying the whole. 6. The method according to claim 5, wherein when the input signal is zero or has a certain amplitude or less, a part and / or the whole compression process is stopped and a zero code and / or a specific pattern is output. The described digital signal processing device. 7. A digital signal processing device having the functions of the digital signal processing device according to claim 1, 2, 3, 4, 5, or 6. 8. The ratio of combining the respective functions for reducing the power consumption of the device is fixed or is used together at a ratio adapted to an input signal, or is used alone.
The described digital signal processing device. 9. The main power source of the device is composed of a battery,
9. The digital signal processing device according to claim 7, wherein each function for reducing the power consumption is selected and / or used in combination according to the type of battery, load characteristics, and remaining capacity. 10. The length of a compression / expansion processing block is made variable in accordance with an input signal, and a change in an input signal of a processing block and a change in an input signal of another processing block, and / or a power, or 10. The digital signal processing apparatus according to claim 1, wherein the length of the processing block is determined based on energy or peak information. 11. The length of the processing block is determined based on the change of the input signal of the processing block and the change information of the input signal obtained by the input signal having a time width longer than the maximum of the processing block in terms of time. Claims 1, 2, characterized in that
The digital signal processing device according to 3, 4, 5, 6, 7, 8, and 9. 12. A digital signal processing device having the functions of the digital signal processing device according to claim 10 or 11. 13. The digital signal processing according to claim 12, wherein the ratios involved in the determination of the elements that determine the length of the processing block are fixed or used together at a ratio adapted to the input signal or used alone. apparatus. 14. The input signal is an audio signal, and the frequency width of a quantization noise generation control block for controlling the generation of at least most of the quantization noise in a higher frequency band is made wider. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1
2. The digital signal processing device described in 2 or 13. 15. Dividing a time axis signal into a plurality of bands on the frequency axis and using orthogonal transformation for the division.
And / or performing conversion from a plurality of bands on the frequency axis to a time axis signal, using inverse orthogonal transformation for the conversion, and changing the size of the orthogonal transformation and changing the shape of the window function used at the time of orthogonal transformation. 15. The method according to claim 14, wherein
The described digital signal processing device. 16. When dividing the time axis signal into a plurality of bands on the frequency axis, first divide into a plurality of bands and form a block composed of a plurality of samples for each of the divided bands, Coefficient data is obtained by performing orthogonal transformation for each block of each band, and / or when performing conversion from a plurality of bands on the frequency axis to a time axis signal, inverse orthogonal transformation is performed for each block of each band, 16. The digital signal processing apparatus according to claim 15, wherein each inverse orthogonal transform output is combined to obtain a combined signal on the time axis. 17. A division frequency width in dividing a time axis signal before orthogonal transformation into a plurality of bands on a frequency axis and / or a combination of a plurality of bands on a frequency axis after inverse orthogonal transformation into a time axis signal Combined frequency width from multiple bands,
The digital signal processing device according to claim 16, wherein the digital signal processing device is widened in a substantially high region. 18. The digital signal processing apparatus according to claim 17, wherein the divided frequency width and / or the combined frequency width are made the same in two consecutive lowest bands. 19. The digital signal processing apparatus according to claim 18, wherein the main information and / or the sub information of the compression code is not assigned to the signal components in the band substantially equal to or more than the signal pass band. 20. A QMF for dividing into the plurality of bands and / or converting into a signal on the time axis composed of the plurality of bands.
A filter is used, Claim 16, 17,
18. A digital signal processing device according to 18, 19. 21. The modified discrete cosine transform is used as the orthogonal transform.
The digital signal processing device according to 8, 19, 20.