JPH06268494A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the degradation of noise mergin from being incurred by rise or decline as compared with a power supply potential by the potential between the base and emitter of bi-polar transistors for the output of the bi-polar transistors connected in totem-pole and to obtain output whose power supply potential level is 'H' or 'L'. CONSTITUTION:When the bi-polar resistors 11 and 12 are operated by the input of an input terminal IN1, a latch circuit 15 is operated and NMOS 14 and 17 are gate controlled. Thus, the decline from a high power supply potential Vcc or the rise from a low power supply potential Vss for the potential between the base and the emitter of the bi-polar transistors 11 and 12 are not performed and the 'H' or 'L' of the power supply potential Vcc and Vss levels can be outputted from an output terminal OUT1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device for use in a semiconductor memory device or the like for driving a load having a BiCMOS structure including a bipolar transistor and a CMOS (complementary MOS transistor).

[0002]

2. Description of the Related Art Conventionally, various semiconductor integrated circuit devices such as a driver circuit using BiCMOS have been proposed for speeding up, and one configuration example thereof is shown in FIG. FIG. 2 is a circuit diagram showing a configuration example of a conventional semiconductor integrated circuit device. This semiconductor integrated circuit device is a BiCMOS driver, and has NPN bipolar transistors 1 and 2 connected in a totem pole between a high power supply potential Vcc and a low power supply potential Vss, and an output terminal OUT is connected to the connection point. Has been done. The totem pole connection is a connection configuration that uses an active pull-up to lower the drive source impedance and increase the output current in the transistor-transistor logic (TTL) output stage. It has the advantage that it can be driven without causing The output side of the CMOS inverter 13 is connected to the base of the bipolar transistor 1, and the input side of the CMOS inverter 13 is connected to the input terminal IN. The CMOS inverter 13 and the bipolar transistor 1 form an active pull-up circuit. This active pull-up circuit has the advantages of increasing the output gain and lowering the output impedance as compared with the method of pulling up with a resistive load. An active pull-down circuit for controlling the base of the bipolar transistor 2 based on an input signal from the input terminal IN is connected to the base of the bipolar transistor 2. This active pull-down circuit includes an N-channel MOS transistor (hereinafter, referred to as NM) whose gate is connected to an input terminal IN.
OS) 4 and an NMOS 5 whose gate is connected to the output terminal OUT, the NMOSs 4 and 5 being connected in series between the output terminal OUT and the low power supply potential Vss. The connection point is connected to the base of the bipolar transistor 2. This active pull-down circuit has an advantage that the current gain and operation speed can be improved as compared with the case where pull-down is performed by using a resistive load. In the device of FIG. 2, the inverter 13 constitutes a CMOS logic circuit part, and the bipolar transistors 1 and 2 and the NMOS are formed.
A driving unit that drives a load is configured by the components 4 and 5.

Next, the operation will be described. For example, when an "L" level (hereinafter referred to as "L") is input to the input terminal IN, it is inverted by the inverter 13 and its output becomes the "H" level (hereinafter referred to as "H"), and the bipolar transistor 1 Turns on. At this time, input terminal IN
"L" cuts off the NMOS 4 so that the base current is not supplied to the bipolar transistor 2 and the bipolar transistor 2 is turned off. As a result, the output terminal OUT is
"H" is output from the high power supply potential Vcc through the bipolar transistor 1. When "H" is input to the input terminal IN, it is inverted by the inverter 13, the output of the inverter 13 becomes "L", and the bipolar transistor 1 is turned off. At this time, the NMOS 4 is turned on by "H" input to the input terminal IN, and the charge of the output terminal OUT is supplied to the base of the bipolar transistor 2 through the NMOS 4, so that the bipolar transistor 2 is turned on. As a result, the output terminal OUT outputs “L” via the bipolar transistor 2.

[0004]

However, in the conventional semiconductor integrated circuit device, due to the bipolar transistors 1 and 2 connected to the totem pole, the output signal of the output terminal OUT is based on the power supply potential Vcc or Vss. There is a problem that the noise margin is deteriorated by raising or lowering by the emitter potential V _BE , which is difficult to solve. The present invention provides a semiconductor integrated circuit device that solves the problem of deterioration of noise margin as a problem that the above-mentioned conventional technique has and that can obtain power supply potentials at the “H” output and the “L” output, respectively. Is.

[0005]

In order to solve the above-mentioned problems, the first invention is a semiconductor integrated circuit of BiCMOS structure in which a bipolar transistor connected to a totem pole drives a load connected to its output terminal. In the device, a MOS transistor that controls the conduction state of the bipolar transistor based on an input signal is connected to the output terminal of the bipolar transistor, the potential of the output terminal is compared with a threshold potential, and the MOS is based on the comparison result. And a logic circuit that gate-controls the transistor. In the second invention, the logic circuit of the first invention is configured by a latch circuit having a predetermined threshold potential.

[0006]

According to the first aspect of the present invention, the semiconductor integrated circuit device is configured as described above, so that when the bipolar transistor operates based on the input signal and the output signal is output from the output terminal, it is connected to the output terminal. The specified logic circuit operates,
The logic circuit gate-controls the MOS transistor, and the conduction state of the bipolar transistor is controlled. As a result, the output of the bipolar transistor is suppressed from rising or falling by, for example, the potential between the base and the emitter from the power supply potential, and the output of power supply potential level "H" or "L" is obtained. According to the second aspect of the invention, the logic circuit including the latch circuit compares the threshold potential with the potential of the output terminal, and turns on the MOS transistor until the potential of the output terminal exceeds the threshold potential, for example. As a result, the bipolar transistor is operated so as not to be turned off, and the high speed switching operation is performed. Therefore, the above problem can be solved.

[0007]

1 is a circuit diagram of a semiconductor integrated circuit device showing an embodiment of the present invention. This semiconductor integrated circuit device is
NPN which is an iCMOS driver and is connected to the totem pole between the high power supply potential Vcc and the low power supply potential Vss
Type bipolar transistors 11 and 12, and an output terminal OUT1 is connected to the connection point thereof. The base of the bipolar transistor 11 is connected to the high power supply potential Vcc via a pull-up P-channel MOS transistor (hereinafter referred to as PMOS) 13 having a gate connected to the input terminal IN1. Further, an NMOS 14 for controlling the bipolar transistor 11 is connected between the base of the bipolar transistor 11 and the low power supply potential Vss. Gate of NMOS 14 and output terminal OU
A logic circuit (for example, a latch circuit) 15 that gate-controls the NMOS 14 is connected between the T1 and the T1. The latch circuit 15 is composed of two inverters 1 connected in antiparallel.
5a and 15b, has a predetermined threshold potential (threshold potential), compares the magnitude of the threshold potential with the potential of the output terminal OUT1, and based on the comparison result, NM
It has a function of controlling the gate of the OS 14. An active pull-down circuit that controls the base of the bipolar transistor 12 based on an input signal from the input terminal IN1 is connected to the base of the bipolar transistor 12. The active pull-down circuit has an NMOS 16 having a gate connected to the input terminal IN1 and an NMOS 17 having a gate connected to the output terminal OUT1. The NMOSs 16 and 17 have the output terminal OUT1 and the low power supply potential Vss. And the connection point of the NMOSs 16 and 17 is connected to the base of the bipolar transistor 12. The NMOS 17 is gate-controlled by the latch circuit 15 via the output terminal OUT1. Next, the operation will be described.

For example, assume that the input signal input to the input terminal IN1 transits from "H" to "L". Then P
The MOS 13 begins to turn on and the NMOS 16 begins to turn off. When the PMOS 13 starts to turn on, the high power supply potential Vcc is applied to the bipolar transistor 1 through the PMOS 13.
Current starts to be supplied to the base of 1. In contrast, NM
Since the OS 16 starts to turn off, the base current of the bipolar transistor 12 decreases. When the base current is supplied to the bipolar transistor 11, the potential of the output terminal OUT1 exceeds the threshold potential of the latch circuit 15 due to the potential increase from the bipolar transistor 11, and "H" is applied to the output terminal OUT1. (High power supply potential Vcc) can be obtained. At the same time, the output of the latch circuit 15 turns off the NMOS 14, and further turns on the NMOS 17,
The bipolar transistor 11 is turned on through the PMOS 13, and the bipolar transistor 1 is turned on through the NMOS 17.
2 is turned off, and the operation ends. Next, input terminal IN
A case where the input signal input to 1 transits from "L" to "H" will be described. In this case, the NMOS 16 starts to turn on and the PMOS 13 starts to turn off. When the NMOS 16 turns on, a current flows through the base of the bipolar transistor 12 through the NMOS 16 and the bipolar transistor 12 turns on. As the bipolar transistor 12 turns on more, the bipolar transistor 11 turns more off. The potential of the output terminal OUT1 is the latch circuit 15
When the potential exceeds the threshold potential of, the output terminal OUT1 can obtain "L" (low power supply potential Vss). As described above, in the present embodiment, the latch circuit 15 connected to the output terminal OUT1 controls the gates of the NMOSs 14 and 17, so that the output signal includes the base-emitter potential V _BE of the bipolar transistors 11 and 12. It is possible to obtain outputs of "H" (high power supply potential Vcc) and "L" (low power supply potential Vss) without rising or falling of the minute.
The noise margin can be maximized. Furthermore, the latch circuit 1
Until the threshold potential of 5 is exceeded, the NMOSs 14 and 17 are on, and the bipolar transistors 11 and 12 are not turned off, so high-speed switching is possible.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) Even if the latch circuit 15 of FIG. 1 is configured by another logic circuit having the same threshold potential, the same operation and effect as those of the above embodiment can be obtained. (B) By changing the polarity of the power supply in FIG. 1 or the like, the NPN type bipolar transistors 11 and 12 may be formed of other bipolar transistors, or the PMOS 13 may be an NMO.
It is also possible to configure the NMOSs 14, 16 and 17 by S and the PMOS by PMOS. Further, the active pull-up circuit and the active pull-down circuit of the bipolar transistors 11 and 12 can have other transistor configurations. (C) Although FIG. 1 shows a configuration example of a 1-input BiCMOS driver, it can be applied to a multi-input BiCMOS driver by connecting a multi-input gate to the input terminal IN1.

[0010]

As described in detail above, according to the first aspect of the invention, a predetermined logic circuit is connected to the output terminal of a totem pole-connected bipolar transistor, and the MOS circuit for bipolar control is connected by the logic circuit. Since the transistor is gate-controlled, it is possible to prevent the bipolar transistor from rising or falling by, for example, the potential between the base and the emitter, obtain an output of "H" or "L" of the power supply potential level, and obtain a noise margin. Can be maximized. Moreover, since the logic circuit is provided, for example, it is possible to turn on the MOS transistor and not turn off the bipolar transistor until the threshold potential of the logic circuit is exceeded, whereby high-speed switching can be expected. . According to the second invention, since the logic circuit is configured by the latch circuit, it is possible to control the gate of the MOS transistor with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

11, 12 Bipolar transistor 13 PMOS for pull-up 14, 17 Bipolar transistor control NM
OS 15 Latch circuit (logic circuit) 16 Pull-down NMOS IN1 input terminal OUT1 output terminal Vcc high power supply potential Vss low power supply potential

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having a bipolar transistor and a CMOS transistor, wherein a bipolar transistor connected to a totem pole drives a load connected to an output terminal of the bipolar transistor, and a conductive state of the bipolar transistor is changed based on an input signal. A MOS transistor for controlling, and a logic circuit connected to the output terminal of the bipolar transistor, comparing the potential of the output terminal with a threshold potential, and controlling the gate of the MOS transistor based on the comparison result are provided. A characteristic semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the logic circuit comprises a latch circuit having a predetermined threshold potential.