JPH06266557A - Data processor and data processing method - Google Patents

Abstract

PURPOSE:To perform an arithmetic processing at a high speed by the constitution of less circuits even when the calculating formula of an arithmetic part is complicated without depending on a RAM for arithmetic data to be the exclusive data area of a computing element and a DMAC for directly writing and reading data to be calculated, arithmetic data and result data by contriving the transfer method and holding circuits of the data. CONSTITUTION:A calculation supporting means 12 for supporting the arithmetic processing of a data processing control means 11 is provided separately from the arithmetic part 11A provided in the data processing control means 11. At least, the calculation supporting means 12 is composed of first and second data holding means 12A and 12B, an arithmetic means 12C and an output data holding means 12D. The first data holding means 12A holds the data X to be calculated, the second data holding means 12B holds the arithmetic data Y, the arithmetic means 12C performs the arithmetic processing based on the data X to be calculated and the arithmetic data Y and the output data holding means 12D holds arithmetic result data O.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIG. 9) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Action Example (1) Description of First Example ( 2 to 7) (2) Description of the second embodiment (FIG. 8) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method, and more specifically,
The present invention relates to an apparatus provided with an arithmetic circuit other than an arithmetic circuit of a central processing unit (hereinafter referred to as CPU) and an improvement of an arithmetic processing method. In recent years, models that can perform high-speed calculations have been given priority in the usage of microcontrollers that perform various types of information processing. For this reason, there is a tendency to adopt a method in which a dedicated arithmetic circuit that can operate at a higher speed than that calculated by a CPU is mounted on a microcontroller.

According to this, an arithmetic data RAM is connected to an arithmetic unit that assists the arithmetic processing of the CPU, and the RAM
The data to be calculated and the calculation data that have been expanded are sequentially read out, and the calculation data and the calculation data are processed by the calculator. Therefore, it is necessary to transfer the data to be operated and the operation data to the dedicated data area of the operation unit in advance before the operation processing. This requires a large amount of data processing time, which hinders the speedup.

Further, a direct memory access controller (hereinafter simply referred to as a DMAC) is connected to an arithmetic unit that assists the arithmetic processing of the CPU, and the operated data and the arithmetic data are directly read from the general-purpose RAM via the DMAC. When they are arithmetically processed by the arithmetic unit, the arithmetic result data is directly written to the general-purpose RAM via the DMAC.

Therefore, the data to be calculated and the calculation data depending on the processing performance of the DMAC are input to the calculation unit,
It is necessary to efficiently assign the address of the arithmetic unit so that this operation becomes faster. Therefore, a RAM for arithmetic data, which is a dedicated data area of the arithmetic unit, and a D for directly writing / reading the operated data, the arithmetic data, and the result data
There is a demand for a device and method that can devise the holding circuit and the transfer method without depending on the MAC and can perform high-speed arithmetic processing with a small circuit configuration even when the calculation formula of the arithmetic unit is complicated. ing.

[0006]

2. Description of the Related Art FIG. 9 is an explanatory diagram according to a conventional example. FIG. 9A is a configuration diagram of a data processing device including a calculation data RAM, and FIG. 9B is a configuration diagram of a data processing device including a DMAC. For example,
A first data processing device provided with an arithmetic circuit in addition to the arithmetic circuit of the CPU 1A is shown in FIG.
It comprises an OM (read-only memory) 2A, a general-purpose RAM (writable / readable memory at any time) 3A, a computing unit 4A, and a computing data RAM 5.

With respect to the function of the first data processing apparatus, for example, an arithmetic circuit incorporated in the CPU 1A executes arithmetic processing based on a micro control program read from the ROM 2A. At this time, the calculation processing results that are sequentially executed are stored in the general-purpose RAM 3A. Further, the arithmetic processing result is transferred to the arithmetic data RAM 5 so that the arithmetic unit 4A, which operates faster than the arithmetic circuit incorporated in the CPU 1A, can perform arithmetic operation. As a result, the computing unit 4A causes the computing data R
The operated data X and the operated data Y developed in the AM 5 are read out, and the operation processing is performed based on the operated data X and the operated data Y.

The resulting data O is the operation data RAM 5
Is stored in the memory and is read by the CPU 1A. As a result, the arithmetic processing load of the CPU 1A is entrusted to the arithmetic unit 4A, and the arithmetic processing speed is increased. Also, CPU
A second data processing device provided with an arithmetic circuit other than the arithmetic circuit of 1B has a CPU 1B and a ROM 2 in FIG. 9B.
B, a general-purpose RAM 3B, an arithmetic unit 4B and a DMAC 6.

With respect to the function of the second data processing device, for example, as in the first data processing device, an arithmetic circuit incorporated in the CPU 1B executes arithmetic processing based on a micro control program. At this time, the result of the arithmetic processing executed sequentially is transferred to the general-purpose RAM 3B via the DMAC 6.
Further, in order for the arithmetic unit 4B operating faster than the CPU 1B to perform arithmetic operation, the arithmetic processing result is directly read from the general-purpose RAM 3B via the DMAC 6, and the operated data X and the arithmetic data Y are transferred to the arithmetic unit 4B. Also, the computing unit 4B
Then, the arithmetic processing is performed based on the operated data X and the operated data Y, and the resulting data O is transferred to the general-purpose RA via the DMAC 6.
Written directly to M3B. As a result, the arithmetic processing load on the CPU 1B is reduced as in the first data processing device.
We are entrusting this to B. We are trying to speed up the arithmetic processing.

[0010]

By the way, according to the first data processing apparatus of the prior art, the arithmetic data RAM 5 is connected to the arithmetic unit 4A for assisting the arithmetic processing of the CPU 1A, and the data expanded in the RAM 5 is stored. The calculation data X and the calculation data Y are sequentially read, and the calculation target data X and the calculation data Y are processed by the calculation unit 4A.

Therefore, before the arithmetic processing, the operated data X and the operated data Y must be transferred in advance to the operated data RAM 5, which is a dedicated data area of the operating unit 4A. From this, the entire data processing time becomes "data transfer time + time required for calculation", which requires a large processing time, which hinders speeding up of data processing. The mounting area is increased by the number of circuits of the calculation data RAM 5, and when the number of calculation items exceeds the memory capacity of the RAM 5, it is difficult to use.

Further, according to the second conventional data processing apparatus, D is provided in the arithmetic unit 4B for assisting the arithmetic processing of the CPU 1A.
When the MAC 6 is connected and the arithmetic processing result is directly read from the general-purpose RAM 3B via the DMAC 6 and arithmetic processing is performed by the arithmetic unit 4B on the basis of the operated data X or the arithmetic data Y, the result data O is transferred to the DMAC 6. It is directly written in the general-purpose RAM 3B via the.

Therefore, depending on the performance of the DMAC6,
The overall data processing time is significantly improved compared to the first data processing device. However, the operated data X and the operated data Y are processed by the arithmetic unit 4B by software or hardware.
Therefore, it is necessary to efficiently assign the address of the arithmetic unit 4B so that this operation can be performed faster. It should be noted that the mounting area is increased by the circuit of the DMAC 6 and the operated data X and the operated data Y must be expanded in the general-purpose RAM 3B until the operation processing is completed.

As a result, the processing speed of the arithmetic unit 4B is DM.
Depending on the performance of the AC6, if the performance of the DMAC6 becomes an obstacle when the data processing speed is further increased or the calculation formula of the arithmetic unit 4B becomes complicated, the number of software programs increases. is there. The present invention was created in view of the problems of the conventional example, and is a RAM for arithmetic data, which is a dedicated data area of an arithmetic unit, and a DMAC for directly writing / reading operand data, arithmetic data and result data. Data processing device and data that can perform high-speed arithmetic processing with a small circuit configuration even when the calculation formula of the arithmetic unit is complicated without depending on The purpose is to provide a processing method.

[0015]

[Means for Solving the Problems] FIGS. 1A and 1B are
The principle view of the data processing device and the data processing method according to the present invention is shown. The first data processing device of the present invention is shown in FIG.
As shown in (A), in addition to the arithmetic unit 11A provided in the data processing control means 11, an arithmetic auxiliary means 12 for assisting the arithmetic processing of the data processing control means 11 is provided, and at least the arithmetic auxiliary means. Reference numeral 12 is first and second data holding means 12A, 12B, arithmetic means 12C and output data holding means.
12D, the first data holding means 12A holds the first input data X, and the second data holding means 12B.
Holds the second input data Y, the arithmetic means 12C performs arithmetic processing based on the first input data X and the second input data Y, and the output data holding means 12D holds the arithmetic result data O It is characterized by doing.

In the second data processor of the present invention, as shown in FIG. 1 (B), two or more operation assisting means 12 are connected to the signal line 13 connected to the data processing control means 11. Is characterized by. In the second data processor of the present invention, as shown in FIG. 1 (B), between the two or more operation assisting means 12, the output data holding means 12D of one operation assisting means 12 and the other The switching means 14 is connected between the first data holding means 12A and the second data holding means 12B of the calculation assisting means 12.

Further, the first data processing method of the present invention is a data processing method in which the arithmetic processing is performed separately from the arithmetic processing of the data processing control means 11, at least in the first write cycle, the first input data X. Received the transfer of
After that, the second input data Y is transferred in the second write cycle, the arithmetic processing is performed based on the first input data X and the second input data Y, and the arithmetic result data O
Is transferred in a read cycle.

Further, in the first data processing method of the present invention, the arithmetic processing is performed in the second write cycle.
It is characterized in that it is started upon receiving the transfer of the input data Y. Further, the second data processing method of the present invention is a data processing method in which a plurality of arithmetic processes are performed in addition to the arithmetic process of the data processing control means 11, in which the operation result data O based on one of the arithmetic auxiliary processes is operated on the other. The above object is achieved by using the first input data X or the second input data Y of the auxiliary processing to perform pipeline processing.

[0019]

According to the first data processing device of the present invention, as shown in FIG.
As shown in (A), the arithmetic processing unit 11A provided in the data processing control unit 11 is provided with an arithmetic assisting unit 12,
The calculation assisting means 12 includes the first and second data holding means 12A,
12B, an arithmetic means 12C and an output data holding means 12D.

Therefore, the first input data X is held in the first data holding means 12A, and the second data holding means 12 is held.
When the second input data Y is held in B, the calculating means 12C
Thus, the calculation processing is performed based on the first input data X and the second input data Y, and the calculation result data O is held in the output data holding means 12D. From this, it becomes possible to assist the arithmetic processing of the data processing control means 11 by the arithmetic auxiliary means 12 provided separately from the arithmetic section 11A of the data processing control means 11.

As a result, the calculation means 12C as in the conventional example is provided.
It becomes unnecessary to provide a calculation data RAM which is a dedicated data area for the above and a DMAC which directly writes / reads the calculation target data, the calculation data and the result data. Further, it is possible to omit the calculation data RAM and the DMAC as in the conventional example, and it is possible to have a margin in the mounting area by the circuit scale. Furthermore, even when the calculation formula of the calculation unit is complicated, it is possible to perform high-speed calculation processing with a small circuit configuration.

Further, according to the second data processing apparatus of the present invention, as shown in FIG. 1B, the data processing control means 1
Two or more calculation assisting means 12 are connected to the signal line 13 connected to one. Therefore, the parallel auxiliary arithmetic processing can be performed on the arithmetic unit 11A of the data processing control means 11. For example, as shown in FIG. 1 (B), switching control of the switching means 14 connected between two or more arithmetic assisting means 12, that is, one arithmetic assisting means 12 is performed.
Of the operation result data O held in the output data holding means 12D of the first data holding means 12 of the other operation auxiliary means 12
It is possible to switch between normal parallel data processing and pipeline processing by supplying the data to A or the second data holding means 12B or controlling the transfer switching to another general-purpose RAM or the like.

This greatly contributes to the improvement of the arithmetic processing function of the data processing device and its high speed operation. Further, according to the first data processing method of the present invention,
The first write cycle supplies the first input data X to the first data holding means 12A, and then the second write cycle supplies the second input data Y to the second data holding means 12B. The first input data X and the second
And the input data Y of are processed.

For example, the addresses of the arithmetic means 12C are efficiently allocated so that the first input data X and the second input data Y are transferred to the arithmetic means 12C at high speed by software or hardware. Further, when control is performed to start the arithmetic processing upon receiving the transfer of the second input data Y in the second write cycle, the arithmetic result data O is transferred from the output data holding means 12D to another storage means or the like in the read cycle. Is transferred.

Therefore, it is not necessary to transfer and expand the first input data X and the second input data Y in the dedicated data area of the arithmetic means 12C before the arithmetic processing as in the conventional example.
Further, since the arithmetic processing is started upon receiving the transfer of the second input data Y, the entire data processing time can be set as the data transfer time, and the time required for the operation to be apparently set to “zero”. Is possible.

Even when the calculation formula of the calculating means 12C becomes complicated, the number of programs of software is the first.
The number of control programs for the transfer of the first input data X in the write cycle, the transfer of the second input data Y in the second write cycle, and the transfer of the operation result data in the read cycle can be made equal. This eliminates the dependence on the performance of the DMAC and the like as in the conventional example, and makes the entire data processing time dependent on the first and second write cycles and the read cycle,
It is possible to significantly improve the data processing speed as compared with the conventional example. In addition, it is possible to significantly reduce the processing time and speed up the data processing.

Further, according to the second data processing method of the present invention, the operation result data O based on one operation auxiliary process
Is used for the first input data X or the second input data Y of the other operation auxiliary processing, and the pipeline processing is performed. Therefore, the arithmetic unit 11A of the data processing control means 11
On the other hand, the parallel auxiliary arithmetic processing can be performed at high speed, and it becomes possible to cope with various kinds of arithmetic processing applications only by changing the arithmetic means 12C.

This makes it possible to improve the arithmetic processing function of the data processing device and its high-speed operation.

[0029]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 8 are diagrams for explaining the data processing device and the data processing method according to the embodiment of the present invention. (1) Description of First Embodiment FIG. 2 is an overall configuration diagram of a data processing device according to a first embodiment of the present invention, and FIG. 3 is a configuration diagram of its auxiliary arithmetic unit. 4 (A) and 4 (B) are explanatory views of the address arrangement of the register according to each embodiment of the present invention.
(A), (B) is an explanatory view of the operated register and the operation register. Further, FIGS. 6A and 6B are explanatory diagrams of the result register and the control / status register, and FIG. 7 is an operation flowchart of the auxiliary arithmetic unit according to the first embodiment.

For example, the arithmetic unit of the CPU 21 (hereinafter referred to as ALU
The first data processing device having an arithmetic circuit 22C in addition to 21A is a CP connected to the bus 23 in FIG.
U21, auxiliary arithmetic unit 22, ROM25, general-purpose RA
It comprises an M26 and an interrupt circuit 27. That is, the CPU
Reference numeral 21 is an embodiment of the data processing control means 11 and controls the input / output of the auxiliary arithmetic unit 22, the ROM 25, the general-purpose RAM 26 and the interrupt circuit 27. The CPU 21
Although the ALU 21A is provided therein, the processing function of the ALU 21A may be inferior to that of the arithmetic circuit 22C of the auxiliary arithmetic unit 22 in the embodiment of the present invention.

The auxiliary operation unit 22 is an operation assisting means 12
The register to be operated (hereinafter referred to as register XR
22A, calculation register (hereinafter referred to as register YRE)
22B, an arithmetic circuit 22C, a result register (hereinafter referred to as register OREG) 22D, and a control unit 22E.
The auxiliary arithmetic unit 22 will be described in detail with reference to FIGS.

The ROM 25 stores the micro control program of the data processing device, and is composed of an electrically erasable read-only memory (EEPROM) and an erasable read-only memory (EPROM). General-purpose R
The AM 26 stores data based on the arithmetic processing of the CPU 21 and operation result data (hereinafter simply referred to as result data) O output from the register OREG22D. As the general-purpose RAM 26, a memory that can be written / read / written at any time is used. The interrupt circuit 27 controls an interrupt request generated by the CPU 21 and the auxiliary arithmetic unit 22.

As a result, the AL provided in the CPU 21
The arithmetic processing of U21A can be assisted by the auxiliary arithmetic unit 22. FIG. 3 is an internal configuration diagram of the auxiliary arithmetic unit according to each embodiment of the present invention, and FIG. 4 (A), (B)
5A and 5B are explanatory diagrams of the address arrangement of the registers according to the respective embodiments of the present invention, and FIGS. 5A and 5B are explanatory diagrams of the operand register and the arithmetic register of the auxiliary arithmetic unit.
Further, FIGS. 6A and 6B are explanatory views of the result register and the control / status register, respectively.

For example, the register XREG22A and the register YREG are based on the calculation formula as shown in the formula (1), that is, Σ│X-Y│ (1)
When the value stored in 22B is subtracted and the absolute value of the result is added in order, in FIG.
Is a register XREG22A, a register YREG22B, and a register OREG22D that form each register, and an arithmetic circuit.
22C | XY | arithmetic circuit 221 and Σ arithmetic circuit 22
2, a control circuit 223 constituting the control unit 22E and a control / status register (hereinafter referred to as register AFCS) 224.

That is, the register XREG22A is an embodiment of the first data holding means 12A, and, for example, the processed data which is an example of the first input data X based on the operation reference clock signal CLK of the data processing device. Is a writable / readable register R / W for holding. here,
The register XREG22A has the operation reference clock signal CLK = 2.
In the cycle (first write cycle), the writing of the data to be operated X is completed. The register XREG22A has 16
One set of bit registers and the operand data X are 16 bits without a sign.

In addition, as shown in FIG. 4A, for example, as shown in FIG. 4A, the address arrangement of the register according to each embodiment of the present invention has a memory area in the address map range from the lower address 100H (hexadecimal) to the upper address 300H. General-purpose RAM 26 provided
If you want to use the same address as
Input data (calculated data) X is assigned to the lower address 100H that specifies 22A, and subsequently input data (calculated data) Y is assigned to the address 101H that specifies the register YREG22B. Further, the result data O is assigned to the address 102H designating the register OREG22D.

When assigning the most efficient address in software, it is assigned to an address having a short instruction execution time as shown in FIG. 4A, although it depends on the architecture of the CPU 21. For example, when the data processing operation involves a short instruction execution time such as MOV (transfer instruction), general-purpose register RW, and accumulation rate A, input data (calculated data) X is input to general-purpose register RW0 on the address map. Allocation, then general register RW
Input data (calculation data) Y is assigned to 1. The result data O is assigned to the general-purpose register RW2 on the address map.

As a concrete example of adopting the same address as that of the general-purpose RAM 26, as shown in FIG. 5A, the subtracted number X lower data XD00 to the lower address "000080H" is used.
XD07 is stored in bits 0-7 of register XREG22A. The initial value of bits 0 to 7 of bits 0 to 7 of the register XREG22A is "00000000". Further, the subtracted number X upper data X is set by the upper address "000081H".
D08 to XD15 are stored in bits 8 to 15 and the bit 8
The initial value of ~ 15 is "00000000". The register XREG22A is an arithmetic register that can be written / read at any time.

The register YREG22B is an embodiment of the second data holding means 12B, and similarly, it is writable / readable for holding the operation data which is an example of the second input data Y based on the operation reference clock signal CLK. Register R /
W. Here, the register YREG22B completes the writing of the operand data Y in the second write cycle (signal CLK = 2 cycles) which continues to occur in the first write cycle.

More specifically, as shown in FIG. 5B, the subtraction number Y lower data YD00 to lower address "000082H" is used.
YD07 is stored in bits 0 to 7 of register YREG22B, and the initial value of bits 0 to 7 is "00000000".
Further, the subtracted number Y high-order data YD08 to YD15 are stored in bits 8 to 15 of the register YREG22B by the high-order address "000083H", and the initial values of the bits 8 to 15 are "00".
000000 ". Since the arithmetic operation of the arithmetic circuit 22C is started by performing a write operation (W) to the lower byte of the register YREG22B, this register XREG22
After setting A, register YREG22B is set.

The register YREG22A is an arithmetic register that can be written / read at any time, like the register XREG22A. The operation is started by performing a write operation on the lower side of the operation data of this register YREG22A, and the operation is not performed in the read cycle. The arithmetic circuit 22C is an embodiment of the arithmetic means 12C and performs arithmetic processing based on the operated data X and the operated data Y. For example, the arithmetic circuit 22C is composed of a | X−Y | arithmetic circuit 221 and a Σ arithmetic circuit 222, and the | X−Y | arithmetic circuit 221 is a register Y.
When the writing of the REG22B in the second writing cycle is completed, the subtraction operation of the absolute values of the operated data X and the operated data Y is started.

Further, the Σ operation circuit 222 performs a successive addition process (accumulation rate) on the subtraction result data based on the operation data X and the operation data Y. The operation is YRE
It starts by performing a write operation on the lower byte of G22A. As a result, the data processing is completed in the calculation time = 2 cycles. The register OREG22D is an embodiment of the output data holding means 12D, and is a read-only register that holds the operation result data (hereinafter also simply referred to as result data) O output from the operation circuit 22C.

Specifically, as shown in FIG. 6A, the result value lower data OD00 to O are obtained by the lower address "000084H".
D07 is stored in bits 0 to 7 of register OREG22D, and the initial value of bits 0 to 7 is "00000000".
Further, the result value upper data OD08 to OD15 is stored in the 8 to 15 bits of the register OREG22D by the upper address "000085H", and the initial value of the 8 to 15 bits is "0000000."
It is "0". The register OREG22D is written with the result data O calculated by the write operation of the lower byte of the register YREG22B, and if there is an overflow, the overflow flag (COVF) is set. The register OREG22D is the register AFCS.
It is cleared by the RCLR bit of 224. The register OREG22D is also cleared by reset, the result data O is composed of unsigned 16 bits + overflow flag, and the overflow flag set is inserted in the third cycle.

Further, the control unit 22E uses the register XREG22.
The input / output of A, the register YREG22B, the arithmetic circuit 22C and the register OREG22D is controlled. For example,
The control unit 22E includes a control circuit 223 and a register AFCS224, and the control circuit 223 includes a register XREG22A, a register YREG22B, an arithmetic circuit 22C and a register OREG22.
The operation reference clock signal CLK is supplied to D.

Further, the register AFCS224 is provided in the control unit 22.
It constitutes a part of E and generates an interrupt or outputs a control signal SC to the control circuit 223 based on the control data DC. Specifically, as shown in FIG. 6B, the control data DC is transferred to the register AFCS by the lower address "000086H".
It is stored in 0 to 7 bits of 224. Register AFCS22
For C4, the CIE (calculated interrupt enable) bit is written in bit 7 and the C6 is written in bit 6.
OVF (calculated over flag) bit is written and RCLR (register clear) in bit 0
Each bit is written. Initial value 00-0
Table 1 shows the contents of each bit of the register AFCS224.

[0046]

[Table 1]

For example, in Table 1, the CIE bit is data for permitting the calculation result overflow interrupt and is cleared by reset. Further, writing "0" indicates that the overflow interrupt is prohibited, and writing "1" indicates that the overflow interrupt is permitted. Note that interrupt processing cannot be entered at the end of calculation. The COVF bit is a calculation result overflow flag and is set when the calculation result is over. For example, when the result is "FFFF _H " or more, it is cleared by writing "0" and resetting. The set factor is when an overflow occurs, and the clear factor is "0".
This is the case by writing and resetting. The RCLR bit is a bit for clearing the register OREG22D, and the result data O can be read by writing "0". Also, writing "0" indicates no function / no effect on operation, and writing "1" clears register OREG22D to "0000 _H ".

In this way, according to the data processing device of the first embodiment of the present invention, as shown in FIGS.
An auxiliary arithmetic unit 22 is provided separately from the ALU 21A provided in the CPU 21, and the auxiliary arithmetic unit 22 includes registers XREG22A, YREG22B, | X-Y | arithmetic circuit 22.
1, Σ arithmetic circuit 222, register OREG22D, control circuit
223 and register AFCS224.

Therefore, when the operated data X is held in the register XREG22A and the operated data Y is held in the register YREG22B, the | X-Y | operating circuit 221 outputs the operated data X and the operated data Y based on the operated data X and the operated data Y. Absolute value XY
Is calculated, the calculated result value is added by the Σ calculating circuit 222, and the calculated result data O is stored in the register OR.
It is held in EG22D. From this, the AL of CPU21
The auxiliary arithmetic unit 22 provided separately from the U21A can assist the arithmetic processing of the CPU 21.

As a result, the arithmetic circuit 22C as in the conventional example is provided.
RAM for operation data, which is a dedicated data area for, and direct writing of operation data X, operation data Y, and result data O
There is no need for a DMAC that controls reading. Further, it is possible to omit the calculation data RAM and the DMAC as in the conventional example, and it is possible to have a margin in the mounting area by the circuit scale. Furthermore, even when the calculation formula of ALU is complicated,
It is possible to perform high-speed arithmetic processing with a small circuit configuration.

Next, a data processing method according to the embodiment of the present invention will be described while supplementing the operation of the data processing apparatus of the present invention. FIG. 7 shows an operation flowchart of the auxiliary arithmetic unit of the data processing apparatus according to the first embodiment. For example, in the case where the absolute value difference sum like the calculation formula (1) is calculated at high speed separately from the calculation processing of the CPU 21, FIG.
In step P1, the control / status register (register AFCS) 224 is initialized. At this time, for example, the lower address # 81H value related to the transfer instruction MOV is written in the register AFCS224 based on the micro control program.

Next, at step P2, the data to be operated X is set in the operated register (XREG) 22A. At this time, the processed data X is transferred to the register XREG22A in the first write cycle. Specifically, the subtracted number X lower-order data XD00 to XD07 are registered in the register XREG by the address value # 5555H based on the micro control program.
22A is transferred to bits 0 to 7, and the subtracted number X upper data XD08 to XD15 is transferred to bits 8 to 15.

Then, in step P3, the operation register (Y
REG) 22B to set the calculation data Y. At this time, the operation data Y is transferred to the register YR by the second write cycle.
Transferred to EG22B. Specifically, the subtraction number Y lower data YD00 to YD07 is transferred to bits 0 to 7 of the register YREG22B by the address value #AAAAH based on the micro control program, and the subtraction number Y higher data YD08 to YD.
Fifteen is transferred to bits 8-15.

Next, in step P4, arithmetic processing is performed based on the operated data X and the operated data Y. At this time, data YD00 to YD is written in the lower byte of the register YREG22B.
The write operation of 07 starts the calculation operation.
The XY | operation circuit 221 calculates the absolute value XY based on the data to be operated X and the operation data Y. Further, the calculated value is added by the Σ calculation circuit 222 (accumulation rate). Where the address value # 5555H
If the contents of the calculation of (1) involve the change of the value of the operated data X and the value of the operated data Y, the process returns to step P2 and the register XRE
The data in G22A is rewritten, and in step P3, the data in the register YREG22B is also rewritten. After that, the calculation process is repeated by the number of items set in advance. When the operation content of the address value # 5555H is such that the operation data X value is fixed and only the operation data Y value is changed, the process returns to step P3 and only the data in the register YREG22B is rewritten and set in advance. The calculation process is repeated by the number of terms. The operation result data O, that is, the result value lower data OD00 to OD07 is bits 0 to 0 of the register OREG22D.
7 and the result value upper data OD08 to OD15 is 8 to
Stored in 15 bits.

Thereafter, in step P5, the 16-bit result data O is transferred in the read cycle of the register OREG22D. At this time, by designating the lower address "000084H" to the register OREG22D, the result value lower data OD00 to OD07 are transferred to the bit 0 of the register OREG22D.
7 to 7 and the result value upper data OD08 to OD15 are read from 8 to 15 bits by the upper address "000085H". If there is an overflow, the overflow flag (COVF) is set, and
The RCLR bit in register AFCS224 or a reset clears register OREG22D.

The overflow flag is set when the operation result data O exceeds 16 bits during the operation, and an interrupt request can be generated by setting the overflow flag. Further, at the end of the calculation, the interrupt request cannot be generated. In this way, according to the data processing method of the first embodiment of the present invention, as shown in the operation flowchart of FIG.
By the write cycle of the
After being supplied to the REG 22A, the operation data Y is supplied to the register YREG 22B in the second write cycle, and the operation data X and the operation data Y are processed.

For example, as shown in FIGS. 4 (A) and 4 (B), the arithmetic circuit 22C is configured so that the arithmetic data X and the arithmetic data Y can be transferred to the arithmetic circuit 22C at high speed by software or hardware. Each register XREG22A, YRE
When the addresses of the G22B and the register OREG22D are efficiently allocated and the control is performed so as to start the arithmetic processing upon receiving the transfer of the arithmetic data Y in the second write cycle, the arithmetic circuit 22C operates independently of the CPU 21. And register OREG22D in the read cycle.
The operation result data O is transferred from the RAM to the general-purpose RAM 26 or the like.

Therefore, it is not necessary to transfer and expand the data to be operated X and the operation data Y in the dedicated data area of the operation unit 4A before the operation processing. Further, since the arithmetic processing is started upon receiving the transfer of the arithmetic data Y,
The entire data processing time can be used as the data transfer time, and the calculation is completed by the time the register OREG22C is read. This apparently reduces the time required for calculation to "zero".
It becomes possible to

When the calculation time is shorter than the instruction execution time of the CPU 21, it is not necessary to consider the time until the calculation is completed. That is, if the operation time ≦ the transfer instruction, the required result can be obtained without considering the operation time. Further, the flag for confirming the end is unnecessary. Even when the calculation formula of the arithmetic circuit 22C becomes complicated, the number of software programs is such that the operation data X is transferred in the first write cycle and the operation data Y in the second write cycle is transferred.
It is possible to equalize the number of control programs for the transfer of the operation result data in the transfer and read cycles.

From this, since the arithmetic operation is started only by the data transfer, the arithmetic processing can be performed regardless of the number of arithmetic terms, and the degree of freedom (flexibility) in the number of arithmetic terms increases. Further, it is possible to easily deal with the case where the number of calculation items exceeds the memory capacity of the calculation data RAM. As a result, it is possible to deal with a wide variety of arithmetic processing applications only by changing the arithmetic circuit 22C.

This eliminates the dependence on the performance of the DMAC or the like as in the conventional example, and makes it possible to make the entire data processing time dependent on the first and second write cycles and the read cycle. It is possible to significantly improve the speedup of the data processing speed. In addition, it is possible to significantly reduce the processing time and speed up the data processing.

(2) Description of Second Embodiment FIG. 8 is an explanatory diagram of a data processing device and a data processing method according to a second embodiment of the present invention. In the second embodiment, which is different from the first embodiment, two auxiliary arithmetic units 301 and 303 are provided on the bus 33 connected to the CPU 31,
This is performed by switching between normal parallel data processing and pipeline processing.

That is, the second data processing apparatus of the present invention comprises, in FIG. 8, auxiliary calculation units 301 and 302 and a switching unit 24, and the auxiliary calculation units 301 and 30 are provided.
2 is composed of the auxiliary arithmetic unit 22 according to the embodiment of the present invention. Further, the address arrangement of the register according to the second embodiment of the present invention is such that the operation data X1, operation data Y1, result data O1, operation data X2, operation data Y2 and Result data O2 is assigned.

The switching unit 24 is an example of the switching unit 14, and, for example, the register value of the address map is used for the processed data X2 of the auxiliary processing unit 302, or
This is to switch whether to use the result data O1 of the auxiliary arithmetic unit 301. That is, between the two auxiliary arithmetic units 301, 302, one auxiliary arithmetic unit 30
One register OREG33D and the other auxiliary arithmetic unit 30
The switching unit 24 is connected between the two registers XREG33A. Depending on the micro control program, the switching unit 24 may be connected between the register OREG33D of the auxiliary arithmetic unit 301 and the register YREG33B of the auxiliary arithmetic unit 302.

In this way, according to the data processing device of the second embodiment of the present invention, as shown in FIG.
Two auxiliary arithmetic units 301, 302 on the bus 33 of U31
Are connected. Therefore, the parallel auxiliary arithmetic processing can be performed on the ALU 31A of the CPU 31. For example, in FIG. 8, two auxiliary arithmetic units 301 and 302
Switching control of the switching unit 24 connected between the two, that is, the register OR of the auxiliary arithmetic unit 301.
The operation result data O1 held in the EG33D is transferred to the register XREG33A or the register YRE of the auxiliary operation unit 302.
By supplying it to the G33B or controlling the transfer switching to another general-purpose RAM or the like, it becomes possible to switch between normal parallel data processing and pipeline processing.

Therefore, in the data processing method according to the embodiment of the present invention, the operation result data O1 based on the auxiliary operation processing by the auxiliary operation unit 301 is converted into the operated data X2 or the operation data Y2 of the other auxiliary operation unit 302. By using pipeline processing, CPU3
The parallel auxiliary processing can be performed at high speed for one ALU 31A, and it is possible to cope with a wide variety of arithmetic processing applications only by changing the arithmetic circuit 33C.

This makes it possible to improve the arithmetic processing function of the data processing device and its high-speed operation.

[0068]

As described above, according to the first data processing apparatus of the present invention, the operation assisting means is provided separately from the operation unit provided in the data processing control means, and the operation assisting means is the first operation means. , Second data holding means, arithmetic means and output data holding means. For this reason, a calculation data RAM which is a dedicated data area for the calculation means as in the conventional example.
Also, the DMAC for directly writing / reading the data to be operated, the operation data and the result data becomes unnecessary. Further, since the calculation data RAM and the DMAC as in the conventional example can be omitted, it is possible to have a margin in the mounting area by the circuit scale. Furthermore, even when the calculation formula of the calculation unit is complicated, it is possible to perform high-speed calculation processing with a small circuit configuration.

Further, according to the second data processing apparatus of the present invention, two or more calculation assisting means are connected to the signal line connected to the data processing control means. Therefore, by controlling the operation of the switching means connected between the two or more arithmetic auxiliary means, the data processing is performed while selecting the normal parallel data processing and the pipeline processing for the arithmetic unit of the data processing control means. It is possible to perform parallel auxiliary arithmetic processing that

Further, according to the first data processing method of the present invention, the first input data is supplied to the first data holding means in the first write cycle, and then the second write cycle is performed. The second input data is supplied to the second data holding means, and the first input data and the second input data are processed. For this reason, it is not necessary to transfer and expand the first input data and the second input data in advance in the dedicated data area of the calculation means before the calculation processing. Further, since the arithmetic processing is started upon receiving the transfer of the second input data, the entire data processing time can be set as the data transfer time, and the apparent time required for the operation can be set to “zero”. It will be possible.

Further, even when the calculation formula of the arithmetic means becomes complicated, the number of software programs can be set such that the first input data is transferred, the second input data is transferred, and the operation result data is transferred. It can be made equal to the number of control programs. Further, according to the second data processing method of the present invention, the operation result data based on one operation auxiliary process is used for the first input data or the second input data of the other operation auxiliary process, and the pipeline thereof is used. Processing is performed.

Therefore, the parallel auxiliary arithmetic processing can be performed at high speed for the arithmetic unit of the data processing control means,
It is possible to deal with various uses of arithmetic processing only by changing the arithmetic means. As a result, compared with the conventional example, it is possible to reduce the circuit configuration and increase the data processing speed, which greatly contributes to the provision of a data processing device that has a high calculation function and high-speed operation.

[Brief description of drawings]

FIG. 1 is a principle diagram of a data processing device and a data processing method according to the present invention.

FIG. 2 is an overall configuration diagram of a data processing device according to a first embodiment of the present invention.

FIG. 3 is an internal configuration diagram of an auxiliary arithmetic unit according to each embodiment of the present invention.

FIG. 4 is an explanatory diagram of address arrangement of registers according to each embodiment of the present invention.

FIG. 5 is an explanatory diagram of an operand register and an arithmetic register according to each embodiment of the present invention.

FIG. 6 is an explanatory diagram of a result register and a control / status register according to each embodiment of the present invention.

FIG. 7 is an operation flowchart of the auxiliary arithmetic unit according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram of a data processing device according to a second embodiment of the present invention.

FIG. 9 is an explanatory diagram of a data processing device according to a conventional example.

[Explanation of Codes] 11 ... Data processing control means, 11A ... Calculation section, 12 ... Calculation auxiliary means, 12A, 12B ... First and second data holding means, 12C ... Calculation means, 12D ... Output data holding means, 13 ... signal line, 14 ... switching means, X, Y ... first and second input data, O ... operation result data.

Claims (6)

[Claims] 1. A data processing control means (1) separate from an arithmetic unit (11A) provided in the data processing control means (11).
1) A calculation assisting means (12) for assisting the calculation processing is provided, and at least the calculation assisting means (12) is a first and second data holding means (12A, 12B), a calculating means (12C).
And an output data holding means (12D), the first data holding means (12A) holds the first input data (X), and the second data holding means (12B) holds the second input data. (Y) is held and the calculation means (12
C) performs arithmetic processing based on the first input data (X) and the second input data (Y), and the output data holding means (12D) holds the operation result data (O). Data processing device. 2. The data processing apparatus according to claim 1, wherein two or more calculation assisting means (12) are connected to the signal line (13) connected to the data processing control means (11). 3. The output data holding means (12D) of one of the operation assisting means (12) and the first data holding of the other operation assisting means (12) between the two or more operation assisting means (12). Means (12A) or second data holding means (12
Data processing device according to claims 1 and 2, characterized in that a switching means (14) is connected between B). 4. A data processing method for performing arithmetic processing separately from the arithmetic processing of the data processing control means (11), at least after receiving the transfer of the first input data (X) in the first write cycle, , The second input data (Y) is transferred in the second write cycle, arithmetic processing is performed based on the first input data (X) and the second input data (Y), and the arithmetic result data is obtained. A data processing method, wherein (O) is transferred in a read cycle. 5. The data processing method according to claim 4, wherein the arithmetic processing is started upon receiving the transfer of the second input data (Y) in the second write cycle. 6. A data processing method for performing a plurality of arithmetic processes in addition to the arithmetic process of the data processing control means (11), the arithmetic result data (O) based on one of the arithmetic auxiliary processes.
6. The data processing method according to claim 4, wherein the pipeline processing is performed by using the above as the first input data (X) or the second input data (Y) of the other operation auxiliary processing.