JPH06266510A - Disk array system and data write method and fault recovery method for this system - Google Patents

Abstract

PURPOSE:To reduce the overhead for write with respect to a disk array of RAID (level 5) where data is distributed to improve the processing performance. CONSTITUTION:Even if data #1 to #4 already written in addresses SADR1 to SADR3 in a drive as data belonging to groups different from one another will be rewritten with write data, these write data are regarded as new write data and are written in the idle area of an address SADR4 in the drive in parallel. Updated old data is not read out. A nullity flag is registered in an address conversion table with respect to updated old data, and data is read from the newly written area. When all of data in original parity groups are made ineffective, areas holding these groups are used as idle areas. Effective data in parity groups which are made partially ineffective are justified at a proper timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device capable of high-performance input / output operation and a data method therefor.

[0002]

2. Description of the Related Art In a current computer system, data required by a high-order side such as a CPU is stored in a secondary storage device, and data is written into and read from the secondary storage device as needed by the CPU. It is carried out. A non-volatile storage medium is generally used as the secondary storage device, and typical examples thereof include a magnetic disk device and an optical disk. Hereinafter, the disk device is called a drive.

In recent years, as computerization has advanced, there has been a demand for higher performance secondary storage devices in computer systems. As one solution, a disk array composed of a large number of drives each having a relatively small capacity is considered.

D. Patterson, G. Gibson, and RHKartz; AC
ase for Redundant Arrays of Inexpensive Disks (RAI
In D), the performance and reliability of the disk array (level 3) that divides data and processes in parallel and the disk array (level 5) that distributes data and handles them independently are reported. There is.

First, a level 3 disk array that divides data and performs processing in parallel will be described. The disk array is composed of a large number of relatively small capacity drives. One write data transferred from the CPU is divided, parity data is created from a plurality of divided data, and these data are stored in parallel in a plurality of drives. In the case of reading, conversely, the divided data can be read in parallel from each drive, combined and transferred to the CPU. A group of a plurality of data and error correction data may be called a parity group.
In this specification, this term is also used when the error correction data is not parity data. If one of the drives that stores the divided data fails this parity data and the data cannot be read, the data in the remaining normal drive and the parity data are used to recover the data in the failed drive. It is for restoring the data of. In a device composed of a large number of drives such as a disk array, the probability of failure increases due to an increase in the number of parts, so for the purpose of improving reliability,
Parity data is prepared in this way.

Next, a level 5 disk array in which data is distributed and handled independently will be described. In this method, individual data is treated independently without being divided, parity data is generated from a plurality of data, and these are distributed and stored in a large number of drives having a relatively small capacity. As described above, this parity data is also for restoring the data in the failed disk when a failure occurs in the drive storing the data.

In the secondary storage device of a general-purpose large-scale computer system which is generally used at present, another read / write operation is performed.
Since the drive is being used for a write request, the drive often cannot be used and is kept waiting. Since data is stored in a distributed manner in this disk array, even if read / write requests increase, they are distributed to and processed by a plurality of drives in the disk array, and therefore read / write requests are less likely to be repeated. .

In these disk arrays, as well as general-purpose large-scale computer systems currently in general use,
In the secondary storage device, the storage location (address) of each data is fixed to a predesignated address, and when reading or writing the data from the CPU, the fixed address is accessed. .

In a level 5 type disk array in which data is distributed and handled independently, a large processing overhead is required when creating new parity data at the time of writing. This will be explained below.

FIG. 11 shows a method of creating parity data at the time of writing in a level 5 type disk array in which data is dispersed and treated independently, which is described in the RAID proposed by D. Patterson et al. Show. The data at each address is a unit accessed by one read / write process, and each data is independent.
In the architecture described in RAID, the address for data is fixed. As described above, in such a system, it is essential to set parity data in order to improve reliability. In this system, parity data is created from the data of the same address in each drive. That is, drives # 1 to 4
Parity data is created from the data of the address (1.1) up to and is stored in (1.1) of the drive that stores the parity data. In this system, the read / write processing accesses the data to each drive, as in the current general-purpose large-scale computer system. In such a disk array, for example, when writing data to the address (2.2) of drive # 3, first, drive #
3 (2.2) old data and drive # 5 (2.
The old parity data of 2) is read (step 1), and the exclusive OR of these and the data to be written is created to create new parity data (step 2).

After the creation of the parity data is completed, the write data is stored in the drive # 3 (2.2) and the new parity data is stored in the drive # 5 (2.2) (step 3).

As shown in FIG. 12, in the level 5 disk array, when reading old data and parity data from the drive in which data is stored and the drive in which parity data is stored, the disk rotates on average 1/2 times. Wait, then read and create parity data,
In order to store this newly created parity data and data, it is necessary to wait one more rotation, and therefore, when rewriting data, it is necessary to wait 1.5 rotations on average. In the drive, waiting for the rotation of the 1.5-turn disk is a very large overhead. In order to reduce such an overhead at the time of writing, a method of dynamically converting a write destination address has been applied from Storage Technology Corporation (hereinafter, STK) company for PCT International Publication WO 91/16711, W.
O 91/20076.

According to this prior art, one of the CP
When the data specified by U is updated, the entire data belonging to the virtual track including the data is read into the cache memory, a part of the data is updated with the updated data, and the updated data belonging to the virtual track is cached. When it is evicted from, the data is divided into sector units of the physical track, a new parity group is generated from the divided data or from them and other write data, and it is written to the empty area in the drive. It is like this. At this time, the data belongs to the original virtual track and is invalidated. The length of the data forming the parity group is determined to have the capacity of one physical track of the drive. By collecting valid data from a partially invalid cylinder containing invalid write data and writing it to another area at an appropriate timing, the cylinder is made to be a cylinder consisting of only free area. .

[0014]

According to this method, since the data forming the parity data has the length of the physical track, the capacity of the cache for holding a plurality of data until forming the parity group is large. Become.

It is an object of the present invention to provide a data writing method and an apparatus therefor capable of dynamically writing update data by address conversion using a cache memory having a smaller capacity than holding update data. The purpose is to

[0016]

According to the present invention, a plurality of disk drives and a predetermined length of data transferred from one or a plurality of host devices and newly written to the plurality of disk drives, respectively. In a disk array system having a cache memory for temporarily holding a plurality of write data composed of any of the data having the predetermined length for updating the data already written in the plurality of disk drives, ) From the plurality of write data held in the cache memory, as the data for forming the error correction data group, the write data of the number equal to the predetermined number having the predetermined length is extracted, and the extracted predetermined data is extracted. Error correction data is generated from a predetermined number of write data, and (b) the predetermined number of write data and Error correction data as one error correction data group and are written in parallel to a plurality of empty areas belonging to different ones of the plurality of drives, and (c) the predetermined number of write data If the disk drive contains update data for the written data, the written data is invalidated.

After that, at a proper timing, valid data in the partially invalid parity group is collected to generate a new parity group, and the new parity group is written to the free space, and the original partially invalid parity group is written. Invalidate all valid data in.

[0018]

[Function] The parity data can be created without reading the data and the parity data before the rewriting, and the reading of the old data and the old parity data for the rewriting becomes unnecessary.

Further, since the length of the data forming the parity group is set to a constant data length sent from the host device, the capacity of the cache for holding the write data by the time the parity group is generated is small. Good.

[0020]

【Example】

 Example 1 (1) Outline One example of the present invention will be described below with reference to FIG.

This embodiment comprises a CPU 1, an array disk controller (hereinafter ADC) 2 and an array disk unit (hereinafter ADU) 3. The ADU 3 is composed of a plurality of logical groups 10. Each logical group 10 has m SCSI drives 12 and each SCSI group.
Drive path 9-1 connecting drive 12 and ADC 2
To 4 The number of SCSI drives 12 is not particularly limited in order to obtain the effects of the present invention.
This logical group 10 is a failure recovery unit, and the SCSI drive 12 in this logical group 10 is an error correction data group consisting of m-1 data and parity data generated from them (hereinafter, for simplification, Called a parity group).

Next, the internal structure of the ADC 2 will be described with reference to FIG. The ADC 2 is composed of a channel path director 5, two clusters 13 and a cache memory 7 which is a non-volatile semiconductor memory such as a battery backup. The cache memory 7 stores data and an address conversion table. The cache memory 7 and the address conversion table therein are shared by all the clusters in the ADC 2. The cluster 13 is a set of paths that can operate independently in the ADC 2, and the power supplies and circuits are completely independent between the clusters 13. Cluster 13 is a channel,
Channel path 6 which is a path between the cache memories 7.
2 and each of the drive paths 6-1 to 4 which are paths between the cache memory 7 and the SCSI drive 12 are configured. Each channel path 6-1
4 to drive path 8 are connected via a cache memory 7. The command issued by the CPU 1 is issued to the channel path director 5 of the ADC 2 through the external interface path 4. The ADC 2 is composed of two clusters 13, and each cluster is composed of two paths. Therefore, the ADC 2 is composed of a total of four paths. From this, the ADC 2 can simultaneously accept up to 4 commands from the CPU 1. Therefore, when a command is issued from the CPU 1, it is determined whether the command can be accepted by the channel path director 5 in the ADC 2. FIG. 2 is a diagram showing the internal structure of the channel path director 5 and one cluster 13-1 of FIG. As shown in FIG. 2, CPU 1 to AD
The command sent to C2 is captured by the interface adapter 15, and the microprocessor (MP)
20 checks whether there is a usable path among the external interface paths 4 in the cluster, and if there is a usable external interface path 4, the MP 20 switches the channel path switch 16 to perform command acceptance processing and acceptance. If it is not possible, the CPU1 gives a response that the request cannot be accepted.
Send to.

In Level 3 RAID, basically, error correction data, for example, parity data is generated from a plurality of write data, and the plurality of write data and error correction data are combined into one error correction data. The data groups are distributed and stored in a plurality of drives.

Data other than parity data can be used as the error correction data. However, in the following, for simplification of expression, error correction data will be simply referred to as parity data, and error correction data group will be referred to as parity group, including the case where data other than parity data is used.

The schematic operation of this embodiment is as follows.

The method of writing the write data transferred from the CPU in the first area basically follows the conventional level 5 RAID method.

That is, a plurality of write data are held in the cache memory 7, parity data is generated from the held write data having a length equal to the record length of each physical drive, and these data are set as a parity group. , Writing is dispersed in the first area provided in a plurality of drives in any of the logical groups 12.

The CPU reads the written data.
When it is requested by the CPU, only that data is selectively read and sent to the CPU via the cache memory 7.

When the data for updating the written data is transferred from the CPU, the written data and the parity data in the parity group to which the written data belongs are read to the cache memory 7, and these are read. The new parity data is generated from the updated data and the update data, and the old write data and the old parity data are rewritten with the update data and the new parity data. Therefore, the data in the original parity group will be partially updated.

On the other hand, the method of writing the write data transferred from the CPU in the second area is characteristic of this embodiment. That is, the write data transferred from the CPU and held in the cache memory 7 is equal to the record length, regardless of whether the write data is data for rewriting the data written in any logical group. A predetermined number of the data are collected, parity data is generated from them, and a new parity data group is distributed and stored in a free area in a second area provided in a plurality of drives in one of the logical groups 12. To be done. As a result, the overhead of updating the write data described in the section of the prior art is reduced.

When any one of the plurality of written data is data for updating the written data, the written data is invalidated. As a result, the parity group to which the written data belongs is partially invalidated.

When the above write processing is performed on a plurality of parity groups, the free area in the logical group decreases. Therefore, in this embodiment, valid data in the parity group, which has become partially invalid, is collected in the cache memory 7, a new parity group is created from them, and stored in a free area. The partially invalid parity group for which this collection has been completed is subsequently used as a free area for writing a new parity group.

In this way, when data having a certain address designated by the CPU is written in the second area and then another write data having the address is transferred from the CPU, the latter data is the former data. The data is stored in a position different from the position in the drive where the data is written. That is, the address specified by the CPU is dynamically converted into the in-drive address. Therefore, in the following, the second area is also referred to as an area for dynamic address translation.

Further, in this embodiment, the updated data is not read from the drive and is invalidated. Therefore, unlike the dynamic conversion described in the above-mentioned International Publication, data can be updated at high speed.

(2) Address conversion table In this embodiment, the SCSI drive 12 that constitutes the ADU 3
Uses a SCSI interface drive. C
When PU1 is a large-scale general-purpose computer such as the IBM System 9000 series, the CPU 1 issues commands according to the command system of the channel interface operable by the IBM operating system (OS). Therefore, if a SCSI drive is used as the SCSI drive 12, the command from the CPU 1
It becomes necessary to convert the command into a command based on the command system of the SI interface. This conversion is roughly divided into command protocol conversion and address conversion.

The address conversion table will be described below.

In the following, the data length transferred from the CPU 1 is equal to one sector length of the drive or n times that (n is an integer greater than 1). In the present embodiment, the write data (record) having n times the sector length is divided into a plurality of data (blocks) having a length equal to m times the sector length (m is an integer smaller than n) and processed. However, for simplicity, only the case where the record length of the data transferred from the CPU 1 is always constant will be described below. C
The address designated by PU1 is, as shown in FIG. 13, the position of the cylinder to which the track in which the data is stored belongs, the head address that determines the track in which that data is stored, and the inside of that track. Specify the position of the record. Specifically, the number (drive number) of the drive in which the requested data is stored, the cylinder address (CC) that is the cylinder number in the drive, and the head address (HH) that is the number of the head that selects a track in the cylinder. And the record address (R). Conventional CK
D format compatible magnetic disk subsystem (IB
In M3990-3390), the drive may be accessed according to this address. However, in this embodiment, a plurality of SCSI drives 12 logically emulate a conventional magnetic disk subsystem compatible with the CKD format. That is, the ADC 2 makes the CPU 1 appear as if the plurality of SCSI drives 12 correspond to one drive used in the conventional magnetic disk subsystem compatible with the CKD format. Therefore, the MP20 converts the address (CCHHR) designated by the CPU1 into the address of the SCSI drive. For this address conversion, a table 70 for address conversion as shown in FIG. 3 is used.
(Hereinafter referred to as address table) is used. ADC
The address table 70 is stored in an appropriate area inside the cache memory 7 in the memory 2. In this embodiment, the drive designated by the CPU 1 is a single drive compatible with the CKD format. However, in the present invention, the drive that the CPU 1 recognizes as a single unit is actually composed of a plurality of SCSI drives, and thus is defined as a logical drive. Therefore, the MP of ADC2
20 is the CPU designated address 7 designated by the CPU 1.
1 (which consists of drive number 74 and CCHHR 75) is the SCSI drive address 72 for the SCSI drive 12 (this is the SCSI drive number 77 and the address within that SCSI drive (hereinafter referred to as Add in SCSI).
r) 78)). The address table 70 has a CPU designated address 71 designated by the CPU 1 and an SCS that actually stores data corresponding to it.
An address (SCSI drive address) 72 in the I drive 12, a parity drive address 73 in which parity data corresponding to the data is stored, and an address (cache address) 81 in the cache memory 7
Then, a cache flag 82 indicating whether or not the data exists in the cache memory 7 is stored. When the cache flag 82 is on (1), the cache memory 7
Indicates that there is data in the cache memory, and if it is off (0), it indicates that there is no data in the cache memory 7.

Further, the address table 70 stores a pointer (DM pointer) 76 to the dynamic address conversion table 90 shown in FIG. 4 when performing dynamic address conversion. The SCSI drive address 72 is composed of the SCSI drive number (SCSI drive number) 77 in which data is stored and the SCSI Addr 78 (this is composed of the cylinder address, head address, record number, and sector number in the SCSI drive). In the parity drive address 73, the SCSI drive number (parity drive number) 79 in which the parity data corresponding to the data is stored and the address in the SCSI drive in which the parity data is stored (hereinafter referred to as Addr in parity data) 80 (which is composed of a cylinder address, a head address, a record number, and the number of sectors in the parity drive) is stored. The access flag 84 is used in the second embodiment.

The cache address 81 is the DM pointer 7
If the data determined by the corresponding SCSI drive address 72 in 6 exists in the cache memory 7, the address of this data in the cache memory 7 is registered. If the data is stored in the cache memory 7 in this way, the address table 7
Similarly to 0, the cache flag 82 is turned on (1).
The invalid flag is a flag indicating whether the data determined by the SCSI drive address 72 corresponding to the DM pointer 76 is valid or invalid, and when invalid, ON (1) is registered. The drive flag is a flag indicating whether or not the data is written in the drive. When it is on (1), this data has been written to the drive, and when it is off (0), it has not been written to the drive yet. Indicates.

The address table 70 and the dynamic address conversion table 90 are stored in the address table 70 and the dynamic address conversion table 90 when the system is powered on.
A specific SCS in the logical group 10 by the MP20
It is automatically read from the I drive 12 into the cache memory 7 without involvement of the CPU 1. On the other hand, when the power is turned off, the MP20 automatically stores the address table 70 in the cache memory 7 at a predetermined location in the read SCSI drive 12 without involvement of the CPU 1.

(3) Securing area for dynamic address conversion and other areas The processing of this embodiment will be described in detail below.

First, the user sets, via the CPU 1, an area for storing data for performing dynamic address translation before using the disk array and an area for normal level 5 processing.

When the address is dynamically converted according to the present embodiment, an empty area must be prepared in advance, and when the empty area is exhausted during processing, refilling is performed to secure the empty area. Must. For this reason, in the present embodiment, refilling frequently occurs for data that causes access with extremely high randomness, and therefore address translation is not performed as dynamically as possible. Therefore, the user preliminarily investigates the amount of sequential data that can improve the performance by dynamically performing address conversion, and sets an area for performing dynamic address conversion. As a setting method, at the time of initial setting, the user applies to the ADC 2 the area to be secured in the form of a specific range of the CPU designated address. As shown in FIGS. 3 and 4, in the ADC 2, as shown in FIGS. 3 and 4, the MPS 20 creates an area corresponding to the size of the area for performing the dynamic address translation requested by the user.
Secured in the I drive 12, this SCSI drive 12
Address of area secured in (Addr7 in SCSI
8) is registered in the dynamic address translation table 90. MP
In order to establish a link between one row of the address table 70 and one row of the dynamic address translation table 90, 120 sets the DM pointers 76 of the same value to each row. The CPU designated address belonging to the above-mentioned CPU designated range is called a specific address. When performing dynamic address conversion when the CPU 1 requests data writing later, when a specific address belonging to the above-mentioned CPU-specified range is specified as the write destination, this CPU-specified address is the DM pointer in the address table 70. 76 is registered in one set line. When a CPU-specified address that does not belong to the CPU-specified range is specified by the write request, this CPU-specified address is registered in one row in the address table 70 where the DM pointer 76 is not set. In the dynamic address conversion, not only sequential data but also data for data compression is stored in the area for dynamic address conversion.

Areas for dynamic address translation are distributed and formed in areas of the same address range in a plurality of drives forming each logical group 10. Each area may be composed of a plurality of areas each having a size of a sector unit, or may be composed of a plurality of areas each having a size of a cylinder unit. After the area is set in this way, the actual processing is that when the MP 20 performs address conversion by the address table 70 in the cache memory 7, the address designated by the CPU 1 (CPU designated address 71) The DM pointer 76 is referred to as to whether the address is the address (specific address) of the area where the dynamic address conversion is performed. If the data is the specific address, the data is processed so that the dynamic address conversion is performed. If normal level 5
Process as.

(4) Outline of data write operation Area and level 5 for performing the dynamic address conversion as described above
After setting the area, the following data write processing is performed.

It is assumed that a write command is issued from the CPU 1. First, one of MP20s of ADC2 is CPU1
To CPU specified drive number, write data and CP
After receiving the write command for designating the U-designated address 71, it checks whether processing is possible in each channel path 6 in the cluster 13 to which the MP 20 belongs, and if possible, returns a response indicating that processing is possible to the CPU 1. CP
ADC after receiving a response that U1 can process
Transfer the data to 2. At this time, the ADC2 has MP20
In the channel path director 5, the channel path switch 16 connects the external interface path 4 and the interface adapter 15 to the channel path 6
To establish a connection between the CPU 1 and the ADC 2. CP
After establishing the connection between U1 and ADC2, the data transfer from CPU1 is accepted. The data transferred from the CPU 1 is transferred to the channel interface 21 according to the instruction from the MP 20.
The protocol conversion is performed according to, and the speed is adjusted from the transfer speed in the external interface path 4 to the processing speed in the ADC 2. After the protocol conversion and speed control in the channel interface 21 are completed, the data is stored in the DCC 22.
Then, the data is transferred to the compression circuit 27 in accordance with the data transfer control.

Regarding the data to be compressed, the data transferred to the compression circuit 27 is compressed according to the instruction of the MP20.

The data compressed by the compression circuit 27 is
It is transferred to the channel adapter 24 and stored in the cache memory 7 by the adapter 24. The data which is not compressed is transferred from the DCC to the channel adapter 24 through the through path in the compression circuit 27 and stored in the cache memory 7 in the same manner as the compressed data. The cache memory 7 for storing the write data is preferably made non-volatile by a battery or the like. When the MP 20 confirms that the data is stored in the cache memory 7 in this way, the MP 20 reports a completion report of the writing process to the CPU 1.

By repeating such an operation, a plurality of write data are written in the cache memory 7. At this time, it is determined based on the address table 70 whether or not the address designated for the write data belongs to the specific range of the CPU designated address, and the result is used to determine the write data. , Are stored in the cache memory 7 in groups of data to be written in the dynamic write area and groups of data not to be written. These write data are processed for each group.

The data to be written in the area where the dynamic address translation is not performed is processed as follows.

First, whether or not the address designated by the CPU for each write data is already registered in the address conversion table, that is, each write data is written to update the already written data. It is determined whether the data is the data or the data of the address is written for the first time.

When the number of pieces of written data that are not to be updated reaches a predetermined number, the parity data generation circuit (PG) 36 generates a parity data group from the pieces of data according to the instruction of the MP 20, and the MP 20
Write their write data and parity data,
Determine the free space to write.

That is, by referring to the address table 70, a free area belonging to the above area and having the same in-drive address in a predetermined number of drives in any of the logical groups 10 is selected. Then address table 7
The CPU designated addresses of these write data are registered in 0, and the drive number 77 and drive address 78 of the recording area assigned to these write data, and similar addresses 79 and 80 for the parity data.
Is registered, the cache address 81 is registered, and then the cache flag 82 is set to ON (1).

Then, these parity groups are
Store in the free space allocated above.

When it is determined that the data to be written in the area where the dynamic address translation is not performed is the data for updating the written data, the written data and the writing thereof will be described in detail below. The original parity data in the original parity group to which the existing data belongs is read, new parity data is generated from those data and the write data for update, and the update data and the new parity data are used. So,
Rewrite the original written data and the original parity data. Therefore, the original parity group is rewritten and a new parity group is not generated.

The write operation in this case will be described below with reference to FIG.

(5) Update of Data in Area for Non-Dynamic Address Translation First, the MP1 20 instructs the drive interface 28 to read the written data and the parity data. Specifically, in FIG. 3, when rewriting the data in which the CPU designated address 71 is at the positions of Drive # 2 and ADR3, the MP 20 sets the address table
At CPU designated address 71 (Drive # 2, A
Check each item corresponding to DR3). MP in FIG.
Since 20 has already registered this CPU designated address but the DM pointer 76 is not registered for that address, it judges that this data is data to be processed at level 5, and the SCSI drive address 72 and parity drive address 73 From this, the write destination SCSI drive number 77, SCSI addr 78, parity drive number 79, and parity data addr 80 are recognized. M
P20 is a read request for the data and the parity data from the SCSI interface 12 in which the pre-write data and the parity data already stored in the write destination address are stored in the drive interface 28 by the converted address. Instruct to issue. In the two SCSI drives 12 that have received this read request from the drive interface 28, the Addr 78 in the SCSI and the Addr 80 in the parity data are accessed to write the written data and the parity data to the relevant SCSI.
Transfer from the drive to the cache memory 7. The parity data generation circuit 36 uses the written data, the parity data, and the new write data to generate the MP20.
, The new parity data after the update is created.
The new write data and the new parity data are written to the addresses where the write data and the parity data before the update were stored, respectively.

(6) Writing and updating of data in the area where the address is dynamically converted In this way, the data to be written in the area where the address is not dynamically converted is the already written data. Different processing is performed depending on whether or not the data is updated.

On the other hand, the data to be written in the area for dynamic address conversion is processed as follows.

Such data is grouped by a predetermined number and stored in a free area in the logical group as a new parity group, irrespective of whether or not it is the data for updating the written data.

That is, when the number of such write data reaches a predetermined number, the parity data generation circuit 36 generates the parity data from the data according to the instruction of the MP 20, and the write data and the generated parity. A new parity group is generated from the data. The MP 20 determines a free area in which to write those parity groups. Unlike the case where the dynamic address translation is not performed, the empty area is selected from the areas belonging to the dynamic address translation area.

That is, a free area of a predetermined number of drives in any of the logical groups 10 having the same in-drive address is selected by referring to the dynamic address table 90. After that, the CPU designated addresses of these write data are registered in the address table 70, and further, in the dynamic address table 90, the drive number 77 and drive address 78 of the recording area assigned to these write data, and the parity data. Register similar addresses 79 and 80 for the cache address 81
, The cache flag 82 is set to ON (1), and the invalid flag 91 and the drive flag 83 are registered.
Remains 0.

Then, these parity groups are
Store in the free space allocated above.

When none of the write data forming this new parity group is the data for rewriting the written data, the write operation is completed as described above, but any one of the write data is already written data. When updating, invalidates the written data. Therefore, the original parity group will contain partially invalid data.

The details of writing data to the area for dynamic address conversion will be described below with reference to FIG.

For example, written data # 1 in the SCSI drive SD # 1, then SD # 2 written data # 2, then SD # 3 data # 3, and then written in SD # 4 data #. For 4 the write command is C in order
A case where the PU is issued will be described as an example.

The MP 20 writes these data in the cache memory 7. At this time, information about each data is registered in the address tables 70 and 90 in the cache. The write data # 1 to # 4 before update
Are stored in the cache memory 7, the old data in the cache memory 7 are rewritten, and then the following is performed.

It is assumed that the logical group 10 is composed of five SCSI drives 12. The MP 20 creates parity data when four pieces of write data are prepared in the cache memory 7.

That is, in the dynamic address conversion table 90, the MP 20 sets the invalid flag 91 to off (0), the cache flag 82 to on (1), and the drive flag 8
Look for data where 3 is off (0). The MP 20 checks the number of data items satisfying this condition, and when the number reaches 4, it instructs the parity data generation circuit (PG) 36 to create parity data for the four write data items. M
P20 writes these four data and the newly generated parity data in parallel to the logical drive as one new parity group. For this purpose, the MP 20 first searches for a write destination address. That is, each SCSI
Search for a space where all the data # 1 to data # 4 and parity data can be written in the drive 12. In particular,
In the dynamic address translation table 90, the MP 20 searches the SCSI drives 12 forming the logical group for an area in which the invalid flag 91 of the Addr 78 within the same SCSI is turned on. In this case, it does not matter whether the corresponding parity data is valid or not.

In the following, the CPU designated address 71 of the data # 1 to # 4 is the dynamic address conversion table 9 shown in FIG.
0, data # 1 is DM a-2, data # 2 is D
Mb-3, data # 3 is DM c-1, data # 4 is D
It corresponds to M d-3.

In the case of FIG. 4, it is assumed that the SCSI drives # 1 to 5 constitute the logical group, and drives SD # 1 to SD4.
The invalid flag 91 is turned on in all areas of the address SADR4, and it is determined that the areas # 1 to 4 can be written.

Therefore, with respect to the CPU designated address 71 (specific address) designated by the user as the writing destination of the data # 1, the MP1 20 is the DM a-2 item of the dynamic address conversion table 90 by the DM pointer 76.
It is converted so that it will be written to SADR2 of drive SD # 1, but since dynamic address conversion is performed, it is decided to write to SADR4 in SCSI drive SD # 1 which has been decided as a new write destination after judgment of the write space. To do. Similarly, the MP20 uses the address S of the drive SD # 2.
ADR3 data # 2, SD # 3 SCSI drive 1
Data # 3 of SADR1 of 2 and SA of drive SD # 4
The write data # 2, # 3, and # 4 for updating the data # 4 of the DR3 are also SCSI drives SD # 2 to SD.
It is decided to write to the address SADR4 of # 4.

As described above, after the MP 20 determines the write destination address, the MP 20 sends the SCSI interface SDr 78 (SADR4) in the writable space to the drive interface 28 and each SCSI drive SD.
Instruct to issue a write request to # 1 to SD # 5. The drive interface 28 issues a write command and an Addr 78 in SCSI (SADR4) to the SCSI drive via the drive unit path 9 in accordance with the SCSI write processing procedure. Each SC for which a write command has been issued from the drive interface 28
In the SI drive 12, the instruction Addr7 in SCSI
8 (SADR4) seek, access processing waiting for rotation is performed. After the access processing in the SCSI drive 12 is completed, the cache adapter 14 reads the data from the cache memory 7 and transfers it to the drive interface 28. The drive interface 28 transfers the transferred data to the corresponding SCSI drive 12 via the drive unit path 9. Addr78 in the SCSI of the relevant SCSI drive 12 of data (SA
When the writing to DR4) is completed, the SCSI drive 12 sends a completion report to the drive interface 28, and reports to the MP 20 that the drive interface 28 has received this completion report. At this time, MP20
If this write data is not left in the cache memory 7, the cache flag 82 of the address table 70 is turned off based on this report. Similarly to the data, the parity data is written according to the parity drive address 73. Further, when the write address is dynamically converted in this way, when the drive interface 28 receives the completion report from the SCSI drive 12,
The DM pointer 76 for the CPU designated address 71 designated as the writing destination by the user of the address table 70
Value is changed to the value of the DM pointer 76 corresponding to the SCSI drive address 72 after writing in the dynamic address conversion table 90. At this time, each item of the dynamic address translation table 90 is also changed at the same time. Specifically, in the address table 70 of FIG. 3, when the CPU 1 instructs to write the data # 1 in the ADR1 of the Drive # 1, when the data # 1 is dynamically converted as described above, DM pointer 76 is DM
Since it is a-2, the dynamic address translation table 9
0, the address SA of the SCSI drive SD # 1
DR2 was compatible. After the data # 1 is written by the dynamic address conversion, the MP1 20 has the Drive # 1 of the address table 70 and the DM pointer 7 of the ADR1.
6 is changed from DM a-2 to DM a-4. At the same time, the MP 20 turns off (0) the invalid flag 91 of DM a-4 and turns on (1) the drive flag 83 in the dynamic address translation table 90, and when the write data is left in the cache 7, the cache address 81 The address is registered in and the cache flag 82 remains on (1). In the future, when the user issues a read request for this data, the previously stored address is not accessed but the newly stored address is accessed.

At the same time, the dynamic address translation table 9
0, invalid flag 9 of DM a-2 before writing
1 is turned on (1), and the cache flag 82 and the drive flag 83 are turned off (0). This area will be used as a space for another writing later.

The write operation to the drive as described above is performed by each SCSI drive 1 constituting the logical group 10.
2 in parallel. Hereinafter, the above write operation is also referred to as batch write.

In this way, for the area where the dynamic address conversion is performed, the write data is stored in the cache memory 7 regardless of whether or not the write data updates the written data, and a predetermined number of the stored data is stored. Parity data is created from the write data, and the write data and the parity data are written in parallel to the plurality of SCSI drives 12. No reading is performed on the pre-write data and the parity data which are already stored in the write destination address designated by the user as in the conventional level 5.
Therefore, it becomes possible to reduce the overhead at the time of writing.

However, when the address of the write data is dynamically changed and stored, the areas in which the invalid flag 91 is turned on (1) are dispersed, so that the data storage efficiency (storable in the SCSI drive can be increased). If the ratio of the actually stored data capacity to the data capacity) decreases and further such a state progresses, there will be no free area for batch writing by dynamic address translation. This is dealt with by refilling the data described later.

Since data is stored in parallel in a plurality of areas having the same in-drive address in this embodiment,
It is desirable to synchronize all rotations of each SCSI drive 12 in the logical group 10.

(7) Failure Recovery When some invalid data exist, if a SCSI drive in the logical group 10 fails, the data and parity data in the remaining SCSI drives 12 excluding the failed SCSI drive Due to obstacle S
It is possible to restore the data in the CSI drive. When such failure recovery is performed, the data in which the corresponding invalid flag 91 in the cache memory 7 in each SCSI drive 12 is turned on is also read as valid data and used to restore the failure data. Invalid flag 9
The data in which 1 is turned on is old data before updating, but has a value when the parity group to which it belongs was generated. Therefore, it can be used to recover the data of the failed drive. Therefore, in the present embodiment, when the data already written in the dynamic address translation area is updated, the invalid flag is attached to the data, but the data is not erased for that reason.

(8) Dynamic Address Translation Area and Non-Dynamic Address Translation Area First, the data storage area will be described. In this embodiment, the amount of data actually stored in the area of the SCSI drive 12 where dynamic address translation is performed is 1 / V of the maximum capacity that can be stored in the area where dynamic address translation is performed. This is because the address of the write data is dynamically converted and the batch writing is performed, so that an area (rewriting area) in which the batch writing is performed is required. That is, SCSI
If the maximum writable data is stored in the area of the drive 12 where the dynamic address conversion is performed, if a write request is issued later, there will be no place to write even if batch writing is attempted. is there. In a large-scale general-purpose computer, the user reserves an area (capacity) that he can use in advance. The user reads the data,
When writing, it is necessary to process within the area corresponding to this capacity. If the usable area (capacity) is exceeded, a new area (capacity) must be secured. Therefore, as shown above, the user
When setting the area for dynamic address translation by 1,
An area to be rewritten is reserved in advance for a later write request, and the area is secured ((V-1) / V).

The ratio of the rewritable area to be reserved in advance is random for random data when dynamic address translation is performed not only for sequentially accessed data but also for partially randomly accessed data. If there are many read / write requests to access different addresses, the value of 1 / V should be decreased, and if there are many read / write requests to access relatively similar addresses, the value of 1 / V should be increased. It is desirable to change the value of. Further, in the former case, it is desirable to move the data from the cache memory 7 to the SCSI drive earlier, and in the latter case, conversely, the data should be retained in the cache memory 7 for a long time. 2 for changing 1 / V
There are two ways. First, the user recognizes the amount of random access to the data to be stored in advance and determines the ratio (1 / V) of the data to be stored. The user decides the ratio of the data to be actually stored in the area (capacity) secured by the user, judging from the characteristics of his data. For example, if the rate of access to rewrite the same data one after another is about 30% of all accesses,
The value is set to about 1 / V = 1/2, and the user stores data only in 1/2 of the area (capacity) secured by the user in advance. The other is that the user does not reserve the area (capacity) in advance, but records the history of the addresses accessed by the MP 20 in the ADC 2 for a certain period of time, and obtains the random access ratio from the address history data. , ADC
The ratio (1 / V) of the data stored in the MP20 of 2 is automatically assigned. For example, if the SCSI drive 12 stores 4/5 of the amount of data that can be stored and the ratio of random access to this data increases, the data is moved to another logical group at any time, and MP1 2
0 reduces 1 / V. (9) Refilling the partial invalid parity group However, even if the rewrite area is secured in advance in this way, the capacity of data that can be stored in one SCSI drive 12 is finite, so when batch writing is repeated,
The rewriting area disappears. So SCSI drive 1
It becomes necessary to collect valid data in 2 and create a new rewriting area. This method will be described below.

FIG. 7 shows the same S in each SCSI drive 12.
The data of Addr78 in CSI is extracted. Each SCSI drive 1 in the logical group 10
Parity data is created by data of two Addr 78 (same row) in the same SCSI, that is, data that should form the same parity group. For example SADR a
, The parity data # 1 is created by the data 1 of the SCSI drive # 1, the data # 5 of the SCSI drive # 2, the data # 9 of the SCSI drive # 3, and the data # 13 of the SCSI drive # 4. In FIG. 7, data # 9 is the only data in which the invalid flag 91 is off in the data group of SADR a. As described above, the invalid data # 1, # 5, and # 13 are left as the data for data restoration in the failed disk when the failure occurs. As for the SADR b, the data with the invalid flag 91 being off is the two data # 10 and # 14, and the SADR
In c, three data # 3, # 7, # 15, SADR
Data d, data # 4, # 8, # 12, and # 16 and the invalid flag 91 are all off. The MP 20 constantly monitors the address table 70 and the dynamic address translation table 90 in the cache memory 7, sees the SCSI drive address 72 and the invalid flag 91 in the dynamic address translation table 90, and belongs to the same parity group, that is, The number of areas in which the invalid flag 91 is turned on (1) corresponding to the same SCSI Addr 78 is recognized, and when the number of areas becomes larger than a preset number, refilling is performed. For example, the number of areas in which the invalid flag 91 is turned on (1) for the same SCSI Addr 78 is 3
When it is set in advance to perform refilling when the number is larger than the number of pieces, if SADR a in FIG. 7 is set to SADR3 in FIG. Then, the MP20 refills. Further, this refilling process can be performed by the user's instruction.

Specifically, the MP 20 makes a pseudo read request for valid data in the partially invalid parity group, that is, in the present example, for data at the address SADR3 of the drive SD # 3 in FIG. Is issued, this data is pseudo-read to the cache memory 7 and stored in the cache memory 7, and other write data transferred from the CPU 1 or data pseudo-read from another line are also used. The following four data are paired, new parity data is created from them, and a free space for writing is searched at the same time as writing in dynamic address translation,
Store in those areas in parallel. When the data # 9 is read into the cache memory 7, the MP 20 changes the cache address 81 in the address table 70 in the cache memory 7 and turns on the cache flag 82. After the storage in the rewriting area, each item of the address table 70 and the dynamic address conversion table 90 is changed similarly to the writing of the dynamic address conversion.

As another refilling method, as described above, it is not performed as soon as the partially invalid parity group satisfies the refilling condition, but a read request is issued from the CPU 1 to such data, and the SCSI is sent. There is a method to be performed when it is read from the drive 12. That is, at the same time that the data is transferred to the higher-level device, it is stored in the cache memory 7 and write data or data similarly sucked from another row and new parity data are created, and these data parity data are stored in the parity data. The SCSI drive 12 is stored in each rewriting area.

The trigger for activating the refill may be the following.

That is, this is performed when the number of partially invalidated parity groups exceeds a predetermined limit number. At this time, the number of parity groups in which even the number of invalid data is included is counted, and when the count value exceeds a predetermined number, refilling is performed. With this method, the counting operation is simple.

On the other hand, a method may be used in which the number of parity groups including a predetermined number or more of invalid data is counted and the refilling is activated when the count value exceeds the predetermined number. With this method, the number of times of refilling can be limited.

As another method, a method may be performed when the capacity of the free area becomes equal to or less than a predetermined value.

More preferably, of the data write capacity secured by the user via the CPU 1,
A method may be used in which the ratio of the capacity of the free area becomes equal to or less than a predetermined value.

At the stage of storing in the rewriting area, the address table 70 and the dynamic address conversion table 90 are updated in the same manner as at the time of writing. When the invalid flags 91 of all the data in the row are turned on in this way, the row is set as a free area (rewrite area).

Regardless of which of the above two methods is used, the above refilling is performed when the read / write request issued to the logical group 10 is relatively small, especially when the write is small, the system read / write. It is effective because there is little reduction in request processing efficiency.

(10) Reading of data When the MP20 recognizes the command of the read request, CP
The MP 20 refers to the address table 70 from the CPU designated address 71 (drive number 74 and CCHHR 75) designated by U1 and performs dynamic address translation for that address depending on whether the DM pointer is registered or not. Whether or not the data is being carried out is determined. If not, the address conversion is continued by the address table 70 into the SCSI drive address 72 of the data. At the same time, the cache flag 82 in the address table 70 is checked to determine whether the data exists in the cache memory 7. On the other hand, the address table 7
If it is registered in the DM pointer 76 of 0 and the dynamic address translation is being performed, the address translation is performed by the dynamic address translation table 90. However, the address in the drive in which the invalid flag is off is used. Thus, even if a plurality of CPU-specified addresses are registered in the table 90, the recently written data can be read.

At the time of a cache hit, the MP 20 sends the CPU-specified address 71 designated by the CPU 1 to the address table 70 or the dynamic address conversion table 90.
(Drive number 74 and CCHHR 75) is converted into an address (cache address 81) of the cache memory 7, and the data is read out to the cache memory 7. Specifically, the data is read from the cache memory 7 by the cache adapter circuit 24 under the instruction of the MP 20. The cache adapter 24 is the cache memory 7
This is a circuit for reading and writing data to and from the MP20 according to an instruction, and is a circuit for monitoring the state of the cache memory 7 and performing exclusive control for each reading and writing request. Since the data compressed by the compression circuit 27 is also stored in the cache memory 7, the data read by the cache adapter 24 is sent to the compression circuit 27. The data that has not been data-compressed passes through the compression circuit 27 as it is, but the data that has been data-compressed is expanded by the compression circuit 27 to the original data that has been transferred from the CPU 1 and has not been compressed. Compression circuit 27
The data passed through is transferred to the channel interface circuit 21 under the control of the data control circuit (DCC) 22. The channel interface 21 converts the protocol into a channel interface protocol in the CPU 1 and adjusts the speed to a speed corresponding to the channel interface.
After this protocol conversion and speed adjustment, in the channel path director 5, the channel path switch 16 selects the external interface path 4 and the interface adapter 15 transfers data to the CPU 1.

On the other hand, when there is a cache miss, the MP 20 instructs the drive interface 28 to issue a read request to the drive 12 according to the SCSI drive address 72. Drive interface 28
Then, according to the read processing procedure of the SCSI interface, the read command is issued to the drive unit path 9-
Issued via 1 or 9-2. In the drive 12 to which the read command is issued from the drive interface 28, a seek and rotation waiting access process is performed to the designated address in the SCSI drive (Addr 78 in SCSI). After the access processing in the drive 12 is completed, the drive 12 transfers the data to the drive interface 28 via the read drive unit path 9. The drive interface 28 transfers the transferred data to the cache adapter circuit 14 on the drive side, and the cache adapter 14 stores the data in the cache memory 7.
At this time, the cache adapter 14 reports to the MP 20 that data is stored in the cache memory 7,
Based on this report, 20 turns on the cache flag 82 corresponding to the CPU designated address 71 of the address table 70 or the dynamic address conversion table 90 that the user has issued and issued the request, and sets the address in the cache memory 7 as follows. To update. The drive number and CCH specified as the address of the read request destination from the CPU1
A CPU-specified address 71 (drive number 74 and CCHHR 75) in the address table 70 is searched for the HR, and the address in the cache memory 7 storing the corresponding data is written in the cache address 81 in correspondence with the CPU-specified address 71. . At the same time, the cache flag 82 is turned on. After storing the data in the cache memory 7, turning on the cache flag 82 of the address table 70 or the dynamic address conversion table 90, and updating the address in the cache memory 7, the CPU 1 is affected by the same procedure as the cache hit. Transfer data.

(11) Modification In the present embodiment, the unit for creating parity data is the same address (cylinder address, head address, and record address are all the same) for each SCSI drive 12 constituting the logical group 10. But,
In order to improve data storage efficiency, parity data can be created even if the cylinder address and the head address are different, if the distances from the index are equal (record addresses are equal), without limiting to the same address. Even in this case, the operation of this embodiment can be performed.

(12) Summary of First Embodiment As described above, in the present embodiment, when writing data to the area where the address is dynamically converted, parity data is generated from a plurality of write data. , A parity group is generated from the write data and the generated parity data, and they are written in a free area. This writing is also applied when each write data is data that updates already written data.

At the time of writing by the conventional RAID of level 5, the written data and the corresponding written parity data are read from the drive, new parity data is generated from these and the update data, and this generation is generated. The written parity data and the data for updating the parity data are written in the area holding the old parity data and the area holding the old write data. Due to the reading of the old data from these two areas and the writing of the new data to those areas, the waiting time such as the rotation waiting of the drive is large as an overhead.

In the present embodiment, by the writing method described above, it is not necessary to read the old data from the drive and write the new data there, which is required in the above conventional example. Therefore, the above overhead does not occur.

Further, in the present embodiment, when a part of a plurality of data forming a certain parity group is rewritten, none of the data in the parity group is read from the drive. In other words, the rewritten data is invalidated, and the other data is retained in the drive as valid data. As a result, the processing at the time of rewriting some data becomes faster.

Further, in the present embodiment, the length of a plurality of pieces of data forming one parity group is made equal to the fixed length of the data sent from the host device. As a result, even if the data in one of the parity groups is partially invalidated, the number of cases in which all the data in the parity data are invalidated increases. In this way, the completely invalid area can be used as it is as a free area without refilling. Therefore, the number of parity groups remaining in the partially invalid state is smaller than that in the case of forming the parity data from the longer data, and as a result, the number of the partially invalid parity groups that need to be refilled is smaller.

Further, in the present embodiment, as a result of making the lengths of a plurality of data constituting one parity group equal to the fixed length of the data sent from the host device, a plurality of write data transferred from the host device are obtained. The size of the in-cache area for temporarily holding the data from them until the parity group is configured may be small.

(Embodiment 2) In this embodiment, FIG.
A function for independently determining whether to dynamically perform address conversion according to the data attribute is added to the ADC 2 shown in FIG. In this embodiment, the sequential data is A
The MP1 20 of DC2 makes a judgment independently and controls so as to store it in the area where dynamic address conversion is performed. In the first embodiment, the MP drive 20 uses the address table 70 or the dynamic address conversion table 90 to actually read or write data from the address 71 designated by the CPU 1 (CPU designated address).
Converted to SCSI drive address 72 for 2.
At the time of writing, after such address conversion, the data sent from the CPU 1 is once stored in the cache memory 7. After that, the data is held in the cache until the data is evicted by the replacement algorithm unique to the cache.

In this embodiment, all write data is temporarily stored in the cache memory 7 and held in the cache memory 7 for a certain period of time. The time held in the cache memory 7 can be preset by the user for the ADC 2, and is controlled by the MP 20 in the ADC 2. The data held in the cache memory 7 is compared with the CPU designated address 71 of the write request issued later as will be described later, and the CPU designated address 71 is compared to determine whether each belongs to the sequential data. The MP 20 independently controls so that the data belonging to the data is stored in the area where the dynamic address conversion is performed.

Therefore, a method of determining whether the data is sequential data in MP120 will be described below.

At the time of writing, after the data is stored in the cache memory 7 from the CPU 1, the MP 120 is C
For the CPU-specified address 71 sent from PU1, the address conversion table in the cache memory 7 is referenced. As shown in FIG. 3, in this embodiment, an access flag 84 is set for each CPU designated address 71 in the address table 70. The access flag 84 is the CPU designated address 71 designated by the CPU 1 at the time of writing.
On the other hand, after the write data is stored in the cache memory 7, the MP120 is turned on (1). After a certain period of time designated by the user in advance, the SC is deleted from the cache memory 7.
At the time of storing in the SI drive 12, the access flag 84 is turned off (0) by the MP 120.

At the time of writing, for the CPU designated address 71 designated by the CPU 1, the MP 120 checks the CPU designated address 71 for which the access flag 84 is ON (1) in the address table 70,
The CPU designated address 71 designated by the CPU 1 is compared with the CPU designated address 71 for which the access flag 84 is ON (1) in the address table 70. Specifically, drive number 74 and CCHHR75
Of the cylinder addresses (CC) of. If the CPU designated address 71 of the data issued before and stored in the cache memory 7 (the access flag 84 is on (1)) and the CPU designated address 71 of the write request issued later are compared, the drive If the numbers 74 match and the cylinder addresses of the CCHHR 75 match, these writing processes are determined to be sequential processes. Similarly, the CPU-specified address 71 is compared also with the write request issued next. In this way
Regarding the issued write request data, MP1 2
0 determines whether the process is sequential or not for a predetermined time set by the user. In the case of sequential data, the MP1 20 uniquely sets the SCSI data for the group of sequential data.
Write control is performed in an area of the drive 12 where dynamic address conversion is performed. Specifically, similar to the first embodiment, the address table 70 and the dynamic address table 90 are registered, and the write process from the cache memory 7 to the SCSI drive 12 is performed.

(Embodiment 3) In this embodiment, as shown in FIG. 8, a sub DKC 11 is provided for each logical group 10 and the cache memory 7 shown in Embodiments 1 and 2 is provided therein.
The address table 70 and the dynamic address conversion table 90 in FIG. Of the data processing procedure in this embodiment, only the portions different from the processing procedures shown in the first and second embodiments will be described with reference to FIGS.
In this embodiment, as shown in FIG. 10, the address table 70 and the dynamic address conversion table 90 in the cache memory 7 shown in the first and second embodiments are used as the data address table (DA) in the sub DKC 11 for each logical group 10 unit.
T) Divide into 30. The format and function of the stored table of the DAT 30 are similar to those of the first and second embodiments, except that they are held in a dedicated memory for storing an address conversion table different from the memory for storing write or read data. That is the point. A group address table (GAT) 23 as shown in FIG. 5 is stored in the cache memory 7 in the ADC 2, and the MP 20 uses this GA.
The CPU designated address 71 designated by the CPU 1 at T23 determines which logical group 10 in the ADU 3 is the location designated by the CPU designated address 71.

When the read request from the CPU 1 is transferred, the CPU designated address 7 designated by the CPU 1
1, the MP 20 determines the logical group 10 by the GAT 23, and the MP 20 drives the drive interface 2 so as to issue a read request to the logical group 10.
Tell 8. The drive interface 28 that has received the instruction from the MP 20 sends the sub DKC 1 of the logical group 10 concerned.
Issue a read request to 1. In the sub DKC 11, the microprocessor MP29 accepts the read request command, refers to the DAT 30, and stores the data in the same manner as the MP 20 shown in the first embodiment processes using the address table 70 and the dynamic address table 90. The SCSI drive address 72 and the parity drive address 73 for the CPU designated address 71 in the logical group 10 that has been set are determined. After the address is fixed, the MP is processed in the same manner as the MP20 process in the first embodiment.
29 issues a read request to the SCSI drive 12. S issued a read request from MP29
The CSI drive 12 waits for seek and rotation, transfers the data to the drive adapter circuit 34 as soon as the data can be read, and drives the drive adapter 34.
Is stored in the sub cache memory 32. After the storage of the data in the sub cache memory 32 is completed, the drive adapter 34 reports the storage to the MP 29, and the MP2
9 is a CP in the DAT 30 like the MP 20 in the first embodiment.
The cache flag 8 corresponding to the U designated address 71
2 is turned on (1), and the address stored in the sub cache 32 is registered in the cache address 81. When a read or write request is issued for the data whose cache flag 82 is ON later, the processing is performed in the sub cache 32. DAT 30 by MP3 29
When the update of the
When a response indicating that data transfer is possible is sent to the live IF 28, and the Drive IF 28 receives this response, M
Report to P120. When the MP1 20 receives this report, if it can be stored in the cache memory 7,
It instructs the Drive IF 28 to transfer the data from the sub DKC 11. In Drive IF28, when the instruction from MP1 20 is received, M of sub DKC 11
A read request is issued to P3 29. The MP3 29 receiving this read request instructs the sub cache adapter circuit (SCA) 31 to read the data from the sub cache 32, and the SCA 31 actually reads the data and transfers the data to the Drive IF 28. After the Drive IF 28 receives the data, the processing shown in the first and second embodiments is performed.

On the other hand, at the time of writing, the logical group 10 is fixed and the MP of the logical group 10 is determined as in the case of reading.
Issue a write request to 329. After accepting the write request and storing the write data in the sub-cache 32, for the data to be dynamically converted and stored, as shown in the first and second embodiments, the dynamic address is converted and the data is written to the drive 12. If dynamic address translation is not performed, level 5 processing is performed. In this embodiment, the sub DKC is used.
The PG 36 creates parity data in the data stored in the sub-cache 32 in 11. In this way, load management can be achieved by performing address management and data processing in the drive 12 in the sub DKC 11.

In FIG. 8, each logical group 10 has a sub DKC 11, but one sub DKC 1
One may manage a plurality of logical groups 10. In this way, the sub DKC 11 for the plurality of logical groups 10 is
The DAT 30 can be collectively managed by collecting the above.

Although the first and second embodiments have been described with respect to the magnetic disk, they are also applicable to a storage device such as an optical disk and a floppy disk.

[0112]

As described above, according to the present invention, the method of writing a parity group including a plurality of write data and parity data generated from them into an empty area in the drive allows the data to be rewritten more than before. It can be done at high speed.

Further, according to the present invention, when a part of a plurality of data forming a certain parity group is rewritten, the rewritten data is invalidated, and the other data is retained as valid data in the drive as it is. By doing so, the processing at the time of rewriting data becomes faster.

Further, according to the present invention, if the length of a plurality of data forming one parity group is set to the length of the data sent from the host device, the data in one of the parity groups is partially Fewer parity groups, even if disabled, remain partially disabled than if the parity data were constructed from longer data, resulting in the number of partially disabled parity groups that need to be refilled. Will be less. Therefore, the data to be refilled is reduced. Furthermore, the size of the in-cache area for temporarily holding the plurality of write data transferred from the higher-level device until they form a parity group may be small.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a first embodiment.

FIG. 2 is an internal configuration diagram of a cluster according to the first embodiment.

FIG. 3 is an explanatory diagram of an address table.

FIG. 4 is an explanatory diagram of a dynamic address translation table.

FIG. 5 is an explanatory diagram of a group address table (GAT) used in the third embodiment.

FIG. 6 is an explanatory diagram of a data storage method of the present invention.

FIG. 7 is an explanatory diagram of a refilling operation of the present invention.

FIG. 8 is an overall configuration diagram of a third embodiment.

FIG. 9 is an internal configuration diagram of a cluster according to the first embodiment.

FIG. 10 is an internal configuration diagram of the sub DKC of FIG.

FIG. 11 is an explanatory diagram of a conventional disk array.

FIG. 12 is an explanatory diagram of a writing time according to a conventional technique.

FIG. 13 is an explanatory diagram of an internal address of the drive of the present invention.

[Explanation of symbols]

2 ... Array disk controller (ADC), 3 ... Array disk unit (ADU), 4 ... External interface path, 5 ... Channel path director, 6 ... Channel path, 7 ... Cache memory, 8 ... Drive path, 9 ...
Array disk unit path, 12 ... Drive, 13 ...
Cluster, 14 ... Drive side cache adapter (C
Adp), 15 ... Interface adapter, 16 ... Channel path switch, 17 ... Control signal line, 18 ... Data line, 19 ... Path, 20 ... Microprocessor 1 (MP
1), 21 ... Channel interface (CH IF)
Circuits, 22 ... Data control circuit (DCC), 23 ... Group address conversion circuit (GAT), 24 ... Channel side cache adapter (C Adp), 27 ... Compression circuit, 28
... Drive interface circuit (Drive I
F), 29 ... Microprocessor 3 (MP3), 30 ...
Data address table, 31 ... Sub cache adapter, 34 ... Drive adapter (Drive Adp),
35 ... Drive path, 36 ... Parity data generation circuit,
70 ... Address table, 71 ... CPU designated address,
72 ... SCSI drive address, 73 ... parity drive address, 74 ... drive number, 75 ... CCHH
R, 76 ... DM pointer, 77 ... SCSI drive number, 78 ... SCSI drive address, 79 ... Parity drive number, 80 ... Parity drive address,
81 ... Cache address, 82 ... Cache flag,
83 ... Drive flag, 84 ... Access flag, 85 ...
Logical group address, 90 ... Dynamic address conversion table, 100 ... Group address table (GAT).

Claims (28)

[Claims] 1. A plurality of disk drives and a predetermined length of data transferred from one or a plurality of host devices to be newly written in each of the plurality of disk drives, or already written in the plurality of disk drives. In a disk array system having a cache memory for temporarily holding a plurality of write data composed of any of the data having the predetermined length to be updated, and (a) a plurality of data held in the cache memory. From the write data, as the data for forming the error correction data group, the write data of the number equal to the predetermined number having the predetermined length are extracted, and the error correction data is extracted from the extracted write data of the predetermined number. (B) The predetermined number of write data and the error correction data are combined into a single error. Correction data group is written in parallel to a plurality of empty areas belonging to different ones of the plurality of drives, and (c) the predetermined number of write data is updated to the data already written to the plurality of disk drives. When the data is included, the data writing method includes the step of invalidating the written data. 2. (d) Each time the amount of write data transferred from the one or more host devices is sufficient to retrieve a number of write data equal to the predetermined number having the record length, A data writing method comprising the steps of executing steps (a) to (c) above. 3. The error correction data is generated by holding one write data in a cache memory when one write data is transferred from the one upper device, When one write data is transferred and the amount of other write data already held in the cache is sufficient to retrieve a number of write data equal to the predetermined number having the fixed length, The generation of the error correction data is executed without waiting for another write data to be transferred to the cache from one or more host devices, and the one write data is transferred from the one host device. And the amount of write data held in the cache is not sufficient to retrieve a predetermined number of write data having the fixed length. The number of write data held in the cache, after reaching the predetermined number, the data writing method of claim 1, wherein comprising a step of executing the generation of the correction data Ri above the mis. 4. (d) The steps (a) to (c) are repeated for other write data held in the cache memory, and (e) the step (d) is repeatedly executed, resulting in the plurality of When all the groups of write data belonging to any one of the error correction data groups stored in the drive are invalidated, the subsequent step (a)
Repeating steps (c) to (c), in particular, a plurality of areas in the plurality of drives, which holds the group of write data and the error correction data belonging to the error correction data group, are set as empty areas and any other error occurs. The data writing method according to claim 1, further comprising a step of writing the correction data group. 5. A plurality of disk drives and data transferred from one or a plurality of host devices, each having a predetermined length to be newly written in the plurality of disk drives, or written in the plurality of disk drives. A disk array system having a cache memory for temporarily holding a plurality of write data consisting of any of the data having the predetermined length for which the already-written data is to be updated; Of the write data of which the number is equal to the predetermined number having the predetermined length as the data for forming the error correction data group, and the error correction is performed from the extracted predetermined number of write data. Data of (b) the predetermined number of write data and the error correction data, As one error correction data group, write in parallel to a plurality of empty areas belonging to different ones of the plurality of drives, (c) the predetermined number of write data is data that has been written to the plurality of disk drives. The method for writing data, which includes the step of invalidating the already written data when the update data is included. (d) The steps (a) to (c) are repeated for other write data held in the cache memory, and (e) When one of the plurality of drives fails, the one drive Of a plurality of valid data among the plurality of valid data held in the above, each of the plurality of valid data held in a drive other than the one drive belongs to an error correction data group to which the data belongs. Alternatively, a failure recovery method comprising a step of selectively recovering using invalid write data and error correction data. 6. The result of executing the step (c) for any one group of write data before the occurrence of the failure,
If all the groups of write data that belong to the error correction data group to which any one of the data identified as invalid data in step (c) becomes invalid, the group of write data and its error correction 6. The method according to claim 5, further comprising the step of using a plurality of areas in the plurality of drives, which hold error correction data belonging to a group, as free areas for writing data belonging to another error correction data group. Disaster recovery method. 7. The recovering step selectively selects a plurality of other valid or invalid write data and the error correction data from a drive other than the one drive among the plurality of drives. 6. The failure recovery method according to claim 5, comprising the step of reading and recovering the one valid data from the read written data and the read error correction data. 8. A plurality of disk drives and a predetermined length of data transferred from one or a plurality of host devices to be newly written in each of the plurality of disk drives, or already written in the plurality of disk drives. In a disk array system having a cache memory for temporarily holding a plurality of write data composed of any of the data having the predetermined length to be updated, and (a) a plurality of data held in the cache memory. From the write data, as the data for forming the data group for error correction, the write data of a number equal to the predetermined number having the predetermined length is extracted, and the error correction is performed from the extracted write data of the predetermined number. Data is generated, and (b) the predetermined number of write data and the error correction data are combined into one As an error correction data group, write in parallel to a plurality of empty areas belonging to different ones of the plurality of drives, and (c) update the predetermined number of write data with respect to the data already written to the plurality of disk drives. When the data is included, the data writing method includes the step of invalidating the written data. (d) repeating steps (a) to (c) with respect to other write data held in the cache memory, (e) each including at least one valid write data and at least one invalid write data It consists of the step of refilling multiple valid write data included in multiple error correction data groups (partially invalid error correction data groups), and the refilling is included in (e1) partially invalid error correction data groups. The one or more valid write data being read out selectively from the plurality of drives, and holding the read one or more valid write data in the cache memory,
(e2) The step (e1) is executed on another partially invalid error correction data group, and (e3) the predetermined number selected from a plurality of valid write data held in the cache memory. A new set of valid write data and a new set of error correction data for that set of write data, and thus a new error correction data group is generated, and (e4) the generated A new error correction data group is written again in parallel to the free space in the plurality of drives, and (e5) the steps (e3) and (e4) are repeated for another new error correction data group, and (e6) a plurality of Of the partial invalid error correction data group of, the valid write data contained therein are all rewritten by the steps (e4) and (e5), Other error correction as Data writing method comprising the step of using a writing over data group. 9. The data writing method according to claim 8, wherein said step (e1) or (e2) is selectively performed on a plurality of partially invalid error correction data groups in a specific state. 10. The specific state is a state in which the number of invalid write data included in a partially invalid error correction data group is equal to or more than a predetermined limit number. Data writing method. 11. The data writing according to claim 9, wherein said step (e1) or (e2) is performed on the error correction data group every time any one error correction data group reaches said specific state. Method. 12. The step (e1) or (e2) is performed on a read request transferred from any one of the host devices for valid write data belonging to any one of the error correction data groups in the specific state. 10. The data writing method according to claim 9, which is performed in response to the requested write data. 13. The step (e1) or (e2) above, wherein the number of partially invalid error correction data groups is
The data writing method according to claim 10, wherein when a predetermined number is reached, the data writing method is performed on the plurality of partially invalid error correction data groups. 14. The step (e1) or (e2) is carried out when a plurality of data writing areas included in the plurality of drives have a free space capacity reaching a predetermined limit value. 10. The data writing method according to claim 9, wherein the data writing is selectively performed on the partially invalid error correction data group. 15. The step (e1) or (e2) is carried out when the ratio of the capacity of the free area to the capacity of the area for writing data included in the plurality of drives reaches a predetermined limit ratio. 10. The data writing method according to claim 9, wherein the method is selectively performed on a plurality of partially invalid error correction data groups. 16. The method further comprises the step of writing the write data to the cache memory when new write data is transferred from the one or more host devices, wherein the step (e3) is performed in the cache. When there is new write data transferred from that higher-level device, an error correction including a number of write data equal to the predetermined number, which is composed of the new write data and the write data read in step (e1) 10. The data writing method according to claim 9, further comprising the step of generating a data group. 17. A plurality of disk drives and a predetermined length of data transferred from one or a plurality of host devices and newly written in the plurality of disk drives, respectively, or already written in the plurality of disk drives. In a disk array system having a cache memory for temporarily holding a plurality of write data consisting of any of the data having the predetermined length to be updated (a) held in the cache memory From a plurality of write data, as the data for forming an error correction data group, a number of write data each having the predetermined length and equal to the predetermined number are extracted, and the error correction is performed from the extracted predetermined number of write data. (B) write the predetermined number of write data and the error correction data, As one error correction data group, write in parallel to a plurality of empty areas belonging to different ones of the plurality of drives, (c) the predetermined number of write data is data that has been written to the plurality of disk drives. The method for writing data, which includes the step of invalidating the already written data when the update data is included. (d) repeating steps (a) to (c) with respect to other write data held in the cache memory, (e) each including at least one valid write data and at least one invalid write data It consists of the step of refilling a plurality of valid write data included in the error correction data group (partially invalid error correction data group), and the refilling is either (e1) which is transferred from one of the higher-level devices. In response to a read request for valid write data included in one partially invalid error correction data group, the write data is selectively read from the plurality of drives, and the read write is performed. The data is transferred to the one higher-level device and is retained in the cache memory, and (e2) the steps (e1) and (e2) are performed. And (e3) a new set of write data held in the cache memory and equal in number to the predetermined number selected from the plurality of write data. Error correction data is newly generated for the set of write data, a new error correction data group is generated, and (e4) the generated new error correction data group is stored in the plurality of drives. Writing in the empty area in parallel, (e5) the write data read in step (e1) or (e2) is held in the plurality of drives when rewritten in step (e4), A method for writing data, comprising the step of invalidating the write data before being rewritten. 18. The steps (e3) to (e4) are performed when a partially invalid error correction data group to which the write data read in the step (e1) or (e2) belongs is in a specific state. 18. The data writing method according to claim 17, which is performed. 19. The specific state according to claim 18, wherein the number of invalid write data included in the partially invalid error correction data group is equal to or more than a predetermined limit number. Data writing method. 20. A plurality of disk drives and data transferred from one or a plurality of host devices, each having a predetermined length to be newly written in the plurality of disk drives, or already written in the plurality of disk drives. In a disk array system having a cache memory for temporarily holding a plurality of write data consisting of any one of the predetermined length data to be updated, (a) a plurality of write data held in the cache memory From the above, as the data for forming the error correction data group, the write data of the number equal to the predetermined number each having the predetermined length is extracted, and the error correction data is extracted from the extracted predetermined number of write data. (B) The predetermined number of write data and the error correction data are combined into a single error. Correction data group is written in parallel to a plurality of empty areas belonging to different ones of the plurality of drives, and (c) the predetermined number of write data is updated to the data already written to the plurality of disk drives. When the data is included, the data writing method includes the step of invalidating the written data. (d) repeating steps (a) to (c) with respect to other write data held in the cache memory, (e) each including at least one valid write data and at least one invalid write data It consists of the step of refilling a plurality of valid write data included in the error correction data group (partially invalid error correction data group), and the refilling consists of (e1) any one partially invalid error correction data group. Selectively read at least one of the one or more valid write data contained in the plurality of drives, and temporarily hold the read write data in the cache memory, e2) When new write data is transferred from any one of the host devices, the write data is temporarily transferred to the cache. Held in Interview storage, (e3)
A new set of write data of a number equal to the predetermined number is selected from a plurality of write data held in the cache memory by the step (e1) or (e2), and a new set of write data is newly selected. Generate error correction data, and thus generate a new error correction data group,
(e4) The new error correction data group thus generated is written in parallel to an empty area in the plurality of drives, (e5)
The write data read in the step (e1) is
A data writing method comprising: when the data is rewritten by the step (e4), invalidates the write data held in the plurality of drives before the rewriting. 21. The data writing method according to claim 20, wherein said step (e1) comprises a step of reading all valid data included in any one partially invalid error correction data group. 22. The steps (e3) to (e4) are performed when the partially invalid error correction data group to which the write data read in the step (e1) or (e2) belongs is in a specific state. 22. The data writing method according to claim 21, which is performed. 23. The specific state is a state in which the number of invalid write data included in a partially invalid error correction data group is equal to or more than a predetermined limit number. Data writing method. 24. When a data write area is secured in accordance with a user's request, it is determined by the user's instruction whether or not the area is a dynamic address translation area, and then the one or more host devices The data according to claim 1, wherein the steps (a) to (d) are executed when the write area is determined to be a dynamic address translation area when the data to be written to the area is transferred. Writing method. 25. A disk array system having a plurality of disk drives, comprising: (a) data having a predetermined length to be newly written in each of the plurality of disk drives or already written in the plurality of disk drives. A cache memory that holds a plurality of write data transferred from one or a plurality of higher-level devices, and that is made up of any one of the data having the predetermined length to be updated, and (b) is held in the cache memory. From the plurality of write data, as the data for forming the data group for error correction, the write data of the number equal to the predetermined number having the predetermined length are extracted, and the error is extracted from the extracted write data of the predetermined number. A circuit for generating correction data, and (c) the predetermined number of write data and the error correction data. And (d) means for writing in parallel to a plurality of empty areas belonging to different ones of the plurality of drives as one error correction data group, and (d) the predetermined number of write data is stored in the plurality of disk drives. When the update data for the written data is included in, the written data is invalidated. 26. A group of write data belonging to any one of the error correction data groups stored in the plurality of drives as a result of the invalidation performed by the invalidation unit for a plurality of groups of write data. When all the data become invalid, a plurality of areas in the plurality of drives, which holds the write data of the group and the error correction data belonging to the error correction data group,
26. The disk array system according to claim 25, further comprising means used for writing another error correction data group as a free area. 27. (e) When a failure occurs in one of the plurality of drives, each of a plurality of valid data among a plurality of data held in the one drive is transferred to the one drive. A means for selectively recovering by using a plurality of other valid or invalid write data and error correction data belonging to an error correction data group to which the data belongs, which is held in a drive other than Item 25. The disk array system according to Item 25. 28. (e) A plurality of valid correction data groups included in a plurality of error correction data groups (partially invalid error correction data groups) each including at least one valid write data and at least one invalid write data. The device further includes means for refilling write data, the refill means selectively selecting one or more valid write data included in the (e1) partially invalid error correction data group from the plurality of drives. Means for writing to the cache memory, one or a plurality of valid write data that have been read, and (e2) the write means.
(e1) means for executing writing to another partially invalid error correction data group, and (e3) the predetermined number selected from a plurality of valid write data held in the cache memory. Means for newly generating error correction data for an equal number of new sets of valid write data and the set of write data, and thereby generating a new error correction data group, and (e4) the generated Means for rewriting the new error correction data group in parallel to the empty areas in the plurality of drives, and (e5) the means.
(e3) A means for repeating (e4) for another new error correction data group, and (e6) a plurality of partially invalid error correction data groups, in which the valid write data included therein 26. The disk array system according to claim 25, further comprising means for using a plurality of areas, which hold all rewritten data, as free areas for writing another error correction data group according to (d4) and (d5). .