JPH06266506A - Disk storage system - Google Patents

Abstract

PURPOSE:To reduce the burden to a control CPU of an HDD to increase the address conversion processing speed by providing an HDC with an operation function which converts the logical address designated by a host CPU to address information required for access. CONSTITUTION:An HDC 14 is provided with an address conversion and calculation part which converts the logical CHS address designated by a host CPU 15 to LBA based on preliminarily determined parameter information in accordance with prescribed interface standards. A control CPU 11 of the HDD generates actual address information required for access to a disk 1 based on the calculated LBA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a disk drive which is a hard disk device, a disk controller and a host computer, and converts a logical address according to an access request from the host computer into address information necessary for accessing the disk. The present invention relates to a system provided with an address translation function.

[0002]

2. Description of the Related Art Conventionally, SCSI, IDE, PCMCIA, etc. are well known as interface standards between a hard disk device (HDD) and a host computer (host CPU). The host CPU accesses the HDD using such an interface.

The HDD comprises a disk drive that drives a disk as a recording medium and a disk controller (HDC) that forms an interface with the host CPU. The HDC receives commands from the host CPU and address information to be accessed, and also transfers read / write data between the disk drive and the host CPU. The disk drive is provided with a control CPU for performing disk drive control. The control CPU is H
A control operation according to a command from the host CPU is executed through DC, and data read / write is executed with respect to a sector of the disk corresponding to the address information from the host CPU.

According to the well-known interface standard as described above, when the host CPU accesses the HDD, the address of the target sector to be accessed is a logical address composed of a cylinder number, a head number, and a sector number (hereinafter referred to as CHS address). )). The host CPU stores the parameter information such as the number of sectors per track, the number of heads, and the number of cylinders required for access by the OS to grasp the HDD configuration in advance.

By the way, according to the interface standard,
There is an upper limit to the number of sectors, heads, and cylinders in the parameter information. For example, in IDE and PCMCIA, the number of heads is up to 16, the number of cylinders is up to 1024, and the number of sectors is up to 255. However, as the actual configuration of the HDD, the number of cylinders cannot always be set to 1024 in order to reduce the number of disks and increase the capacity. In such a case, the parameter information shown on the host CPU side is logically adjusted so as to be within the limit of the interface standard.

Further, even if the storage capacity is the same, the parameter information is generally different for each HDD model. In this case, on the host CPU side, it is easier to manage HDDs having the same capacity with the same number of cylinders, heads, and sectors. Therefore, even if the specifications of the physical parameters of the HDD are different, the host CPU can access the HDD with a predetermined logical configuration.

In order to realize such an access operation, the following conversion processing of physical parameters and logical parameters is executed. First, the CHS address specified by the host CPU, the number of heads determined in advance,
The logical block address (LBA) is calculated from the parameter information of the number of sectors and the number of cylinders per track.
Then, the calculated LBA is converted into the actual HDD address.

Here, the LBA is logical address information that is handled by adding a series of numbers to the sector numbers on the disk.
For example, when the parameters managed by the host CPU are 10 sectors per track and 2 heads,
The LBA of the sector corresponding to cylinder number 0, head number 0, and sector number 0 is 0. Also, cylinder number 0,
LBA of the sector corresponding to head number 1 and sector number 0
Is 10. Also, in the IDE and PCMCIA interface specifications, the address following the last sector number on one track is the head number in the same cylinder + 1.
It becomes the minimum sector number in the specified location. When the upper limit of the head number is reached, the cylinder number is incremented by 1 and the head with the smallest head number is selected.

[0009]

Conventionally, even when the specifications of the physical parameters of the HDD are different, the access target specified by the host CPU is determined as a logical block from the CHS address according to the interface standard and the predetermined parameter information. By performing the address conversion process for converting the address (LBA), access becomes possible. Such address conversion processing is normally H
It is executed by the control CPU of the DC.

However, the control CPU is, for example, a microprocessor having an 8-bit width data calculation function, and a large amount of data is required for calculation processing such as LBA calculation. Specifically, for example, when the storage capacity per sector of the disk is 512 bytes, an HDD having a storage capacity of 200 megabytes
The maximum value of the LBA of is 390625. When expressed in hexadecimal, this is 05F5E1h, which is a 19-bit data amount.

An object of the present invention is to provide a disk storage system having an address conversion function, by providing the HDC with a calculation function for converting a logical address designated by the host CPU into address information necessary for access, and The purpose is to reduce the load on the control CPU and speed up the address conversion process.

[0012]

According to the present invention, in a disk storage system comprising a host computer, a disk controller and a disk drive, a logical address designated by the host computer is accessed in accordance with a predetermined interface standard. In this system, the disk controller is provided with address conversion processing means for converting the address information necessary for the above.

[0013]

In the present invention, the disk controller has address conversion processing means for converting the logical CHS address designated by the host computer into the address information which is the LBA based on the predetermined parameter information according to the predetermined interface standard. I have it. Therefore, the control CPU of the disk drive can reduce the load associated with the address conversion processing.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram for explaining the configuration of the address translation device (address translation processing means) of the present invention,
2 is a block diagram showing a main part of the disk storage system according to the embodiment, and FIGS. 3 and 4 are flow charts for explaining the operation of the embodiment.

As shown in FIG. 2, this system is roughly divided into a disk drive (HDD), a disk controller (HDC) 14 and a host CPU 15. HD
D has a disk rotating mechanism for rotating the disk 1 as a recording medium, a servo mechanism for positioning the head 2 on a target track on the disk, and a read / write circuit 3 for recording / reproducing data. .

The disk rotating mechanism has a spindle motor 4 and a spindle motor (SPM) driver 5 for rotating the disk 1. The servo mechanism includes a carriage mechanism 6 that holds the head 2, a voice coil motor (VCM) 7 that drives the carriage mechanism 6, and a VCM.
It has a VCM driver 8 and a servo circuit 9 for driving 7. The servo circuit 9 controls the VCM driver 8 based on a command from the control CPU 11 through a logic circuit 10 including a gate array to execute servo processing for positioning the head 2 on a target track on the disk 1. At this time, the servo circuit 9 uses the servo signal (position error signal or the like) S output from the read / write circuit 3 to perform positioning control. The logic circuit 10 includes a PLD (Programmable Logi).
c Device or FPGA (Field Progr)
It is a programmable logic integrated circuit such as an Amable Gate Array).

The read / write circuit 3 is a circuit for generating a write current according to write data for writing to the disk 1 and reproducing read data from a read signal from the head 2. Head 2 is read / write circuit 3
A write magnetic field from the magnetic field generates a recording magnetic field corresponding to the write data. The read / write circuit 3 is the head 2
It has a head amplifier 3a that amplifies a read signal from the device and a pulse peak detector (PPD) 3b for discriminating the read data RD and the sync pulse P from the read signal. The servo signal S is extracted by the PPD 3b.

Logic circuit 10 and control CPU 11
Is an element constituting a disk control device of the HDD.
The logic circuit 10 has a logic circuit configuration based on the logic data set by the control CPU 11. The control CPU 11 is a microprocessor that determines the disk control operation of the HDD according to a program stored in the ROM 12. ROM 12 is a control CPU 1
The logic data of the logic circuit 10 is stored together with the program of 1. The control CPU 11 is a ROM 12
The logic data read from is set in the logic circuit 10.

The HDC 14 includes an HDD and a host CPU 15
And interfaces with the control CPU 11 and the logic circuit 10 to exchange various interface signals and data. The HDC 14 temporarily stores read data in sector units read from the disk 2 and write data to be written in the disk 2 in a RAM 16 which is a sector buffer memory. Host CP
U15 is C of the computer body that accesses the HDD
It is PU. The HDC 14 is shown in FIG.
The address translation device shown in FIG.

The address translation device, as shown in FIG.
Address conversion calculation unit 20, host head register 21,
Host sector register 22, start bit register 23,
An end bit register 24, an output register 25, an input register 26, a target address register 27 and a CHS address register 28 are provided. Address conversion calculator 2
Reference numeral 0 is a main constituent element of the device, which executes an address conversion process for converting a CHS address designated by the host CPU 15 into a logical block address (LBA), or conversely, converting an LBA into a CHS address.

The host head register 21 is a host CP.
This is a parameter register that holds the number of HDD logical heads recognized by U15. Host sector register 22
Is a parameter register that holds the number of logical sectors per track of the HDD recognized by the host CPU 15. The start bit register 23 holds a start bit for instructing the start of the calculation operation of the conversion process. The end bit register 24 holds an end bit for instructing the end of the calculation operation.

The output register 25 is a register for holding the LBA which is the calculation result of the address conversion calculation unit 20. The LBA has a data width of 32 bits, for example, and the most significant bit string BIT31-24 (H), the intermediate upper bit string BIT23-16 (UH), and the intermediate lower bit string BIT1.
5-8 (LH) and the least significant bit string BIT7-0 (L). The input register 26 is used by the address translation calculator 20.
Is a register for storing the LBA when converting to a CHS address.

The target address register 27 is used by the host CP.
This is a register for holding the CHS address set by U15. The CHS address is composed of the lower 8 bits (L), the upper 8 bits (H) of the cylinder number CYL, the head number HE and the sector number SEC. CHS
The address register 28 is a register for storing the CHS address register converted by the address conversion calculation unit 20. Next, the operation of the embodiment will be described with reference to the flowcharts of FIGS.

As shown in step S1 of FIG.
14 reads the CHS address of the address target designated by the host CPU 15. The HDC 14 sets the read CHS address in the target address register 27 (step S2). Further, the HDC 14 sets the number of HDD logical heads recognized by the host CPU 15 in the host head register 21, and sets the number of logical sectors per track in the host sector register 22 (step S3).

In response to an instruction from the host CPU 15, the HDC 14 sets a start bit for instructing the start of the calculation operation in the start bit register 23 (step S).
4). The address conversion calculation unit 20 refers to the parameter information (the number of logical heads and the number of logical sectors of the HDD) held in the parameter registers 21 and 22 in accordance with the setting of the start bit and is set in the target address register 27. A calculation operation for converting the CHS address into the LBA is executed (step S5). The address translation calculator 20 specifically calculates the LBA by the following equation (1). LBA = (HSEC × HHE × CYL) + (HE × HSEC) + (SEC-1) (1)

Here, HSEC is the number of logical sectors set in the host sector register 22. HHE is the number of logical heads set in the host head register 21. CYL is a cylinder number set in the target address register 27. HE is the target address register 27
Is the head number set in. SEC is a sector number set in the target address register 27.

Upon completion of the calculation operation, the address translation calculator 20 sets an end bit for instructing the end of the calculation operation in the end bit register 24 (YES in step S6, S7). The address translation calculator 20 sets the calculation result LBA in the output register 25. HDC1
4 recognizes the end of the calculation operation of the address translation calculator 20 by the end bit set in the end bit register 24 (step S8). The HDC 14 reads the calculation result LBA from the output register 25 and outputs it to the control CPU 11 of the HDD (step S9).

The control CPU 11 generates, from the calculated LBA, actual address information which is an access target of the disk 1. The address information is the head number PHE,
It consists of a cylinder number PCYL and a sector number PSEC.
The control CPU 11 calculates the address information by the following equations (2) to (4). PSEC = LBA mod DSEC (2) However, DSEC is the number of sectors per track of the disk 1, and mod means a remainder. PCYL = int (LBA / (DHE × DSEC × DCYL)) (3) where DHE is the number of heads of the HDD, DCYL is the number of cylinders per surface of the disk 1, and int is rounded down to the nearest whole number. means. PHE = (int (LBA / (DHE × DSEC))) mod DHE ... (4)

Next, the address conversion calculation unit 20 reverses the address conversion processing from the LBA to the host CPU 1
It also performs a calculation to convert to a CHS address recognized by 5. That is, as shown in step S10 of FIG.
14 sets the designated LBA in the input register 26. Further, the HDC 14 sets the number of HDD logical heads recognized by the host CPU 15 in the host head register 21, and sets the number of logical sectors per track in the host sector register 22 (step S11).

In response to an instruction from the host CPU 15, the HDC 14 sets a start bit for instructing the start of the calculation operation in the start bit register 23 (step S1).
2). The address translation calculation unit 20 refers to the parameter information (the number of logical heads and the number of logical sectors of the HDD) held in the parameter registers 21 and 22 according to the setting of the start bit, and sets the LB set in the input register 26.
A calculation operation for converting A into a CHS address is executed (step S13).

When the address translation calculator 20 completes the calculation operation, it sets an end bit for instructing the end of the calculation operation in the end bit register 24 (step S14).
YES, S15). The address conversion calculation unit 20 stores the CHS address, which is the calculation result, in the CHS address register 2
Set to 8. HDC 14 uses end bit register 2
The end bit set to 4 recognizes the end of the calculation operation of the address translation calculator 20 (step S1).
6). The HDC 14 reads the CHS address, which is the calculation result, from the CHS address register 28, and the host CP
Transfer to U15 (step S17).

In this way, the HDC 14 is connected to the host C.
An address conversion process for converting a logical address (CHS address) to be accessed specified by the PU 15 into a logical block address (LBA) according to the interface standard is executed. The control CPU 11 of the HDD is
When the calculation operation of the address conversion calculation unit 20 of the HDC 14 is completed, the actual address information necessary for accessing the disk 1 is generated based on the calculated LBA. As a result, the sector of the logical address designated by the host CPU 15 is accessed.

According to the present invention, an address conversion process for converting a CHS address into an LBA, which requires a large amount of data, is performed by H
It is executed by the address conversion calculation unit 20 provided in the DC 14. Therefore, the control CPU 11 of the HDD is only required to generate the actual address information based on the calculated LBA, which significantly reduces the load.

[0035]

As described above in detail, according to the present invention, the HDC side executes the address conversion process for converting the logical address designated by the host CPU into the address information in accordance with the interface standard. The burden on the control CPU can be reduced. Therefore, the processing time required for the address conversion processing can be shortened, and as a result, the access to the HDD can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a configuration of an address translation device according to the present invention.

FIG. 2 is a block diagram showing a main part of the disk storage system according to the embodiment.

FIG. 3 is a flowchart for explaining the operation of the embodiment.

FIG. 4 is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

1 ... Disk, 11 ... Control CPU, 14 ... HDC, 1
5 ... Host CPU, 20 ... Address translation calculator.

Claims (2)

[Claims] 1. A disk storage system comprising a host computer, a disk controller and a disk drive, wherein a logical address, which is provided in the disk controller and designated by the host computer according to a predetermined interface standard, is stored in the disk of the disk drive. A disk storage system comprising address conversion processing means for converting address information necessary for executing access. 2. A disk storage system comprising a host computer, a disk controller and a disk drive, wherein the disk drive is provided in the disk controller and a logical address specified by the host computer is predetermined according to a predetermined interface standard. Address conversion processing means for converting into a logical block address on the basis of the parameter information of the above, and the logical block address calculated by the address conversion processing means, which is provided in the disk drive, executes the disk access of the disk drive. A disk storage system, comprising: an address generation means for converting into actual address information necessary for that purpose.