JPH06266462A - Power economizing device of electronic apparatus - Google Patents

Abstract

PURPOSE:To reduce the power consumption caused by an MPU by controlling a frequency of a clock supplied to the MPU, in a data processor such as a computer, etc. CONSTITUTION:A frequency of an MPU clock signal 22 supplied to an MPU2 by a clock control circuit 14 is lowered in the course of holding cycle of the MPU2. Or, the MPU clock signal 22 supplied to the MPU2 is stopped by a clock stop control circuit. When the MPU2 accesses an input/output part and a memory whose access time is slow, a wait cycle is not executed by the MPU2, but a signal for stopping the MPU clock signal 22 in a wait period, is generated by a bus wait control circuit, and by using this signal, the MPU clock signal 22 supplied to the MPU2 is stopped temporarily by the clock stop control circuit. In such a manner, electric power consumed by the MPU is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-saving device for various electronic devices, and more particularly to a relatively small battery-operable computer device generally called a personal computer. .

[0002]

2. Description of the Related Art In recent years, along with the miniaturization and higher functionality of electronic devices typified by computers, laptop-type and notebook-type products that can be carried around have appeared. Usually, a battery is used as a power source for these mobile phones.

In order to carry and use these for a long time, it is necessary to increase the capacity of the battery which is the power source or reduce the consumed power.

[0004]

The electronic device of this type is
Due to the usage form of carrying it, increasing the capacity of the battery results in an increase in the battery weight, and the external dimensions also increase, so the product weight and the product size increase, May interfere with mobile use.

Therefore, in order to prolong the portable use time as much as possible, it is necessary to reduce the power consumption.

An object of the present invention is to obtain a power saving device for an electronic device which can reduce the power consumption of the electronic device called a laptop computer, a notebook computer, etc. and can be used for a long time while being carried.

[0007]

An electronic device of the type described above comprises a central processing unit, which operates by receiving a clock signal. However, it has a unique operating mode. One of them is a hold cycle. It operates by inputting a clock signal, but does not perform any processing, and only consumes power.

The present invention has been made paying attention to this point, and is characterized in that in an electronic device having a central processing unit that operates in synchronization with a clock signal, the hold cycle of the central processing unit is It has a clock control circuit for lowering the clock frequency of the clock signal supplied to the central processing unit. Here, the clock control circuit may stop the clock signal supplied to the central processing unit.

A feature of the present invention is that an electronic device is provided with a central processing unit that operates in synchronization with a clock signal, an input / output unit that is accessed from the central processing unit and has a different access time, and a memory. In the second aspect, a clock control circuit for lowering the clock frequency of the clock signal supplied to the central processing unit is provided during the wait period when accessing the input / output unit and the memory having a long access time. Here, the clock control circuit may stop the clock signal supplied to the central processing unit.

Further, a feature of the present invention is that the direct memory access unit is an electronic device including a central processing unit that operates in synchronization with a clock signal, and a direct memory access unit. During the data transfer period, the clock control circuit for lowering the clock frequency of the clock signal supplied to the central processing unit is provided. Here, the clock control circuit may stop the clock signal supplied to the central processing unit.

[0011]

The central processing unit consumes power when the clock signal is input. The degree of power consumption increases as the frequency of the clock signal increases.

With the above arrangement, when the central processing unit enters the hold cycle, the clock control circuit lowers the frequency of the clock signal supplied to the central processing unit, so that the power consumption can be reduced accordingly. .

Further, the clock control circuit lowers the frequency of the clock signal supplied to the central processing unit during the wait period when the central processing unit accesses the input / output unit and the memory which have a long access time. , The power consumption can be reduced.

Further, in the clock control circuit, during the data transfer period by the direct memory access section,
Since the clock frequency of the clock signal supplied to the central processing unit is reduced, the power consumption can be reduced accordingly.

[0015]

Embodiments of the present invention shown in the drawings will be described below.

FIG. 7 is a diagram for explaining a general hold cycle of the central processing unit, and FIG. 8 shows its time chart. In this figure, a clock generator 1 is directly connected to a central processing unit (hereinafter referred to as MPU) 2, a hold request (HRQ) signal 3 is input to the MPU 2, and the MPU 2 outputs a hold response (HOLDA) signal 4. Even if the MPU 2 is outputted and is in the hold cycle, the frequency of the clock (CLK) signal 5 supplied to the MPU 2 does not change or stops as shown in FIG. 8 and is always constant.

FIG. 9 is a diagram for explaining a wait period when accessing the input / output unit and the memory which have a long access time, and FIG. 10 shows the time chart.
In this case, the MPU 2 operates in synchronization with the clock signal 5 from the clock generator 1, and the I / O unit (I / I) is operated via the address bus 6, the data bus 7, and the bus control signal 8.
O) The data is processed by reading and writing the data between the memory 9 and the memory 10. With respect to the input / output unit (I / O) 9 and the memory 10 whose access time is sufficiently fast, reading and writing are performed at the timing shown in "cycle without wait" in FIG. 10, and two cycles of T1 and T2 are performed. The operation ends with. Whether or not the cycle ends is controlled by a bus wait control (WAIT) signal 12 output from the bus wait control circuit 11 to the MPU 2, and the bus wait control signal 12 is LOW at the end of T2.
If it is a level, the access cycle ends.

Input / output unit (I / O) with slow access time
In the case of 9 and memory 10, the access operation cannot be completed in the two cycles of T1 and T2, and the slow input / output unit (I / O)
The cycle of T2 is repeated until the operations of the memory 9 and the memory 10 are completed to extend the access time, and the MPU 2 waits until the read / write of the slow input / output unit (I / O) 9 and the memory 10 is completed. How many clocks are extended is set in the bus wait control circuit 11 for each type of the input / output unit (I / O) 9 and the memory 10. In this way, the input / output unit (I / O) 9 and the memory 10 having different access times
Access is controlled, but as shown in FIG. 10, the clock signal 5 is always supplied to the MPU 2 even in a wait cycle.

As described above, in the conventional device, since the clock generator 1 is directly connected to the MPU 2, the normal clock signal 5 is supplied to the MPU 2 even when the MPU 2 is in the hold cycle, and the power consumption of the MPU 2 does not change. , Power is wasted.

Further, even when the slow input / output unit (I / O) 9 and the memory 10 are being accessed, since the normal clock signal 5 is supplied to the MPU 2, the power consumption of the MPU 2 does not change and the power consumption does not change. Is wasted.

According to the embodiment, M during the hold cycle
It is possible to reduce the power consumption of the PU2 and also reduce the power consumption of the MPU2 while accessing the input / output unit (I / O) 9 and the memory 10 with a slow access time.

The MPU 2, when supplied with the clock signal, consumes power. The degree of power consumption increases as the frequency of the clock signal increases.

Further, as described above, during the hold cycle, the MPU 2 is not performing any processing and is merely consuming power. Therefore, a clock control circuit is provided between the clock generator and the MPU2, and a control circuit that lowers the frequency of the clock signal or stops the clock signal during the hold cycle is provided between the clock generator 1 and the MPU2. The frequency of the clock signal is lowered or stopped during the hold cycle.

Further, the MPU 2 has a slow input / output unit (I / O).
Also, during the period of accessing the memory and executing the wait cycle, the MPU 2 does not repeat the wait cycle, but stops the clock signal supplied to the MPU by the clock stop control circuit.

A hold response signal notifying that the MPU 2 has entered the hold cycle causes the clock control circuit to temporarily lower the frequency of the clock signal supplied to the MPU, or the clock stop control circuit to change the clock signal supplied to the MPU. Stop temporarily.

Further, the MPU 2 has a slow input / output unit (I / O).
Also, during the period in which the memory is accessed and the wait cycle is executed, the bus wait control circuit generates a clock stop (CWAIT) signal for controlling the stop of the clock signal, and this signal supplies the clock signal to the MPU. Stop temporarily.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows a DMA according to an embodiment of the present invention.
FIG. 7 is a diagram showing (Direct Memory Access) transfer. Figure 2
Is a timing chart showing the timing.
As an example of the MPU hold cycle, DM is used here.
Take A transfer. In this figure, a DMA request (DRQ) signal 19 for requesting DMA transfer is input from the peripheral device 18 to the DMA controller 17.
DMA controller 17 sends to MPU 2 system bus 20
The hold request signal 3 for requesting the exclusive right is output.

When the MPU 2 outputs the hold response signal 4 indicating that the hold cycle has been entered, the DMA acceptance signal D is sent to the peripheral device 18 which is issuing the DMA transfer request.
The MA response (DACK) signal 21 is sent to start the DMA transfer.

When the hold request signal 3 and the hold response signal 4 are output, the MPU clock signal 22 is controlled by the clock control circuit 14 which lowers the frequency of the MPU clock (MPUCLK) signal 22 supplied to the MPU 2.

When the DMA transfer is completed, the hold request signal 3 is set to LOW to return the exclusive right of the system bus 20 to the MPU 2. When the hold request signal 3 becomes LOW, the clock control circuit 14 becomes MPU.
The frequency of the MPU clock signal 22 supplied to 2 is restored. The signal timing at this time is as shown in FIG.

Another embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a diagram showing a DMA transfer according to another embodiment of the present invention. FIG. 4 is a timing chart showing the signal timing. As an example of the MPU hold cycle, DMA transfer is taken up here. In this figure, a DMA request signal 19 for requesting a DMA transfer is input from the peripheral device 18 to the DMA controller 17, and the DMA controller 17 makes the MPU 2
A hold request signal 3 for requesting the exclusive right of the system bus 20 is output.

When the MPU 2 outputs the hold response signal 4 indicating that the hold cycle has been entered, the DMA acceptance signal D, which is a DMA acceptance signal, is sent to the peripheral device 18 which is issuing the DMA transfer request.
The MA response signal 21 is sent to start the DMA transfer.

Here, when the hold request signal 3 and the hold response signal 4 are output, the MPU clock signal 22 is temporarily stopped by the clock stop control circuit 15 for stopping the MPU clock signal 22 supplied to the MPU 2.
To stop.

When the DMA transfer is completed, the hold request signal 3 is set to LOW in order to return the exclusive right of the system bus 20 to the MPU 2. When the hold request signal 3 becomes LOW, the clock stop control circuit 15 becomes M
The MPU clock signal supplied to PU2 is restored. The signal timing at this time is as shown in FIG.

FIG. 5 shows still another embodiment of the present invention, and FIG. 6 shows its time chart.

The MPU clock signal 22 supplied to the MPU 2 is supplied to the MPU 2 via the clock stop control circuit 15. The MPU clock signal 22 can be temporarily stopped by inputting the clock stop signal 16 generated by the bus wait control circuit 11 to the clock stop control circuit 15. Whether or not the access cycle ends is determined by whether or not the bus wait control signal 12 input to the MPU 2 at the end of T2 is at the LOW level.

Therefore, the bus wait control signal 12 input to the MPU 2 is fixed at the LOW level, and the MPU clock signal 22 supplied to the MPU 2 is stopped during the period of T2, thereby delaying the final period of T2. This T2
The number of clocks to delay the final period of is set in the bus wait control circuit 11 for each type of the I / O 9 and the memory 10.

With the above arrangement, the power consumption of the MPU is almost proportional to the frequency of the clock signal supplied,
The power consumption of the MPU can be reduced by lowering the frequency of the clock signal or stopping the clock signal. Therefore, during the MPU hold cycle, M
By lowering or stopping the frequency of the clock supplied to the PU, the MPU is held during the hold cycle.
The electric power consumed in is reduced compared to the normal time.

In addition, the I / O having a long access time and the MPU during the useless cycle while accessing the memory.
By stopping the clock supplied to the MPU, the power consumed by the MPU can be reduced.

Another embodiment of the present invention will be described below. Generally, a computer device uses a DMA (Direct Memory).
It has a data transfer method called Access. This is CP
Data is transferred between a memory and a peripheral device such as from a hard disk to a main memory or from a main memory to a floppy disk without going through a U (Central Processing Unit).

Regarding this DMA processing, a device called a DMA controller performs the actual processing, the CPU does not perform any processing, and only power is consumed during the DMA.

The CPU consumes power when the clock is input. The degree of power consumption increases as the clock frequency increases.

Therefore, in the present embodiment, two oscillators are provided, or a frequency divider is provided to create clocks of two different frequencies, high and low. Then, normally, a high frequency clock is input to the CPU to operate the CPU, and D
A low frequency clock is input during MA transfer.

With such a configuration, the C
The frequency of the clock input to the PU is reduced, and the CPU
The power consumed by can be reduced. Therefore, the power consumed by the CPU during the DMA transfer is reduced as compared with the normal use.

The above will be described below with reference to FIGS. 11, 12, 13, and 14. FIG. 11 is a diagram for explaining a general DMA transfer, and FIGS. 12 and 13 are circuit structure diagrams showing an embodiment. FIG. 14 is a timing chart showing the signal timing of this embodiment.

First, a normal DMA transfer will be described with reference to FIG. In normal DMA transfer, the following (1) to
DMA transfer is performed by the procedure of (8).

(1) A DMA request (DRQ signal 19) is input to the channel in the DMA controller 17 from the peripheral device 18 or the like.

(2) DMA controller 17 is CPU2
Request the exclusive right of the system bus (HRQ signal 3).

(3) Response signal from the CPU 2 (HOLD
When the A signal 4) is received, the DMA acceptance signal (DACK signal 21) is sent to the channel issuing the DMA transfer request,
Start DMA transfer.

(4) The lower byte of the memory address which is the target of the DMA transfer is transferred from the A0 to A7 terminals to the system
Output to the lower part of the address line 20 and output the upper byte to the system data bus from the D0 to D7 terminals,
Causes the address latch to latch the data once.

(5) The output of the address latch is connected to the upper portion of the system address line 20, and this output and the address data from A0 to A7 described above are 1
The 6-bit DMA transfer address is sent out to the system address.

(6) During the DMA operation, a read signal (MEMR, MEMR, ...) Is sent to the memory and the peripheral device 18 in order to transmit and receive data between the memory of the above-mentioned address and the peripheral device 18.
I / OR) and write control signals (MEMW, I / OW) are output to execute DMA transfer.

(7) When the designated number of bytes of data are transferred, a TC signal is output to notify the CPU 2 that the DMA transfer is completed. If the transfer is not completed here, the process is repeated from (4).

(8) Return the exclusive right of the system bus to the CPU 2 (HRQ signal 3 negate).

Here, as shown in FIG. 12, when the HRQ signal of (2) is output and the HOLDA signal of (3) is output from the CPU, the clock input to the CPU 2 is divided and (8 The circuit 14 (frequency divider) for returning the clock frequency to the original level when the HRQ signal of 1) is negated is inserted between the clock oscillator 1 (including the clock driver) and the CPU 2.

Alternatively, as shown in FIG. 13, oscillators 1a, 1b
Two high-frequency clocks and low-frequency clocks are prepared, and a high-frequency clock is input to the CPU2 during normal use.
When the HRQ signal of (3) is output and the HOLDA of (3) is output, it is synchronized with the high frequency clock and switched to the low frequency clock, and when the HRQ signal of (8) is negated, By lowering the frequency of the clock input to the CPU during the DMA transfer, for example, by inserting the circuit 14 that synchronizes with the low-frequency clock and switches to the high-frequency clock between the oscillators 1a and 1b and the CPU 2. .

It should be noted here that the maximum frequency and the minimum frequency of the clock that can be input to the CPU 2 are determined by the specifications, so that the clock frequency during normal use is below the maximum frequency, and It is necessary to determine the frequency division ratio of the clock or the frequency of the oscillator so that the clock frequency lowered during the DMA transfer becomes equal to or higher than the lowest frequency.

The signal timing is as shown in FIG. 14 regardless of the method shown in FIG. 12 or 13. Various circuits can be considered as the frequency dividing circuit in FIG. 12 and the oscillator switching circuit in FIG.

Incidentally, in FIG. 11, FIG. 12 and FIG.
The signal DRQ (DMA REQUEST) is a signal for the peripheral device to request the DMA transfer from the DMA controller. DREQ is held until DACK becomes active. Signal HRQ (HOLD REQUEST)
Is a signal for requesting the CPU to take exclusive ownership of the system bus. Signal HOLDA (HOLD ACKNOWLED
GE is a hold request (H) from the DMA controller.
This is a signal indicating that the CPU has confirmed the (RQ signal).
When this signal is received by the DMA controller, control of the system bus transfers to the DMA controller. Signal DAC
K (DMA ACKNOWLEDGE) is a DMA acceptance signal for a channel in the DMA controller. When this signal is input to the channel, DMA transfer is started. The signal MEMR (MEMORYREAD) is DMA
Used to read data from the addressed memory during a read cycle. Signal I / OR (I / OR
EAD) is a control signal for reading data from the peripheral device during DMA transfer. Signal MEMW (MEMORY W
RITE) is used to write data to the addressed memory during the DMA write cycle. Signal I
/ OW (I / O WRITE) is a control signal for writing data to the peripheral device during DMA transfer. Signal TC (T
ERMINAL COUNT)
This signal indicates that the DMA transfer currently being executed is the last byte of the predetermined transfer bytes. Signal CCLK (CPU
CLOCK) is a clock signal input to the CPU. The signal DCLK (DMAC CCLOCK) is a clock signal input to the DMA controller. Signal AD
STB (ADDRESS STOROBE) is DMA
It is a strobe signal for sending the upper byte of the memory address to be transferred from the data bus (D0 to D7) to the address latch.

With the above configuration, the frequency of the clock input to the CPU during the DMA transfer is lowered.
The power consumed by the CPU during the DMA transfer is reduced as compared with the normal time.

[0061]

As is apparent from the above description, according to the present invention, the power consumption of electronic devices equipped with a battery called a laptop type computer, a notebook type computer, etc. is reduced, and the operating time during carrying is extended. It is possible to obtain a power saving device for an electronic device that can be used.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the timing of each part of FIG.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a time chart showing the timing of each part of FIG.

FIG. 5 is a circuit diagram showing still another embodiment of the present invention.

FIG. 6 is a time chart showing the timing of each part of FIG.

FIG. 7 is a circuit diagram for explaining a hold mode of a central processing unit.

8 is a time chart showing the timing of each part of FIG.

FIG. 9 is a circuit diagram for explaining a bus weight.

10 is a time chart showing the timing of each part of FIG.

FIG. 11 is a circuit diagram for explaining DMA transfer.

FIG. 12 is a circuit diagram showing still another embodiment of the present invention.

FIG. 13 is a circuit diagram showing still another embodiment of the present invention.

FIG. 14 is a time chart showing the timing of each part of FIGS. 12 and 13;

[Explanation of symbols]

1 ... Clock generator, 2 ... MPU, 3 ... Hold request signal (HRQ), 4 ... Hold response signal (HOLD)
A), 5 ... Clock signal (CLK), 6 ... Address bus, 7 ... Data bus, 8 ... Bus control signal, 9 ...
I / O, 10 ... Memory, 11 ... Bus wait control circuit,
12 ... Bus wait control signal (WAIT), 13 ... MP
U internal clock signal, 14 ... Clock control circuit, 15 ...
Clock stop control circuit, 16 ... Clock stop signal (CW
AIT), 17 ... DMA controller, 18 ... Peripheral device, 19 ... DMA request signal (DRQ), 20 ... System bus (data, address), 21 ... DMA response signal, 22 ... MPU clock signal (MPUCLK)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Tsunemoto 810 Shimoimaizumi, Ebina-shi, Kanagawa Hitachi Systems Office Systems Division

Claims (5)

[Claims] 1. An electronic device including a central processing unit that operates in synchronization with a clock signal, wherein clock control is performed to reduce a clock frequency of a clock signal supplied to the central processing unit during a hold cycle of the central processing unit. A power-saving device for an electronic device, comprising a circuit. 2. An electronic device including a central processing unit that operates in synchronization with a clock signal, comprising a clock control circuit that stops a clock signal supplied to the central processing unit during a hold cycle of the central processing unit. A power saving device for electronic equipment, which is characterized in that 3. An electronic device including a central processing unit which operates in synchronization with a clock signal, an input / output unit accessed from the central processing unit and having different access times, and an input / output unit having a long access time in the electronic device. A power saving apparatus for an electronic device, comprising: a clock control circuit that stops a clock signal supplied to the central processing unit during a wait period when accessing the unit and the memory. 4. An electronic device comprising a central processing unit that operates in synchronization with a clock signal and a direct memory access unit, wherein the central processing unit is provided during a data transfer period by the direct memory access unit. A power saving device for electronic equipment, comprising a clock control circuit for reducing the clock frequency of a clock signal supplied to the electronic device. 5. An electronic device comprising a central processing unit that operates in synchronization with a clock signal and a direct memory access unit, wherein the central processing unit is provided during a data transfer period by the direct memory access unit. A power saving device for an electronic device, comprising a clock control circuit for stopping a clock signal supplied to the electronic device.