JPH06261064A - Atm cell composing method - Google Patents

Abstract

PURPOSE:To prevent deterioration in the line utilization efficiency by scheduling a cell processing start timing so as to distribute timewise production of cells thereby eliminating uneven cell production. CONSTITUTION:When a line number of input data is designated, a write position in an area corresponding to a line is designated based on a sample count of a control memory 5. In the case of setup, data are stored in a cell composing buffer 6 by using a line number and a sample count as an address, the count is incremented by one and when the count reaches 0, the data are read. When no call is set, a silence pattern generating circuit 8 stores a silence pattern in the cell composition buffer 6. Then a control memory 5 is used to make scheduling by controlling cell production start timing such that a succeeding cell is produced as soon as read of a cell is finished thereby distributing timewise cell production, and then the deterioration in the line utilization efficiency is prevented by eliminating a transmission wait de lay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention, when accommodating an STM (synchronous transfer mode) line in an ATM (asynchronous transfer mode) network, receives an STM data string sent by the STM line and assembles it into an ATM cell. Although it is necessary to send the data to the ATM network, the present invention relates to a method for assembling an ATM cell from an STM data string in such a case.

[0002]

2. Description of the Related Art When accommodating an STM line in an ATM network,
An ATM adaptation layer (AAL) process, which is a function of assembling and disassembling an STM data string into ATM cells, is required. Here, the AAL will be briefly described as follows. That is, it is well known that ATM is a transfer method that does not depend on communication media, but on the other hand, the communication characteristics required for various communication services such as voice, video, and data are different, so a match is made between them. It is necessary to realize this, and the realization of this is the basic function of AAL. 362 and I.D. 363.

Now, as a place to which this AAL processing is applied, a place such as a relay system is considered and the time-division multiplexed ST is used.
It is conceivable to take out data for each channel from the M line, assemble an ATM cell corresponding to the channel, and send it out. Assuming that the effective data length stored in one ATM cell (hereinafter, simply referred to as a cell) is L × p bits, one cell is completed in L frame time.

That is, if one frame includes a plurality of time slots, each time slot constitutes one channel, and each time slot includes p-bit data, it corresponds to a certain channel. Even if one cell is completed (in other words, the data of the channel of L × p bits forming one cell arrives), L frames need to arrive.

Since cells are assembled independently for each channel, if the STM line speed multiplexed and input to the AAL multiplexing processing unit and the ATM line speed output from the same are equal, in a certain frame. , If the number of channels for which a call is set is more biased than that of other frames, and if the generation of cells is biased, the completed cells cannot be sent at one time.
This causes a delay in waiting for cells to be sent to the network, which causes deterioration of communication quality.

Conventionally, there has been considered a method of reducing the probability of uneven cell generation, such as increasing the transmission line speed or suppressing the used line rate (channel use rate) against such delay. However, these methods have a drawback that the transmission cost per line increases because the line use efficiency is lowered.

[0007]

Therefore, the present invention solves this problem and reduces the line utilization efficiency (1
It is an object of the present invention to provide an ATM cell assembling method capable of preventing uneven cell generation (without increasing the transmission cost per line).

[0008]

To achieve the above object, according to the present invention, the cell generation start timing is scheduled to prevent cell generation so that the cell generation timing is not biased in any particular frame. By distributing the cells temporally, the delay of cell transmission to the ATM network is eliminated.

[0009]

At present, the line speed of a telephone representing the CBR service is 64 kb / s, and 8 bits are multiplexed in units of data. Therefore, it is assumed that the speed v = 64000 and the number of bits constituting the unit data p = 8. As the adaptive location of the AAL multiplex processing unit, SD with 2016 lines multiplexed
Assuming H155.52 Mb / s, line (channel)
Let the number N = 2016.

SDH is the SD standardized as a new world standard for network node interfaces.
H (New Synchronous Hierarchy), which means a new relay network. ABR of CBR in CCITT recommendation
Since the actual user data length in the 48 bytes of the ATM cell payload is 47 bytes, L = 47 is set and the following description will be given using these numerical values. Fixed speed 6
Consider a case where a 4 kb / s line receives an STM data string in which 2016 lines are multiplexed and an ATM cell is assembled for each line (channel).

Now, in a certain 125 μs frame (in the frame, there are 2016 time slots (hereinafter, T
S) is included), and each TS input in order
In order to assemble the data of (time slot) into a cell, the T
S1 (first TS in 2016 time slots)
It is assumed that the line has just stored the 47th byte data in the buffer.

At that time, the cell of the line of TS1 is completed, and then the data string is read out from the buffer as a cell and transmitted. If the input speed and the output speed to the buffer are equal, sending the 47-byte data (that is, the cell) takes the same time as inputting 47 TSs.

FIG. 6 is a conceptual diagram showing the delay of cells corresponding to each line when the cells of each line are completed continuously in the same frame and sent to the ATM network. That is, in the figure, TS1 to T are set in one frame (125 μs period).
S2016 is included, and for line (channel) 1
Following the data of TS1 of the first frame (8 bits, that is, 1 byte), the data of TS1 of each frame that successively arrives is extracted (the number of frames L, that is, up to 47),
It will be appreciated that the cell corresponding to the line (channel) 1 is completed by being stored in the cell assembly buffer. The same applies to other lines (channels) such as the line 2 and the line 3.

At this time, when cells corresponding to the respective lines such as the line 1, the line 2, and the line 3 are successively prepared, when reading and transmitting the cells, the cells corresponding to the line 2 are transmitted after the first cell corresponding to the line 1 is transmitted. Since the cell is transmitted, the transmission of the cell corresponding to the line 2 must wait until after the transmission of the cell corresponding to the line 1.

That is, assuming that the cell corresponding to the line 1 is transmitted immediately after cell completion when the data of TS1 of the last frame arrives, TS2 of the last frame is transmitted.
The cell corresponding to the line 2 is completed at the time when the data of 1 arrives, but even if the cell is to be transmitted immediately, as shown in FIG. 6, it is necessary to wait until the cell corresponding to the line 1 is completely transmitted. A delay of 2.24 μs occurs.

Similarly, if the cell corresponding to the line 3 is completed at the time when the data of TS3 of the last frame arrives, the transmission waiting delay further increases as shown in FIG. In the worst case, if all cells of the 2016 line are completed in the same 125 μs, it takes time until 47 frames (about 6 ms) after the completion of transmission of the 2016 cells. This worst 6ms
The delay is a non-negligible value.

One of the causes of such a delay is, as can be seen from FIG. 6, when a cell of a certain TS (cell corresponding to a certain line) is being transmitted, a cell of another TS (other This is because the line-compatible cell) is completed. To prevent this, for example, the lines TS2 to TS47, which are input while the cells of the line TS1 are being transmitted, may be controlled so that the cells are not completed within the frame time.

That is, when the cell of TS1 is completed,
Then, if the line of TS48 after 47 TS completes the cell next, it can be transmitted immediately without delay. The basic idea of the present invention is as described above.
A line that can complete a cell within the frame time of μs cycle,
The number of lines that can be completed in one frame is 125 μs, which is controlled so that every TS is exactly 47.
The number of cells that can be transmitted is 42 or 43.

For more detailed explanation, for example, a modulo 47 counter, which counts up every frame of a period of 125 μs, is used, and 47 numbers from 0 to 46 are assigned to each of the sequentially arriving frames. . That is, assuming that the frame number is 0, the next incoming frame has the number 1, and 47 frames after that, the frame has the number 1 again.

The cell of each line (channel) is always 47
Since the cell is completed at the frame period, if the cell of a certain line is completed at the frame number i, the line is always completed at the frame number i. Therefore, by deciding which frame number should be completed for which TS line cell, the cell generation timing can be controlled.

Table 1 below shows an example in which the TS number (line number) corresponding to the cell in which a cell in each frame can be completed is allocated according to the present invention.

[0022]

[Table 1]

In Table 1, when the frame number is 0, the data of the TS1 input first is that the cell is completed in this frame, so that the line buffer (cell assembly buffer for each line shown in FIG. 6) of the line buffer is completed. TS2 is controlled so that it is stored as the 47th byte data, and is input subsequently.
Since the cell is completed in the next frame (frame number 1), the data is stored as the 46th data in the line buffer (cell assembly buffer) at this point.

It is also assumed that the line of TS5 is called and the call connection is completed when the frame number is 2, for example. If TS5 cellization is started from this point, the cell is completed at frame number 1, which does not meet the requirements of Table 1. In order to complete the cell of TS5 in frame 4 according to the rules of Table 1, cell assembly may be started from frame 5.

The simplest implementation method is now Frame 2
In this method, even if the call connection is completed and the call starts, the data input in frames 2, 3, and 4 is discarded, and the cell input is started from the data input in frame 5. Therefore, there is a method for completing a cell by adding invalid data to valid data input from the time the call is set up to the frame when the first cell is completed.

That is, using the above example, the valid data input in the frame 2 at which the call is started is stored as the 45th data in the cell assembly buffer of the line, and the previous 44 bytes contain a silent pattern or the like. Store invalid data. By controlling in this manner, the 47th data can be stored in the frame 5, and the gap between the completion of the call connection and the cellization timing is filled with a silent pattern or the like to perform cellization without data loss. be able to.

In Table 1, the sample counter value represents the value of the sample counter at the time of frame 0 of the line in which cell generation is defined in each frame.

By performing the control as described above,
There are 47 sets of corresponding lines that generate cells in each frame. No matter how these sets are arranged with respect to frame numbers, for example, a set (1, 4
8, 95, ..., 1928, 1975) and the set of frame 2 starting from line 2 are interchanged, and even if control is performed so that a cell is completed from line 2 in frame 0, the delay can be set to 0. I can.

[0029]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram conceptually showing an embodiment of the present invention. In the figure, 1 is an STM user data input line, 2 is an ATM cell output line, 3 is a frame information input line,
4 is a TS counter (that is, T when the frame information is input)
S number output circuit) 5, control memory (a circuit that outputs the storage address in the cell assembly buffer when the TS number is input as an address), 6 is a cell assembly buffer, 7 is a cell read control unit, and 8 is a silence A pattern generation circuit 9 is a gate circuit for switching input data according to information from the control memory 5.

FIG. 2 is an explanatory view showing a concrete example of the control memory 5 and the cell assembly buffer 6 in FIG. In the control memory 5, a sample counter value and a call connection identifier (CI) bit are stored in an area having a line number as an address. The line number and the sample counter value represent the position (address) to be written in the cell assembly buffer 6.

That is, when the line number is designated, the area corresponding to each line in the cell assembly buffer 6 is determined, and the sample counter value is a value designating at which position in the area corresponding to the line the data is written. Is a counter value generated by a counter (hereinafter referred to as a sample counter). The call connection identifier (CI) bit is 1 when a call is set up on the line of the line number,
Otherwise, 0 is set by means not shown.

Now, referring to the ATM cell assembly processing algorithm shown in FIG. 3, the AT in the case of the present invention will be described.
The procedure for assembling the M cell will be described. As shown in the figure, when data is input to the AAL processing unit (step 1), first the line number corresponding to the TS (time slot) number of the data is obtained (step 2), and the line of the control memory 5 is obtained. Access the corresponding area (step 3).

When the call of the line is set (when the CI bit is 1) (YES in step 4), the data is stored in the cell assembly buffer 6 using the line number and the sample counter value as the address ( Step 5). afterwards,
The sample counter is incremented by 1 (step 6), and when the sample counter value becomes 0 (YES in step 7), the cell of the line is completed and is read (step 8).

On the other hand, when the call is not set up (NO in step 4), a silent pattern is stored in the cell assembly buffer 6 using the line number and the sample counter value as an address (step 9), and the sample counter is set to 1 Count up.

Next, returning to FIGS. 1 and 2, the cell assembling processing procedure when a call is set to the lines 1 and 2 after initializing the sample counter will be described again.

In the case of frame 0, (a) In order for each line to generate a cell in a specified frame, the sample counter just needs to indicate 46 when the frame comes. Therefore, in the case of frame 0, the value at the bottom of Table 1 shows the value that the sample counter of the line specified in each frame should take. As the initial setting of the sample counter in the control memory 5, the values shown in Table 1 in frame 0 are set in the sample counter of the address output circuit of each line.

(B) When line 1 and line 2 are set up,
The CI bit of the control memory 5 is set and becomes 1. (C) When the frame 0 is input, the sample counter of the line 1 in the control memory 5 is 46, the line 2 is 45, and the line 3 is 44.

(D) The data of the line 1 is written in the 47th byte of the area of the line 1 of the cell assembly buffer 6, and the sample counter counts up by 1 and becomes 0.
Becomes At the same time, a cell completion signal is sent to the cell read control unit 7 (FIG. 1), a cell in which 1 to 46 bytes out of 47 bytes are silent patterns and only the last 1 byte is valid data is read out and sent to the ATM network. To be done.

(E) The data on the line 2 is written to the 46th byte in the area of the line 2 of the cell assembly buffer 6, and the sample counter is incremented by 1 to 47. (F) Since the CI bit of the line 3 is not set, invalid data (silent pattern) is written to the cell assembly buffer 6 from the silent pattern output circuit 8 through the gate circuit 9 and the sample counter is incremented by 45. And

In the case of frame 1, (g) line 1 is written at the head position of the line 1 area of cell assembly buffer 6 and the cell counter is set to 1.

(H) The line 2 is written at the 47th byte of the line 2 area of the cell assembly buffer 6 and the sample counter is incremented by 1, and at the same time the cell is completed and a signal is sent to the cell read control unit 7. Sent and the cells of line 2 are read. (I) Since the CI bit is not set on the line 3, the silent pattern is written and the sample counter is incremented by 1 as in the case of frame 0.

Next, an embodiment of an ATM cell assembling method in the case where the multiplexed STM lines are converted into cells for each line and cell multiplex output is performed will be described. As described above, when accommodating the STM line in the ATM network, the ATM adaptation layer (AAL) process which is a function of assembling and disassembling into ATM cells is required.

As a place where this AAL processing is applied, a place where ATM is converted for each channel from a multiplexed STM line such as a relay system can be considered. Since the effective data length stored in one cell is Lp bits as described above, one line is completed in L frame time for the line of speed vb / s, and (n × v) The b / s line is
N cells are completed within the L frame time.

Since the cells are assembled independently for each channel, if the STM line speed multiplexed and input to the AAL processing unit is equal to the output ATM line speed, the occurrence of cells is biased in a certain frame. This causes a delay in waiting for a cell to be sent to the ATM network, which causes deterioration of communication quality. In the case where the multiplexed STM data is multiplexed on a single speed line, the transmission delay is set to 0 by shifting the cell generation interval in each frame by exactly L lines in response to such a delay. Such an embodiment has already been described.

However, in this embodiment, when (n × v) b / s lines are multiplexed in addition to vb / s, the transmission waiting delay cannot be completely set to zero. Therefore, in the embodiments to be described below, even if not only a constant speed v but also a speed of (n × v) is multiplexed, cell generation is performed so that the timing of cell generation is not biased in an arbitrary frame. An embodiment in which the delay can be eliminated by scheduling the start timing and distributing the cell generation will be described below.

FIG. 4 is an explanatory diagram showing another example of the structure of one frame, and shows the case of v = 64 kb / s as described above. Therefore, one frame period is 125 μs, and the multiplicity is 2016, which is the number of effective TSs in the case of SDH155.52 Mb / s.

A line having a speed v uses one TS in one frame and inputs exactly L bytes (Lp bits) in an L frame to complete a cell. Here, for example, 12
Using a modulo L counter that counts up every frame of a period of 5 μs, the frame is changed from 0 to (L-
The numbering of L in 1) will be performed. That is, if the frame number is 0 now, the number of the next frame will be 1, and after that, L frames will be 1 again.

Since the cell of each line of speed v is always completed in the L frame period, if the cell of a certain line is completed with the frame number i, the line is always the cell at the frame number i. Will be completed. Therefore, by deciding which frame number should be used to complete the cell of which TS line, the timing of cell generation can be controlled.

Table 1 above shows an example of allocating TS numbers by which cells can be completed at each frame number in the case of speed v. As can be seen from Table 1, every frame has L TS numbers, that is, 47 TS numbers. For example, if the cell of TS1 is completed,
It shows that it takes time to input 47 TS data to transmit it.

If, in the meantime, a cell on a different TS line is completed, that cell will be subjected to a transmission waiting delay. Therefore, in order to prevent such a delay, the next cell may be completed just after the transmission of the cell of TS1 is completed. That is TS48 which is shifted by 47TS. In this way, 47 frames are 20
Table 1 shows the allocation of all 16 TSs.

Under the control as described above, consider a case where lines of (n × v) speed are multiplexed. In the following, first n =
The case of 6 will be described. A line with a speed of (n × v) is
N TSs per line (channel) in one frame
Is used to store n bytes (np bits) in one frame, so that n cells are completed in an L frame. n =
6, that is, a line of 384 kb / s uses TS1 to TS6.

Now, in frame 0, the 384 kb / s line writes all 6 TS data to complete the cell,
Assuming that cell formation is started from the beginning of the TS from frame 1, the cell is completed at the time of storing 5TS in 6TS in frame 8 next. Thus, the 38 of the above example
Frames 0, 8, 16, 24, 3 for 4 kb / s lines
A cell occurs in 6 frames of 2 and 40.

When the TS1 to TS6 are used by the 384 kb / s line and the remaining TS are used by the 64 kb / s line, under the control of Table 1, a cell generation deviation and a transmission waiting delay occur. For example, in frame 8, a 384 kb / s cell is generated at the time of input of TS5 and is transmitted. However, according to the rules in Table 1, a cell of the TS9 line is generated next, and the cell is delayed in transmission waiting. Further, in that frame, one more cell is generated than the regulation, and conversely, the number of cells generated in frames 1 and 2 is small. This bias becomes even more pronounced as the number of 384 kb / s lines increases.

In order to prevent the occurrence of such a transmission waiting delay, the bias of the cell generation of the (n × v) b / s line is eliminated, the cell generation timing of the line and the n cells used by the line are used. It suffices that the cell generation timings when the above TSs are used on the vb / s line match.

For example, TS1 to TS6 are 384 kb /
When it is used as s, it occurs in frames 0, 8, 16, 24, 32, and 40, as described above,
Even when each of TS1 to TS6 is used at 64 kb / s, the cell may be controlled so as to occur in the above six frames.

In more detail, in frame 8 38
Since the cell is completed when the TS5 is input to the 4 kb / s line, the TS is still used in this frame even at 64 kb / s.
If 5 lines are allocated, cells will be generated at exactly the same timing. In this way, 384 kb / s
The following Table 2 shows an example of the cell generation regulation in the case where and 64 kb / s are multiplexed.

[0057]

[Table 2]

Table 2 is a specified example of the embodiment described below. In Table 2, all the consecutive TSs are arranged every 8 frames. Therefore, the TS used by 384 kb / s may be any TS as long as it is a serial number. This is from frame i to the next frame i,
This is because the (L + 1) frame can be divided into n equal parts. For example, if n = 24 (1.5 Mb / s),
It may be arranged every two frames (= 48/24).

When n is a divisor of (L + 1), to further generalize, the line of speed (n × v) is TSj, ..., T
Consider the case of using Sj + n. (L + 1) / n
= K, and the first cell conversion is started from frame i + 1.

The first cell is completed in frame i + k
Then, nk bytes of data are input during the k frame, and L bytes of the data are the first cell.
Since L = 1, one byte is stored at the beginning of the next cell. That is, in frame i + k, TS (j + n-1)
Since the cell is completed at the time of input of, the control is performed so that the cell of the TS (j + n-1) line is completed in this frame.

The next cell is completed in frame i + 2k,
At this time, similarly, 2 bytes are stored as the next cell, so that the cell is completed at the time of inputting TS (j + n-2). Therefore, in this frame, TS (j + n-
It is sufficient to control so that cells of the line of 2) are generated.

As described above, the continuous TSs are arranged every k, and as the frame number increases by k, the TS number decreases by one. Generally speaking, for any i,

In frame I ₀ , 1st, 1 + Lth, 1+
Control so that the 2L-th, ..., TS cells are completed,
Since (L + 1) / n is an integer, [(L + 1) / n
n] = (L + 1) / n

Frame I _m = (I _m-1- (L + 1) / n)
_modL (m = 1, 2, ..., L-1), and control is performed so that the 1 + mth, (1 + m) + Lth, ... TS cells in the frame are completed.

At this time, the calculation of (I _m-1- (L + 1) / n) is performed modulo L. That is, when it becomes negative, L is added to take a value between 0 and L-1. L takes a value from 0 to L-1, which can define all L frames.

Explaining Table 2 in more detail, for example, when TS5 is used as a line of 64 kb / s, control is performed so that the cell is completed in frame 8, that is, in the next frame 9, the cell This means that the control should be performed so that the data is stored at the head position.

Similarly, TS2 to TS7 are 384 kb / s.
TS2, 3, 4, 5,
Frames 0, 8, 16, 2 to which 6, 7 are assigned
At 4, 32, and 39, the cell is controlled to be completed. To do this, pay attention to TS7, which is the last TS of TS2 to 7, and TS7 is 64 kb /
When it is used for s, writing to the head position of the cell is performed in the frame 40. Therefore, even in the case of 384 kb / s, it is sufficient to control so that 6 TS data in the frame 4 are written from the head. .

When n is not a divisor of L + 1, the cell generation timing of the (n × v) b / s line and the n TSs used by the line are used at vb / s as described above. Although the cell generation timing at this time cannot be completely matched, a is an integer and a ≦ (L + 1) / n <
When satisfying (a + 1), note that the frame generated by the cell of the (n × v) b / s line is a or a + 1, and n frames used by the (n × v) b / s line TS
Are used in the respective vb / s lines, the frame intervals generated by the cells of the respective lines are a or a
Control to be +1.

Generally speaking, the frame interval is a
, The 1st, 1 + Lth, 1st frame I ₀
The control is performed so that the + 2Lth TS cell is completed, and

Frame I _m = (I _m-1 − [(L + 1) /
n]) _modL (m = 1, 2, ..., L−1), m + 1,
TSs of (m + 1) + L, (m + 1) + 2Lth, ...
And that were used at a speed v, then control such cell該回line is completed, provided that I _m is I _0, I _1, ..., equal to the one of I _m-1, its I _m 1 The added value is controlled to be I _m . Here, [(L + 1) / n] is a ≦ (L
Assume that it is equal to an integer a satisfying +1) / n <(a + 1).

On the other hand, when the frame interval is a + 1,
In frame I ₀ , 1st, 1 + Lth, 1 + 2Lth,
..., control to complete the TS cell, and

Frame I _m = (I _m-1 − [(L + 1) /
n] +1) _modL (m = 1, 2, ..., L-1), m +
TS of 1, (m + 1) + L, (m + 1) + 2Lth, ...
But controlled to cell該回line is completed and that were used at a speed v, but I _m is I _0, I _1, ..., equal to the one of I _m-1, to the I _m The value obtained by adding 1 is controlled to become I _m . Here, [(L + 1) / n] is a ≦ (L
Assume that it is equal to an integer a satisfying +1) / n <(a + 1).

FIG. 5 is an explanatory diagram for explaining a processing procedure (another embodiment of the present invention) using the above-described method, and an operation example will be described below.

In FIG. 5, v = 64 kb / s, L = 47, n
= 6, and a TS number is input, a configuration example of a control memory that obtains and outputs a cell assembly buffer address is shown. This control memory is for each line, at which position in the line number and cell assembly buffer area of each line. It is composed of a modulo 47 counter (hereinafter referred to as a sample counter) that specifies whether to write. The cell assembly buffer is 64 kb / s
It has a sufficient memory capacity to store cells for 2016 lines.

N = 6, that is, a line of 384 kb / s uses TS1 to TS6, and this is line 1, and the other lines are 64 kb / s. Line 1
The area of the cell assembly buffer is 6 times 64 kb / s, and the area is set from 1-1 to 1-6. Line 1 and T
Line 46, which is a 64 kb / s line using S52
Starts celling from frame 0.

As an initial setting of the sample counter, in order to generate a cell when the line 1 is in the frame 7 and TS5,
The sample counter value at 0 frame is set to 0,
Also, the same frame 7 is completed when TS52 is 64.
The kb / s line 46 sets the sample counter value to 39, and writes a silent pattern from the 1st byte to the 37th byte of the cell.

(A) When TS1 is input in frame 0, it is written in the 1st byte of 1-1 of the line 1 area of the cell assembly buffer according to the sample counter value 0 of line 1, and the sample counter is set to 1. It is updated, and similarly, up to TS6, the 6th byte of the cell assembly buffer is written, and the sample counter value is updated to 6.

(B) On the other hand, the line 46 of 64 kb / s
When the TS 52 is input, the data is stored in the 40th byte of the line 46 of the cell assembly buffer according to the sample counter value 39, and the sample counter value is updated to 40. Data is stored in this way, and at frame 7,

(C) In the line 1, TS5 according to the sample counter value 46, 47 in the area 1-1 of the cell assembly buffer.
When written in the byte, the cell is completed, the sample counter value is updated to 0, and the cell starts to be read. Next, the data of TS6 is written in the area of the 1st byte of 1-2 of the cell assembly buffer, and the sample counter value is updated to 1.

(D) The line 46 has a sample counter value of 46 when the TS 52 is input, and is written in the 47th byte of the line 46 of the cell assembly buffer to complete the cell. Since this cell is completed at the 47th byte after the cell on line 1 is completed, the cell on line 46 is completed when the cell on line 1 is just read from the buffer.

[0081]

As described above, according to the present invention, a certain cell is completed and is not being read while another cell is being completed. Is completed and the line usage rate is 100%
In this case, the transmission waiting delay can be completely suppressed to 0, and the transmission cost per line can be reduced.

Further, according to the present invention, a frame in which a cell of a (n × v) b / s line is generated and a cell in which a TS used by the line is used at vb / s are generated. The frames to be generated can be almost matched, and particularly when n is a divisor of L + 1 and the TS used in the line is a serial number, the timings generated by these cells can be matched completely.

As an effect, even in a frame in which a high speed line of (n × v) b / s is multiplexed in addition to a low speed line of vb / s, while a certain cell is being completed and read,
The other cell will not be completed and the next cell will be completed as soon as the reading of one cell is completed. Even if the line utilization is 100%, the transmission waiting delay can be suppressed to 0. The transmission cost per line can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram conceptually showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing specific examples of a control memory 5 and a cell assembly buffer 6 in FIG.

FIG. 3 is a flowchart showing an ATM cell assembly processing algorithm.

FIG. 4 is an explanatory diagram showing a configuration example of one frame.

FIG. 5 is an explanatory diagram for explaining another embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a transmission delay when a cell is completed and transmitted to an ATM network by a conventional technique.

[Explanation of symbols]

1 ... STM user data signal line, 2 ... ATM cell output line, 3 ... frame information input line, 4 ... TS counter, 5 ...
Control memory, 6 ... Cell assembly buffer, 7 ... Cell read control unit, 8 ... Silent pattern generation circuit, 9 ... Gate circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7240-5K H04L 13/00 307C

Claims (4)

[Claims] 1. N time slots in one frame
S, which has a frame structure including each channel and is transmitted at a rate of p bits for each time slot.
TM data string is received, and this is L × for each channel.
When assembling one ATM cell for each channel in the cell assembling method of assembling and transmitting the ATM cell corresponding to each channel consisting of a fixed-length data string of p bits (where N, p, and L are integers) ,
When the number of received frames required for the assembly is L, the first, second, and
......, the Lth frame number is attached, and hereinafter, it is assumed that the frame arrives by repeating this number, and the channel numbers of the N channels are taken out from the first number in order of number and every L number. The group of channel numbers obtained by the above is G1, and the group of channel numbers obtained by extracting every L number from the second number in the numerical order is G2. Hereinafter, when obtaining groups of channel numbers in the same manner, A group of each channel number is assigned to any one of the frame numbers and attached, and at the time of arrival of each of the first to Lth frames, the group belonging to the frame number is assigned. Controls the assembly timing of the ATM cells so that the ATM cells corresponding to the constituent channel numbers are assembled. ATM cell assembly wherein the door. 2. A plurality of time slots are assigned to a channel belonging to a certain first type out of N time slots included in one frame, and one channel is assigned to another channel belonging to a second type. The STM has a frame structure in which channels of the first and second types having different required numbers of time slots are mixed so that time slots are allocated, and p bits are transmitted per time slot. Receive the data string and
In the channel belonging to the first type, an ATM cell group corresponding to each channel is formed by a plurality of cells each having a fixed length data string of L × p bits, the number of which is the same as the number of required time slots per channel. In the cell assembly method of assembling and transmitting to the ATM cell corresponding to each channel composed of a fixed length data string of L × p bits for the channels belonging to the second type (however,
(N, n, p, L are integers), when assembling an ATM cell group corresponding to each channel or one ATM cell for each channel, the number of received frames required for the assembly is L, where L is the number of received frames. , L-th frame numbers are assigned to the received frames in the order of arrival, and hereinafter, it is assumed that the frames arrive by repeating this number, and the channel numbers of the N channels are first G1 is a group of channel numbers obtained by taking out every L number in the order of numbers from No. 1 to G2, and G2 is a group of channel numbers obtained by taking every L number from the second number in order of numbers. , In the same way, obtain a group of channel numbers and assign each channel number group to one of the frame numbers. In this case, when (L + 1) is divisible by n, the number obtained by the division is M, and a frame number separated by M from an arbitrary frame number assigned and assigned to the group G1 is set to the adjacent group. Assign G2 and attach it,
Hereinafter, this is repeated, and at the time of arrival of each of the first to Lth frames, the ATM cells corresponding to the channel numbers constituting the group belonging to the frame number are assembled so that the ATM cells are assembled. An ATM cell assembling method characterized by controlling an assembling timing. 3. A plurality of time slots are assigned to a channel belonging to a certain first type out of N time slots included in one frame, and one channel is assigned to another second type. The STM has a frame structure in which channels of the first and second types having different required numbers of time slots are mixed so that time slots are allocated, and p bits are transmitted per time slot. Receive the data string and
In the channel belonging to the first type, an ATM cell group corresponding to each channel is formed by a plurality of cells each having a fixed length data string of L × p bits, the number of which is the same as the number of required time slots per channel. In the cell assembly method of assembling and transmitting to the ATM cell corresponding to each channel composed of a fixed length data string of L × p bits for the channels belonging to the second type (however,
(N, n, p, L are integers), when assembling an ATM cell group corresponding to each channel or one ATM cell for each channel, the number of received frames required for the assembly is L, where L is the number of received frames. , L-th frame numbers are assigned to the received frames in the order of arrival, and hereinafter, it is assumed that the frames arrive by repeating this number, and the channel numbers of the N channels are first G1 is a group of channel numbers obtained by taking out every L number in the order of numbers from No. 1 to G2, and G2 is a group of channel numbers obtained by taking every L number from the second number in order of numbers. , In the same way, obtain a group of channel numbers and assign each channel number group to one of the frame numbers. In this case, if (L + 1) is not divisible by n, the integer obtained by rounding down the fraction obtained by the division is M, and the frame separated from the arbitrary frame number assigned by the group G1 is M frames. Number G and its adjacent group G
2 is assigned and attached, and this is repeated thereafter, but when another group is already assigned and attached to the frame number of the target to which a group is assigned and attached, the next unassigned To the frame number,
Assemble the ATM cells so that the ATM cells corresponding to the channel numbers constituting the group belonging to the frame number are assembled at the time of arrival of the first to Lth frames. An ATM cell assembling method characterized by controlling timing. 4. A plurality of time slots are assigned to a channel belonging to a certain first type out of N time slots included in one frame, and one channel is assigned to a channel belonging to another second type. The STM has a frame structure in which channels of the first and second types having different required numbers of time slots are mixed so that time slots are allocated, and p bits are transmitted per time slot. Receive the data string and
In the channel belonging to the first type, an ATM cell group corresponding to each channel is formed by a plurality of cells each having a fixed length data string of L × p bits, the number of which is the same as the number of required time slots per channel. In the cell assembly method of assembling and transmitting to the ATM cell corresponding to each channel composed of a fixed length data string of L × p bits for the channels belonging to the second type (however,
(N, n, p, L are integers), when assembling an ATM cell group corresponding to each channel or one ATM cell for each channel, the number of received frames required for the assembly is L, where L is the number of received frames. , L-th frame numbers are assigned to the received frames in the order of arrival, and hereinafter, it is assumed that the frames arrive by repeating this number, and the channel numbers of the N channels are first G1 is a group of channel numbers obtained by taking out every L number in the order of numbers from No. 1 to G2, and G2 is a group of channel numbers obtained by taking every L number from the second number in order of numbers. , In the same way, obtain a group of channel numbers and assign each channel number group to one of the frame numbers. When (L + 1) is not divisible by n, the integer obtained by rounding down the fraction obtained by the division is M, and (M + 1) is separated from any frame number assigned by the group G1. The adjacent group G2 is assigned to and attached to the frame number that has been added, and this process is repeated below. However, another group is already assigned and attached to the frame number of the target frame to be assigned and attached. In this case, it is assigned and attached to the next unassigned frame number, and at the time of arrival of each of the first to Lth frames, the channel number corresponding to the group belonging to the frame number is associated. The ATM cell is characterized by controlling the assembly timing of the ATM cells so that the assembled ATM cells can be assembled. Assembly method.