JPH06259999A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory device by which defects are quickly detected by inactivating a clock generator. CONSTITUTION:As a high level is provided through an inverter 95 when a bar-in mode control input BM is at a low level, a signal is outputted corresponding to a pulse DTD by a NAND gate 94 to perform the same operation as the conventional ATD. A low level is provided through the inverter 95 when the bar-in mode control input BM is at a high level; thus, a high level signal is outputted by the NAND gate 94 regardless of the pulse DTD, the output of a NOR gate 92A is always at a low level, and the ATD0 is always at a high level through an inverter 93.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, by inactivating a clock generator, problems due to incorrect timing of pulses generated by the clock generator are eliminated, and defect analysis in a memory cell is performed. Static type semiconductor memory device (hereinafter,
It is called "SRAM". ) Is related to.

[0002]

2. Description of the Related Art The structure of a conventional SRAM will be described with reference to FIG. FIG. 16 is a diagram showing a configuration of a conventional SRAM. In FIG. 16, this SRAM 10
2 includes n memory blocks BK ₁ to BK _n and a block selector 8 for selecting a memory block to be accessed. Memory blocks BK ₁ to B
One of K _n , for example the memory block BK ₁ , should be accessed with the memory cell array 1 ₁ having memory cells (not shown) arranged in rows and columns, and the bit line load circuit 17 _1. It includes a multiplexer 2 ₁ for selecting a bit line pair, a write buffer 3 ₁ for writing data, and a sense amplifier 4 ₁ for reading data. Similar circuit configurations are provided in the other memory blocks BK ₂ to BK _n .

SRAM 102 further receives a row address buffer 51 which receives a row address signal RA externally applied, a column address buffer 52 which receives a column address signal CA externally applied, and a block address signal BA externally applied. A block address buffer 53, a row decoder 6 for decoding the row address signal RA, a column decoder 7 for decoding the column address signal CA, and a block for selecting a block to be accessed by decoding the block address signal BA. A selector 8, a data input buffer 55 that receives input data DI, a data output buffer 56 that outputs an output data signal DO, and a read operation that operates in response to a chip select signal / CS and a write enable signal / WE externally applied. / And a write control circuit 54. The data holding circuit 57 and the clock generator 58 will be described later.

Next, a normal access operation of the above-mentioned conventional SRAM will be described. For example, when the memory block BK ₁ is accessed, the block address signal BA for designating the memory block BK ₁ is applied to the block selector 8 via the block address buffer 53. The block selector 8 decodes the applied block address signal BA and selectively activates only the write buffer 3 ₁ and the sense amplifier 4 ₁ . In reading data, the row decoder 6 causes the row address signal RA
One word line of the memory cell array 1 ₁ in response (not shown) is activated. The column decoder 7 selects one column in the memory cell array 1 ₁ in response to the column address signal CA. Therefore, the data signal stored in the memory cell designated by row decoder 6 and column decoder 7 is applied to sense amplifier 4 ₁ via multiplexer 2 ₁ . The data signal amplified by the sense amplifier 4 ₁ is output as output data DO via the data output buffer 56.

In the write operation, the input data DI is transferred to the write buffer 3 ₁ via the data input buffer 55.
Given to. The column decoder 7 selects one column in the memory cell array 1 ₁ in response to the column address signal CA.
Row decoder 6 activates one word line in memory cell array 1 ₁ in response to row address signal RA. Therefore, the write buffer 3 ₁ has the multiplexer 2 ₁
A data signal is written to the memory cell designated by the row decoder 6 and the column decoder 7 via.

FIG. 17 is a circuit diagram showing a peripheral circuit of the memory cell array 1 ₁ shown in FIG. In FIG. 17, four memory cells in the memory cell array 1 ₁ are shown to simplify the display.
Only one memory cell 24a-24d is shown. The memory cells 24a and 24c are connected to the bit line 20a.
And 20b. Memory cells 24b and 24d are connected between bit lines 21a and 21b.

The bit line load circuit 17 ₁ has a power supply potential Vcc.
And an NMOS transistor 25 connected between the corresponding bit line 20a, 20b, 21a and 21b
a, 25b, 26a and 26b. On the other hand, the multiplexer 2 ₁ includes I / O line pair 29a, 29b and the bit lines 20a, 20b, connected NMOS transistors 27a between 21a and 21b, 27b, the 28a and 28b. The I / O line pairs 29a and 29b are connected to the input side of the sense amplifier 4 _{1 and} the output side of the write buffer 3 ₁ .

Row decoder 6 selectively activates one of word lines WL ₀ and WL ₁ connected to the memory cell to be accessed. The memory cells 24a and 24b connected to the word line WL _{0 form} one memory cell row. When word line WL ₀ is activated, the memory cell row including memory cells 24a and 24b is accessed. On the other hand, the column decoder 7 selects the column selection signals Y0 and Y0 for selecting the memory cell column to be accessed.
1 is activated. For example, when column select signal Y0 is activated, transistors 27a and 27b are turned on, so that the memory cell column including memory cells 24a and 24c is accessed.

FIG. 18 is a circuit diagram showing an example of the memory cell shown in FIG. In FIG. 18, this memory cell MC ₁ (for example, the memory cell 24a in FIG. 17) is
It includes MOS transistors 41a and 41b, resistors 43a and 43b as high resistance loads, and NMOS transistors 42a and 42b as access gates.

FIG. 19 is a circuit diagram showing another example of the memory cell shown in FIG. In FIG. 19, this memory cell MC ₂ (for example, the memory cell 24a in FIG. 17) is
It includes NMOS transistors 41a and 41b, PMOS transistors 44a and 44b serving as loads, and NMOS transistors 42a and 42b serving as access gates.

In the memory cell selected by the word line and the operating sense amplifier, a current constantly flows.
Therefore, in order to reduce the activation time and reduce the current consumption during low-speed operation, a pulse is generated by detecting a change in address or data, and the pulse signal shortens the operation time of the circuit. Such improvements have been made.

Referring again to FIG. 16, the SRAM 102 is
Further, the data holding circuit 57 for holding the output signal of the data input buffer 55 and the input signal of the data output buffer 56, and the change of the row address buffer 51, the column address buffer 52, the block address buffer 53, and the data input buffer 55. Correspondingly generates a pulse,
Row decoder 6 by the pulse, to 4 ₁ sense amplifier includes a clock generator 58 for defining the activation time of 4 _n and the data holding circuit 57.

FIG. 20 is a block diagram showing a structure of clock generator 58 shown in FIG. 20, a row address buffer 51 and a column address buffer 5
Pulse generator circuits 60 ₁ to 60 _m that receive the signal _{No. 2} and generate a pulse when the signal changes, and pulse generator circuits 61 ₁ that receive the signal from the block address buffer 53 and generate a pulse when the signal changes Through 61
_j, and a pulse generation circuit (data change detection circuit) 61 which receives data input buffer 55 and write control input WE1 and generates a pulse DTD when data input buffer 55 changes during writing.

The clock generator 58 further receives a pulse generated from the pulse generation circuits 60 ₁ to 60 _m , an OR gate 62 generating a pulse SATD1, and a pulse generated from the pulse generation circuits 61 ₁ to 61 _j , OR gate 63 for generating pulse SATD2, and O
A pulse ATD0 for activating the row decoder 6 by receiving the output of the R gate 62, the output of the OR gate 63, the pulse of the pulse generating circuit 61 and the write control input WE1.
It a sense amplifier 4 ₁ including ATD (address transition detection circuit) 64 which generates a pulse RDL for activating the pulse ATD1 and the data holding circuit 57 for activating the 4 _n.

Pulse generator circuits 60 ₁ to 60 _m , 61 _1
Through 61 _j generate a pulse when the row address RA, the column row address CA or the block address BA changes. By taking the logical sum of the pulse, activates at least one row address RA, when a column row address CA or the block address BA changes, the row decoder 6, a sense amplifier 4 ₁ to 4 _n and the data holding circuit 57 Sufficient pulses are generated at ATD 64 to cause this.

At the time of reading, first the row decoder 6 is activated, then the sense amplifiers 4 ₁ to 4 _n are activated, and when the data is determined, the data holding circuit 57 is activated for a while. After that, the sense amplifiers 4 ₁ to 4 _n
Is turned off, and after a while, the row decoder 6 is turned off. Then, even if the sense amplifiers 4 ₁ to 4 _n are turned off, the output data is held by the data holding circuit 57 and the data is still output.

At the time of writing, the data can be rewritten by changing the data holding circuit 57 and activating only the row decoder 6 according to the input data. After writing, if the address is not changed, the data in the data holding circuit 57 is output.

FIG. 21 is a circuit diagram of the ATD 64 shown in FIG. 21, a NOR gate 70 that receives pulses SATD1 and SATD2 and a delay circuit (RD: Rise Del) that receives an output signal A of the NOR gate 70 are provided.
ay) 71, a delay circuit 72 that receives the output signal B of the delay circuit 71, a delay circuit 73 that receives the output signal C of the delay circuit 72, an inverter 74 that receives the output signal D of the delay circuit 73, and an output of the inverter 74. Inverter 75 receiving signal E and inverter 76 receiving output signal A of NOR gate 70 are included. The delay circuits 71, 72, 73 delay only the rising edge of the signal.

The ATD 64 has a node N on the input side.
Inverter 77 connected to ₁ , input side is node N ₁
And the inverter 7 whose output side is connected to the node N _2.
8, an inverter 79 having an input side connected to the node N ₂ and an output side connected to the node N ₁ , and an NMOS transistor 80 having a gate to which the write control input WE1 is input.
And an NMOS transistor 81 whose gate receives the output signal F of the inverter 76.

The ATD 64 has a PMOS transistor 86 whose gate receives the output signal G of the inverter 77, a PMOS transistor 87 whose gate receives the output signal H of the inverter 75, and a NO gate.
The PMOS transistor 88 to which the output signal A of the R gate 70 is input, the NMOS transistor 89 to which the output signal H of the inverter 75 is input to the gate, and the N to which the output signal A of the NOR gate 70 is input to the gate
A MOS transistor 90, and an NMOS transistor 91 whose gate receives the output signal G of the inverter 77.
Including and PMOS transistors 87 and 88, NM
OS transistors 89 and 91 are connected to node N ₃ .

ATD 64 further includes a NAND gate 82 for receiving an output signal E of inverter 74, an output signal of inverter 79 and an output signal C of delay circuit 72, and an NA.
An inverter 83 for receiving the output signal of the ND gate 82,
A NAND gate 84 receiving the output signal E of the inverter 74, the output signal of the inverter 79 and the output signal B of the delay circuit 71, an inverter 85 receiving the output signal of the NAND gate 84, a NOR receiving the signal of the node N ₃ and the pulse DTD. It includes a gate 92 and an inverter 93 that receives the output signal of NOR gate 92.

FIG. 22 is a timing chart for explaining the operation of ATD 64 shown in FIG. Figure 21
The operation of the ATD 64 will be described below with reference to FIG.

In operation, the write control input WE1 is at low level during reading. As shown in FIG. 22A, the signal SATD1 or SATD2 changes from time t ₁₀ to time t _{10.
When a} high level signal up to _{11 is} applied to the NOR gate 70, the output signal A of the NOR gate 70 outputs a low level from time t ₁₀ to t _11, as shown in FIG. The signal A is delayed only by the rising edge by the delay circuit 71, and the signal B is delayed from the time t ₁₀ to t ₁₂ (t
It becomes low level until ₁₁ <t ₁₂ ). Further, the signal B is delayed only by the rising edge by the delay circuit 72, and the signal C becomes low level from time t ₁₀ to t ₁₃ (t ₁₂ <t ₁₃ ) as shown in FIG. Further, the signal C is delayed only by the rising edge by the delay circuit 73, and as shown in FIG.
The signal D becomes low level from time t ₁₀ to t ₁₄ (t ₁₃ <t ₁₄ ).

The signal D is inverted by the inverter 74,
As shown in (f) of the same figure, the signal E changes from time t ₁₀ to t
_It goes high up to ₁₄ (t ₁₃ <t ₁₄ ). Further, the signal A is inverted by the inverter 76, and the signal F becomes high level from time t ₁₀ to t ₁₁ . Since WE1 is low, the transistor 80 does not turn on. Therefore, at the time of reading, once the address changes, the transistor 81 is turned on, and the node N ₁ holds the high level and the node N ₂ holds the low level. Therefore, the signal G maintains the low level.

Therefore, the node N ₃ becomes high level when the signal A or the signal H is low level. D when reading
TD remains low. Therefore, the node N ₃
Is high level, the NOR gate 92 becomes low level,
ATD0 goes high through the inverter 93. Further, when the signal B and the signal E are at the high level, the NAND gate 84 becomes the low level, and the NAND gate 84 becomes
TD1 goes high. Furthermore, signal C and signal E
Is high, NAND gate 82 goes low and RDL goes high through inverter 83.

[0026] Thus, FIG. (I), as shown in (j) and (k), a high level ATD0 from time t ₁₀ to t _14, ATD1 high level from the time t ₁₂ to t _14, RDL
Becomes high level from time t ₁₃ to t ₁₄ .

Further, at the time of writing, the write control input W
E1 is at a high level. WE1 is at a high level, so
Transistor 80 turns on and node N ₁ remains low. Therefore, the signal G maintains the high level.

Therefore, the node N ₃ becomes low level. At the time of writing, the pulse generation circuit 61 generates a pulse DTD when the input data changes. When DTD is high, NOR gate 92 goes low and, through inverter 93, ATD0 goes high. Also, NA
The ND gate 84 goes high and the ATD1 goes low via the inverter 85. Further, the NAND gate 82 becomes high level and the RD is passed through the inverter 83.
L goes low.

Therefore, ATD0 is always at a high level in response to DTD, ATD1 is always at a low level, and RDL is always at a low level.

FIG. 23A is a timing chart for explaining the read operation of the memory cell 24a shown in FIG. In FIG. 23A, the horizontal axis represents the passage of time and the vertical axis represents the potential (V: volt). Line A
D _i indicates changes in the input signals of the row address buffer 51 and the column address buffer 52. Line AD ₀ shows changes in output signals of row address buffer 51 and column address buffer 52. The line WL is a memory cell 24
The change of the word line WL ₀ connected to a is shown. Line I
/ O indicates a change in potential of the I / O line pair 29a and 29b. The line SA ₀ shows the change in the output voltage of the sense amplifier 4 ₁ . Line D ₀ shows the change in the output voltage of the data output buffer 56.

FIG. 23B shows the ATD6 shown in FIG.
4 is a timing chart of pulses generated in No. 4 of FIG. In FIG. 23 (b), the horizontal axis indicates the passage of time,
The vertical axis represents the potential (V: volt).

At time t ₀ , the input address signal AD _i
Is changed. Therefore, output signals AD ₀ of row address buffer 51 and column address buffer 52 change at time t ₁ . At time t ₂ , word line WL
_Since the potential of ₀ changes, the data signal stored in the memory cell 24a is transmitted to the bit line pair 20a, 20b. In addition to this, since the column selection signal Y0 output from the column decoder 7 becomes high level, the transistor 27a
And 27b turn on. Thus, at time t _3, the potential of the I / O line pairs 29a and 29b are changed.

The sense amplifier 4 ₁ at time t ₄ is the control signal and AT supplied from the read / write control circuit 54
Because it is activated in response to ATD1 given from D64, the amplification of the data signal by the sense amplifier 4 ₁ it is performed. Therefore, at time t ₅ , the output signal DO of the data output buffer 56 changes according to the data read from the memory cell 24a.

At time t ₆ , the data holding circuit 57
Since it is activated in response to the control signal given from read / write control circuit 54 and RDL given from ATD 64, the data held in data holding circuit 57 changes and is given from ATD 64 at time t _7. Since it is inactivated in response to the RDL, the data held in the data holding circuit 57 does not change.

At time t ₈ , the sense amplifier 4 ₁ turns ATD64
Since inactivated in response to ATD1 given from the sense amplifier 4 ₁ is not outputted, so continues to output the data held in the data holding circuit 57,
The output signal DO of the data output buffer 56 is the memory cell 2
The data read from 4a continues to be output. Time t ₈
, Column decoder 7 is inactivated in response to ATD0 provided from ATD64, so that word line WL
The potential of ₀ becomes low level.

In this way, the time for selecting the memory cell by the word line and the time during which the sense amplifier is operating are shortened to reduce the current consumption.

By actually using the ATD circuit, the current consumption is reduced at low speed operation, but the number of circuits to be operated is increased. Therefore, at the time of high speed operation, even if this internal synchronization system is adopted, the current consumption can be reduced. Instead, the current consumption increases.

Further, since each circuit is operated at a timing by adopting this internal synchronization system, a problem often occurs in this operation timing in the initial development stage, and the cause of this SRAM defect is in the memory cell. It is not possible to confirm whether there is any or there is a defect in the circuit.

In the pre-shipment test, generally, an acceleration test (test) of a semiconductor device is performed. The SRAM is also subjected to an acceleration test by applying environmental stress (temperature, humidity, vibration, etc.) and electrical stress (voltage, current, etc.) to the SRAM. That is, after the above stress is applied to the SRAM, data writing and data reading are performed on the SRAM. Data writing and data reading are repeated for all the memory cells in the memory cell array, and it is confirmed that the write data and the read data always match. If no match between the write data and the read data is detected, the SRAM is discarded as a defective product.

It takes a very long time to perform the above-mentioned data writing and reading for each memory cell and individually read out the coincidence. Therefore, in recent years,
The following improvements have been made to reduce the test time.

FIG. 24 is a block diagram showing another conventional SRAM. In FIG. 24, this SRAM 103
Includes a coincidence detection circuit 5 connected to receive the data signals output from the sense amplifiers 4 ₁ to 4 _n . The other circuit configuration of the SRAM 103 is the same as that of the SRAM 102 shown in FIG.

When test mode signal TM is externally applied via spare terminal 600, coincidence detection circuit 5, write buffers 3 ₁ to 3 _n and sense amplifiers 4 ₁ to 4 _n are simultaneously activated. As a result, the common input signal DI can be written in the memory cell of the corresponding address in each of the memory cell arrays 1 ₁ to 1 _n . Furthermore, the data signals read from the memory cells of the corresponding addresses in the memory cell arrays 1 ₁ to 1 _n can be simultaneously applied to the coincidence detection circuit 5 via the sense amplifiers 4 ₁ to 4 _n. Become. The signal indicating the match detection result is output to the outside through the data output buffer 56 in the test mode.

While the test mode signal TM is being applied, the row address signal RA and the column address signal CA
Are repeatedly given to each memory cell array 1 ₁ to 1 _n.
The data signal is written in the memory cell of the corresponding address in the inside, and the stored data signal is read out.
When the match detection circuit 5 detects a match between the write data and the read data at any address, the SRAM is determined to be "non-defective".
As described above, by using the coincidence detection circuit 5, the data writing and the data reading can be repeated in parallel for all the memory cell arrays 1 ₁ to 1 _n , so that the time required for the test can be shortened.

Further, since it takes a very long time to perform the stress application (burn-in) by the above-mentioned data writing for each memory cell, in recent years, the following improvements have been made in order to shorten the stress application time. Has been done.

Referring again to FIG. 24, the SRAM 103 is
When the burn-in mode signal BM is externally applied via the spare terminal 601, all the output signals of the column decoder 7 become the selection level, and the multiplexers 2 ₁ to 2 _n and the write buffers 3 _{1 to} 3 _n are simultaneously activated. . As a result, the common input signal DI can be written in the memory cells of the same row address in each of the memory cell arrays 1 ₁ to 1 _n .

While the burn-in mode signal BM is being applied, the row address signal RA is repeatedly applied,
A data signal is written in the memory cell of the corresponding address in each of the memory cell arrays 1 ₁ to 1 _{n to} apply stress. In this way, all memory cell arrays 1 ₁
Since data can be written in parallel for 1 to 1 _n , the time required for burn-in is shortened.

[0047]

In the conventional semiconductor memory device having the clock generator, the pulse operation during writing shortens the effective time for stressing the memory cell in the burn-in mode, thereby detecting a defect. There was a problem that it took time.

Further, in the conventional semiconductor memory device having the clock generator, the test mode function and the burn-in mode function, the clock generator used for saving the current consumption during the normal use when the test mode function is operated. However, there is a problem in that the timing is deviated and a defect that should be originally detected cannot be detected.

The present invention has been made in order to solve the above problems, and makes the original defective product detection efficient by inactivating the clock generator in the burn-in mode or the test mode. The object is to obtain a semiconductor memory device capable of

[0050]

A semiconductor memory device according to claim 1 of the present invention normally generates a pulse in response to a change in address and activates a specific circuit as necessary.
It is provided with a clock generator that constantly activates a circuit that is activated only for a certain period based on the input of a control signal.

In the semiconductor memory device according to claim 2 of the present invention, normally, a pulse is generated in response to a change in the address buffer or the data input buffer to activate the row decoder, the sense amplifier and the data holding circuit, and the burn-in is performed. A clock generator that does not generate the pulse in the mode is provided.

In a semiconductor memory device according to a third aspect of the present invention, normally, a pulse is generated in response to a change in an address buffer or a data input buffer to activate a row decoder, a sense amplifier and a data holding circuit, and a test is performed. A clock generator that does not generate the pulse in the mode is provided.

[0053]

In the semiconductor memory device according to the first aspect of the present invention, the clock generator normally generates a pulse in response to a change in address, activates a specific circuit as needed, and outputs a control signal. A circuit that is activated only for a certain period based on the input is always activated.

In the semiconductor memory device according to the second aspect of the present invention, the clock generator normally generates a pulse in response to a change in the address buffer or the data input buffer, and the row decoder, the sense amplifier and the data holding circuit. Is activated and the pulse is not generated in the burn-in mode.

In the semiconductor memory device according to the third aspect of the present invention, the clock generator normally generates a pulse corresponding to the change of the address buffer or the data input buffer, and the row decoder, the sense amplifier and the data holding circuit are provided. Are activated, and the pulse is not generated in the test mode.

[0056]

【Example】

Example 1. The configuration of the first embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3. 1 is a block diagram showing a first embodiment of the present invention. 2 is a block diagram showing a clock generator according to the first embodiment of the present invention. Further, FIG. 3 shows A of the first embodiment of the present invention.
It is a circuit diagram which shows TD.

Referring to FIG. 1, the SRAM 100 has a burn-in mode control input BM and a row address buffer 5.
1, the column address buffer 52, block address buffer 53, in response to a change of the data input buffer 55 generates a pulse, the row decoder 6 by the pulse, the sense amplifier 4 ₁ to 4 activation time _n and the data holding circuit 57 And a clock generator 58A that does not generate a pulse in the burn-in mode. Except for the clock generator 58A, the other circuit configuration of the SRAM 100 is
Since it is similar to the conventional SRAM 102 shown in FIG. 16, description thereof will be omitted.

FIG. 2 is a block diagram showing a configuration of clock generator 58A shown in FIG. In FIG. 2, the output of the OR gate 62, the output of the OR gate 63, the pulse of the pulse generation circuit 61 and the write control input WE.
Pulse A for receiving 1 and activating the row decoder 6
And TD0, to sense amplifier 4 ₁ pulse ATD1 to activate the 4 _n, to generate a pulse RDL for activating the data holding circuit 57, burn mode does not generate a pulse ATD (address transition detection Circuit) 64A. Except for the ATD 64A, the other circuit configuration of the clock generator 58A is similar to that of the clock generator 58 shown in FIG.

FIG. 3 is a circuit diagram of the ATD 64A shown in FIG. In FIG. 3, burn-in mode control input BM
An inverter 95 receiving the pulse DTD, an NAND gate 94 receiving the output signal of the inverter 95 and the output signal of the inverter 96, and an N receiving the signal of the node N ₃ and the output signal of the NAND gate 94.
It includes an OR gate 92A. Inverter 93 receives the output signal of NOR gate 92A. Except for the NOR gate 92A, the other circuit configuration of the ATD 64A is similar to that of the conventional ATD 64 shown in FIG.

When the burn-in mode control input BM is at a low level, a high level is given through the inverter 95, so that the NAND gate 94 outputs a signal corresponding to the pulse DTD, and operates similarly to the conventional ATD64. .

When the burn-in mode control input BM is at a high level, a low level is given through the inverter 95, so that the NAND gate 94 outputs a high level signal regardless of the pulse DTD, and the output of the NOR gate 92A is always output. It goes low and ATD0 is always high through the inverter 93.

Therefore, the burn-in mode control input BM
Is set to a high level, the word line that is always selected is in an activated state, and stress can be continuously applied to the memory cell. As a result, it is possible to shorten the time for applying stress in the burn-in mode.

Example 2. The configuration of the second embodiment of the present invention will be described with reference to FIGS. 4, 5 and 6. Figure 4
FIG. 6 is a block diagram showing the configuration of Embodiment 2 of the present invention. FIG. 5 is a block diagram showing a clock generator according to the second embodiment of the present invention. Further, FIG. 6 is a circuit diagram showing an ATD according to the second embodiment of the present invention.

In FIG. 4, the SRAM 104 is an ATD.
Control input CLA, usually row address buffer 51, column address buffer 52, block address buffer 5
3, in response to a change of the data input buffer 55 generates a pulse, the row decoder 6 by the pulse defines the activation time of the sense amplifier 4 ₁ to 4 _n and the data holding circuit 57, ATD when not in use pulses A clock generator 58C that does not generate Clock generator 5
Except for 8C, the other circuit configuration of the SRAM 104 is shown in FIG.
Since it is the same as the conventional SRAM 102 shown in FIG.

FIG. 5 is a block diagram showing a configuration of clock generator 58C shown in FIG. In FIG. 5, the output of the OR gate 62, the output of the OR gate 63, the pulse of the pulse generation circuit 61, and the read / write control circuit 5
4 to receive the signal WE1 output from the signal line 4 and a pulse ATD0 for activating the row decoder 6 and the sense amplifier 4 ₁
ATD1 for activating 4 to 4 _n and pulse RDL for activating the data holding circuit 57, and ATD which does not generate a pulse when the ATD is not used
Including 64C. Except for the ATD 64C, the other circuit configuration of the clock generator 58C is similar to that of the conventional clock generator 58 shown in FIG.

FIG. 6 is a circuit diagram of the ATD 64C shown in FIG. In FIG. 6, ATD control inputs CLA and NA
NAND gate 83 that receives the output signal of ND gate 82
A, a NAND gate 85A that receives the ATD control input CLA and the output signal of the NAND gate 84, and a NAN that receives the ATD control input CLA and the output signal of the NOR gate 92.
D gate 93A is included. NAND gates 83A and 85
Other than A and 93A, the other circuit configuration of ATD64C is
Since it is the same as the conventional ATD 64 shown in FIG. 21, description thereof will be omitted.

When the ATD control input CLA is at a high level, the NAND gates 83A, 85A and 93A output signals corresponding to the output signals of the NAND gates 82 and 84 and the NOR gate 92, respectively.
It operates like 64.

When the ATD control input CLA is at a low level, all the NAND gates 83A, 85A and 93A always output a high level signal regardless of the output signals of the NAND gates 82 and 84 and the NOR gate 92,
ATD0, ATD1 and RDL are always high level.

Therefore, if the ATD control input CLA is set to a high level, the same operation as in the conventional case of the internal synchronization system is performed. Further, if the ATD control input CLA is set to a low level, the ATD control input CLA does not operate in the internal synchronization system and can be operated independently of the ATD 64C.

As a result, the number of circuits to be operated does not increase, so that the current consumption does not increase during high speed operation.
Further, since there is no problem in the operation timing, it is possible to confirm whether the cause of the defect of the SRAM 104 is the memory cell or the circuit defect.

Example 3. The configuration of the third embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 is a block diagram showing the configuration of the third embodiment of the present invention. 8 is a block diagram showing a clock generator according to the third embodiment of the present invention.

In FIG. 7, the SRAM 105 is an ATD.
Control input CLA, usually row address buffer 51, column address buffer 52, block address buffer 5
3, in response to a change of the data input buffer 55 generates a pulse, the row decoder 6 by the pulse defines the activation time of the sense amplifier 4 ₁ to 4 _n and the data holding circuit 57, ATD when not in use pulses A clock generator 58D that does not generate Clock generator 5
Except for 8D, the other circuit configuration of the SRAM 105 is shown in FIG.
Since it is the same as the conventional SRAM 102 shown in FIG.

FIG. 8 is a block diagram showing a configuration of clock generator 58D shown in FIG. In FIG. 8, a row address buffer 51 and a column address buffer 52
Pulse generator circuits 60A ₁ to 60A _m that receive a signal of, and generate a pulse when the signal changes, and do not generate a pulse when the ATD is not used (when CLA is at a low level),
When a signal from the block address buffer 53 is received, a pulse is generated when the signal changes, and when the ATD is not used (CL
When ATD is not in use (C is low), the pulse generators 61A ₁ to 61A _j that do not generate a pulse, the data input buffer 55 and the write control input WE1 are received.
A pulse generation circuit (data change detection circuit) 61A that does not generate a pulse is included when LA is at a low level.

The clock generator 58D further includes
An OR gate 62 which receives a pulse generated from the pulse generation circuits 60A ₁ to 60A _m and generates a pulse SATD1
And an OR gate 63 which receives a pulse generated from the pulse generation circuits 61A ₁ to 61A _j and generates a pulse SATD2.

Except for the pulse generation circuits 60A ₁ to 60A _m , the pulse generation circuits 61A ₁ to 61A _j , and the pulse generation circuit (data change detection circuit) 61A, the other circuit configuration of the clock generator 58D is the same as that shown in FIG. Example 2
The clock generator 58C is the same as the clock generator 58C in FIG.

When the ATD control input CLA is at a high level, the pulse generation circuits 60A ₁ to 60A _m , the pulse generation circuits 61A ₁ to 61A _j , and the pulse generation circuit 61A generate pulses as before, and the ATD 64C also operates.
It operates similarly to the clock generator 58C.

When the ATD control input CLA is at a low level, the pulse generating circuits 60A ₁ to 60A _m , the pulse generating circuits 61A ₁ to 61A _j and the pulse generating circuit 61A do not generate a pulse. However, ATD64C is ATD
0, ATD1, and RDL are always high level.

Therefore, if the ATD control input CLA is set to a high level, the same operation as the conventional one by the internal synchronization system is performed. Further, if the ATD control input CLA is set to a low level, the ATD control input CLA does not operate in the internal synchronization system and can be operated independently of the ATD 64C.

As a result, since the number of circuits to be operated does not increase, current consumption does not increase during high speed operation.
Further, since there is no problem in the operation timing, it becomes possible to confirm whether the cause of the defect of the SRAM 105 is the memory cell or the circuit defect.

Example 4. FIG. 9 is a block diagram showing the configuration of the fourth embodiment of the present invention. In FIG. 9, this SR
The AM 106 is connected to the pulse detection circuit 201 for detecting the pulse width of the pulse signal given from the write control input / WE input to the terminal 203 and the terminal 200 for receiving the most significant bit signal of the block address signal BA. And an ATD control signal holding circuit 202 which is operated. The other circuit configuration of the SRAM 106 is similar to that of the SRAM according to the second or third embodiment.

FIG. 10 shows the pulse detection circuit 2 shown in FIG.
It is a circuit diagram which shows 01. 10, a pulse detection circuit 201 includes an inverter 210 connected to receive a pulse signal PL, a delay circuit 211 receiving an inverted pulse signal / PL, and a signal / PL and a delayed signal / PLD. It includes a NAND gate 212. NA
The output signal of the ND gate 212 is A as a holding signal HD.
It is given to the TD control signal holding circuit 202.

FIG. 11 is a timing chart showing the operation of the pulse detection circuit 201 shown in FIG. Figure 10
The operation mode specifying operation will be described with reference to FIGS.

The pulse signal PL for requesting the holding of the ATD control signal is output via the terminal 200 to the pulse detection circuit 2.
Given to 01. The pulse signal PL is supplied to the inverter 21.
Given to 0. As a result, the inverted pulse signal / PL is output via the inverter 210.

The pulse signal / PL is delayed by the delay circuit 211, and the delayed pulse signal / PLD is NANDed.
Provided to gate 212. NAND gate 212 is
It also receives a pulse signal / PL. The delay time ΔT in the delay circuit 211 is set to 100 ms, for example. Therefore, the NAND gate 212 receives the pulse signal / PL.
Is low level over the delay time ΔT, in other words, when the pulse signal / PL has a pulse width over ΔT, the low level signal HD is output. That is,
As shown in FIG. 11B, the NAND gate 212 outputs the low-level signal HD at time t2 when the delay time ΔT has elapsed after the pulse signal / PL fell at time t1.

The ATD control signal holding circuit 202 is brought into a holding state for the ATD control input CLA in response to the low level holding signal HD. At time t3, as shown in FIG. 11A, the ATD control signal CLA ′ for canceling the internal synchronization falls via the terminal 200. Therefore, the ATD control signal holding circuit 202 holds the low level ATD control signal CLA ′ in response to the low level holding signal HD. The held signal is output from the ATD control signal holding signal 202 as a low level ATD control signal CLA. When the low level ATD control signal CLA is output, the internal synchronization is released in the SRAM 106.

After the ATD control signal CLA is once held in the ATD control signal holding circuit 202, the terminal 2
00 and 203 do not need to continue to provide any special signal. Therefore, these terminals 200 and 203 are
It can be used as usual.

On the other hand, the release of this mode is performed as follows. At time t11, a low level pulse signal / P
L is given to the pulse detection circuit 201. At time t12 when the delay time ΔT has elapsed from time t11, the pulse detection circuit 201 outputs the low-level signal HD. Therefore, the ATD control signal holding circuit 202 becomes ready to hold the ATD control signal CLA in response to the low level holding signal HD.

At time t13, the high level ATD control signal CLA 'is applied to the ATD control signal holding circuit 202. Therefore, the ATD control signal holding circuit 202 holds the high level signal CLA 'and outputs the held signal as the ATD control signal CLA. That is, the high level ATD control signal CLA is output. At this time, the SRAM 106 returns to the internal synchronization state.

FIG. 12 is a circuit diagram showing the ATD control signal holding circuit 202 shown in FIG. In FIG. 12, A
The TD control signal holding circuit 202 includes inverters 283 and 284 and NMOS transistors 291 to 296.
And PMOS transistors 297 and 298 and a capacitor 299.

The ATD control signal holding circuit 202 operates as follows. Inverter 284 provides a high level signal to the gates of transistors 292 and 296 when low level hold signal HD is provided. Therefore, the transistors 292 and 296 are turned on. In addition to this,
When the low level ATD control signal CLA ′ is given through the terminal 200, the inverter 283 gives a high level signal to the gate of the transistor 295. Therefore,
The output node N2 of the latch circuit 265 formed by the transistors 293, 294, 297 and 298 is forcibly pulled down. Therefore, the transistor 29
Since 7 and 294 are turned on, the latch circuit 265 outputs the low level ATD control signal CLA via the node N2.

On the other hand, during the period when the low level holding signal HD is applied, the high level ATD control signal CL
When A'is given, the transistor 291 turns on,
The transistor 295 is turned off. Therefore, the node N1 of the latch circuit 265 is connected to the transistors 291 and 292.
Is forced to pull down, turning on transistors 298 and 293. As a result, high level A
The TD control signal CLA is output via the node N2.

When the high-level holding signal HD is applied, the transistors 292 and 296 are turned off. Therefore, since the holding state of the ATD control signal in the latch circuit 265 is maintained, the level of the ATD control signal CLA output from the ATD control signal holding circuit 202 is maintained.

ATD control signal holding circuit 2 shown in FIG.
The internal synchronization is released during the period in which 02 outputs the low level ATD control signal CLA. On the other hand, during the period in which the high level ATD control signal CLA is output,
Performs internal synchronization operation.

When performing a normal internal synchronization operation, the ATD control signal holding circuit 202 must always output the high level ATD control signal CLA. Therefore, the power supply voltage V
When the supply of cc is started, the threshold voltages of the transistors 291 to 293 are set to the threshold voltages of the transistors 291 to 293 so that the ATD control signal holding circuit 202 automatically outputs the high level ATD control signal CLA. It is designed to be lower than the threshold voltage. As a result, the ATD control signal holding circuit 202
Even if the holding signal HD is not supplied, the ATD control signal CLA of high level can be always output after the power supply voltage Vcc is supplied. Therefore, the SRAM 106 is
After the power supply voltage Vcc is supplied, it is always ready to operate in the normal operation mode.

With such a configuration, it becomes possible to switch the internal synchronization method even if there are no empty pins.
If the D control input CLA is set to a high level, the same operation as in the conventional internal synchronization system is performed. If the ATD control input CLA is set to a low level, the internal synchronization system does not operate.
It can be operated independently of TD.

As a result, since the number of circuits to be operated does not increase, current consumption does not increase during high speed operation.
Further, since there is no problem in the operation timing, it is possible to confirm whether the cause of the SRAM 106 defect is the memory cell or the circuit defect.

Example 5. In the above-described first to third embodiments, the case where there is an empty pin (external terminal) in advance has been described. However, providing a pad for inputting the ATD control input CLA on the wafer will bring a sufficient effect. The internal synchronization should be switched only when testing in the wafer state, and in the initial evaluation of the memory cell, the internal synchronization should be turned off, and then encapsulated in a package and fixed to a high level when shipped as a product. Therefore, always use the internal synchronization method.

As a result, no problem occurs in the operation timing, and it is possible to confirm whether the cause of this SRAM defect is the memory cell or the circuit defect.

Example 6. The configuration of the sixth embodiment of the present invention will be described with reference to FIGS. 13, 14 and 15. FIG. 13 is a block diagram showing a sixth embodiment of the present invention. 14 is a block diagram showing a clock generator according to the sixth embodiment of the present invention. Furthermore, FIG.
FIG. 9 is a circuit diagram showing an ATD of Embodiment 6 of the present invention.

In FIG. 13, this SRAM 101 is
A pulse is generated corresponding to changes in the burn-in mode control input BM, the test mode control input TM, the row address buffer 51, the column address buffer 52, the block address buffer 53, and the data input buffer 55, and the row decoder 6 is generated by the pulse. , to the sense amplifier 4 ₁ defines the activation time of 4 _n and the data holding circuit 57, a clock generator 5 which burn mode it does not generate a pulse
Including 8B. SR except clock generator 58B
Another circuit configuration of AM101 is the conventional S shown in FIG.
The description is omitted because it is the same as the RAM 103.

FIG. 14 is a block diagram showing a structure of clock generator 58B shown in FIG. 14, the output of the OR gate 62, the output of the OR gate 63, the pulse of the pulse generation circuit 61 and the write control input WE1 are received, and the pulse ATD0 for activating the row decoder 6 and the sense amplifiers 4 ₁ to 4 _{n are received.} Pulse ATD1 for activating the data holding circuit 57 and the pulse RDL for activating the data holding circuit 57 are generated, and no pulse is generated in the burn-in mode and the test mode.
It includes a TD (address change detection circuit) 64B. ATD6
The circuit configuration of the clock generator 58B other than 4B is the same as that of the clock generator 5 of the first embodiment shown in FIG.
The description is omitted because it is similar to 8A.

FIG. 15 is a circuit diagram of the ATD 64B shown in FIG. In FIG. 15, a pulse SAT is applied to the gate.
A PMOS transistor 400 to which D1 is input,
The PMOS transistor 401 whose gate receives the pulse SATD2, the inverter 406 which receives the test mode control input TM, and the gate of the inverter 4
06 output signal is input to the PMOS transistor 402, a gate to which the pulse SATD1 is input to the NMOS transistor 403, and a gate to which the pulse SAT is input.
An NMOS transistor 404 to which D2 is input,
The NMOS transistor 405 having the gate to which the output signal of the inverter 406 is input, and the gate to the inverter 4
And an NMOS transistor 407 to which the output signal of 06 is input. Delay circuit (RD: Rise Delay) 71
Is input to the PMOS transistors 401 and 40
2, the sources of NMOS transistors 403 and 404 are connected.

Further, the ATD 64B has an inverter 408 to which the test mode control input TM is input and a PMO to which the test mode control input TM is input to the gate.
An S transistor 409 and an NMOS transistor 410 whose gate receives the output signal of the inverter 408.
An NMOS transistor 411 whose gate receives the test mode control input TM, a PMOS transistor 412 whose gate receives the output signal of the inverter 408, and an inverter 413 which receives WE1.
Including and The PMOS transistor 409 and the NMOS transistor 410 are inserted between the inverter 76 and the gate of the NMOS transistor 81, and the NMOS transistor 411 and the PMOS transistor 412 are connected to the inverter 4.
13 and the gate of the NMOS transistor 81. The other circuit configuration of the ATD 64B is similar to that of the ATD 64A of the first embodiment shown in FIG.

Next, the operation of the sixth embodiment of the present invention will be described. When the test mode control input TM is low level, the output of the inverter 406 is high level, so that the transistor 402 is turned off and the transistors 407 and 408 are turned on. Therefore, the transistors 400, 401, and
402, 403, 404, 405 and 407 operate as NOR gates to which the pulses SATD1 and SATD2 are input. Further, since the output of the inverter 408 becomes high level, the transistors 409 and 410 are turned off and the transistors 411 and 412 are turned on.
The same operation as that in which the signal F is directly connected to the gate of the transistor 81 is performed. Therefore, it operates similarly to the conventional ATD64.

Further, when the burn-in mode control input BM is at a low level, a high level is given through the inverter 95, so that the NAND gate 94 outputs a signal corresponding to the pulse DTD, and operates similarly to the conventional ATD64. do.

When the test mode control input TM is at the high level, the output of the inverter 406 is at the low level, the transistor 402 is turned on and the transistors 407 and 408 are turned off, so that the signal A is always fixed at the high level. It As a result, the signals B, C, D and E are always fixed at the high level and the signal H is fixed at the low level. Further, since the output of the inverter 408 becomes low level, the transistor 40
9 and 410 turn on and transistors 411 and 4
Since 12 is turned off, the signal F of the inverter 76 is directly connected to the gate of the transistor 81.

At the time of reading, that is, when WE1 is at low level, the node N ₂ is at low level, the node N ₁ is at high level, and the signal G is at low level. Therefore, the transistor 86 is turned on and the transistor 91 is turned off. Further, since the signal H is fixed at the low level, the transistor 87 is turned on and the transistor 89 is turned off. As a result, the node N ₃ goes high.

When the node N ₃ is at the high level, the output of the NOR gate 92A is at the low level, and the output ATD0 of the inverter 93 is always at the high level. Since the input signals B and E of the NAND gate 84 and the signal of the node N ₁ are all at the high level, the output of the NAND gate 84 is at the low level and the output ATD1 of the inverter 85 is always at the high level. Further, since the input signals C and E of the NAND gate 82 and the signal of the node N ₁ are all at high level, the output of the NAND gate 82 becomes low level,
The output RDL of the inverter 83 is always high level.

At the time of writing, that is, when WE1 is at a high level, the signal at the node N ₂ is at a high level, the signal at the node N ₁ is at a low level, and the signal G is at a high level. Therefore, the transistor 86 is turned off and the transistor 91 is turned on. As a result, the signal at node N ₃ goes low.

If the signal at node N ₃ is low, then N
The output of the OR gate 92A becomes low level. When the burn-in mode control input BM is at a low level, a high level is given to the NAND gate 94 through the inverter 95.
The NAND gate 94 outputs a signal in response to the pulse DTD, and the NOR gate 92A further includes the NAND gate 94A.
The signal is output corresponding to the output of. Further, RDL and ATD1 are always at a low level, and the same operation as that of the conventional ATD64 is performed.

When the test mode function is activated, the clock generator used to save current consumption during normal use is inactivated, so that the timing of reading does not shift, and it is possible to detect a defect to be originally detected. Become.

When the burn-in mode control input BM is at high level, the same operation as the ATD 64A in FIG. 2 is performed.

Therefore, the burn-in mode control input BM
Is set to a high level, the word line that is always selected is in an activated state, and stress can be continuously applied to the memory cell. As a result, it is possible to shorten the time for applying stress in the burn-in mode.

In the first and sixth embodiments described above, the case where the test mode control input TM and the burn-in mode control input BM are directly input to the clock generators 58A and 58B has been described. , The same effect can be obtained even if the clock generator is inactivated. Further, the same effect can be obtained by applying a signal from an unnecessary address terminal to the clock generator through the high voltage detection circuit in the test mode or the burn-in mode.

In each of the embodiments, the case where the semiconductor memory device is used in the static type semiconductor memory device has been described, but the same effect can be obtained when used in another semiconductor memory device having a clock generator.

[0116]

As described above, the semiconductor memory device according to the first aspect of the present invention normally generates a pulse in response to a change in address, activates a specific circuit as necessary, and outputs a control signal. Since it has a clock generator that constantly activates a circuit that is activated only for a certain period of time based on the input of, the internal synchronization system can be turned off, and the current consumption can be reduced and the cause of SRAM failure can be easily found. There is an effect that can be done.

As described above, the semiconductor memory device according to the second aspect of the present invention normally generates a pulse in response to a change in the address buffer or the data input buffer to generate a row decoder, a sense amplifier and a data holding circuit. Since the clock generator that activates the pulse generator and that does not generate the pulse in the burn-in mode is provided, by deactivating the pulse operation in the write operation, the effective time of stressing the memory cell in the burn-in mode can be shortened, which in turn causes a defect. It is possible to increase the detection efficiency and shorten the construction period.

As described above, the semiconductor memory device according to the third aspect of the present invention normally generates a pulse corresponding to a change in the address buffer or the data input buffer to generate a row decoder, a sense amplifier and a data holding circuit. Since it has a clock generator that activates, and does not generate the pulse in the test mode, the timing is shifted due to the clock generator used to save current consumption during normal use when the test mode function is activated,
This has an effect of solving the problem that a defect to be originally detected cannot be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a clock generator according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an ATD (address change detection circuit) of the clock generator according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a clock generator according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an ATD of the clock generator according to the second embodiment of the present invention.

FIG. 7 is a block diagram showing a third embodiment of the present invention.

FIG. 8 is a block diagram showing a clock generator according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a pulse detection circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart showing the operation of the pulse detection circuit according to the fourth embodiment of the present invention.

FIG. 12 is a circuit diagram showing an ATD control signal holding circuit according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram showing a sixth embodiment of the present invention.

FIG. 14 is a block diagram showing a clock generator according to a sixth embodiment of the present invention.

FIG. 15 is a circuit diagram showing an ATD of a clock generator according to a sixth embodiment of the present invention.

FIG. 16 is a block diagram showing a conventional SRAM.

FIG. 17 is a circuit diagram showing a peripheral circuit of a conventional SRAM memory cell array.

FIG. 18 is a circuit diagram showing a memory cell of a conventional SRAM.

FIG. 19 is a circuit diagram showing another memory cell of the conventional SRAM.

FIG. 20 is a block diagram showing a conventional SRAM clock generator.

FIG. 21: A of a conventional SRAM clock generator
It is a circuit diagram which shows TD.

FIG. 22 A of a conventional SRAM clock generator
6 is a timing chart showing the operation of TD.

FIG. 23 is a timing chart showing a pulse generated in a read operation of a memory cell of a conventional SRAM and ATD.

FIG. 24 is a block diagram showing another conventional SRAM.

[Explanation of symbols]

1 ₁ -1 _n memory cell array 3 ₁ -3 _n write buffer 2 ₁ -2 _n multiplexer 4 ₁ -4 _n sense amplifier 5 match detection circuit 6 row decoder 7 column decoder 8 block selector 51 row address buffer 52 column address buffer 53 block Address buffer 54 Read / write control circuit 55 Data input buffer 56 Data output buffer 57 Data holding circuit 58A, 58B, 58C, 58D Clock generator 64A, 64B, 64C ATD (address change detection circuit) 100, 101, 104, 105, 106 SRAM 201 pulse detection circuit 202 ATD control signal holding circuit

Claims (3)

[Claims] 1. Normally, a pulse is generated in response to a change in address, a specific circuit is activated as needed, and a circuit which is activated only for a certain period based on the input of a control signal is always activated. A semiconductor memory device comprising a clock generator for controlling the semiconductor memory device. 2. A clock generator that generates a pulse in response to a change in an address buffer or a data input buffer in a normal time to activate a row decoder, a sense amplifier and a data holding circuit, and does not generate the pulse in a burn-in mode. A semiconductor memory device provided with. 3. A clock generator which normally generates a pulse in response to a change in an address buffer or a data input buffer to activate a row decoder, a sense amplifier and a data holding circuit, and which does not generate the pulse in a test mode. A semiconductor memory device provided with.