JPH06259903A - Reliability detection circuit for seek control - Google Patents

Abstract

PURPOSE:To save data and to prevent the generation of damages by recording a seek control condition in the device and judging the possibility of the damage generation. CONSTITUTION:The movement of a head 1 from the center of an objective track over a specified range is detected by a position error detecting means 2. The reaching of the head 1 to the target track is decided by a deciding means 3 using a track loss signal. The target track is instructed to the means 3 and based on the notification of reaching the objective track sent by the means 3, the detection result of the means 2 is monitored by a controlling means 4. Then, after reaching the objective track everytime seeking is carried out, the number of seek controls at the time of the head 1 moved from the center of the objective track over the specified range and the total number of seek controls are stored in a nonvolatile storage means 5. Thus, the number of seek controls in an abnormal condition against the total number of seek controls is read out of the means 5, the possibility of the damage generation is identified and the damages are prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a seek control circuit for controlling the positioning of a head based on servo information read by the head, and in particular, stores data indicating a change in the control state due to a change with time of a mechanical section and circuit elements. However, the present invention relates to a seek control reliability detection circuit capable of preventing a failure from occurring by referring to this data.

In recent years, in magnetic disk devices, the recording density in the radial direction of the disk, that is, the number of tracks has been increasing more and more because the capacity has been increased and the size has been reduced.

Therefore, in seek control, precise and accurate control is required, but the control state may become unstable due to a slight change in the circuit element or mechanism. In such a case, the head cannot be positioned on the target track even by the retry operation, and the data may not be read.

As described above, when data cannot be read, the larger the capacity of the magnetic disk device, the greater the damage. In order to avoid such a situation, it is necessary to check the seek control state of the magnetic disk device in advance and, if the control is unstable, move the data to another storage device.

Therefore, it is desirable to be able to check the reliability of seek control.

[0006]

2. Description of the Related Art In a conventional magnetic disk device, since the recording density in the radial direction of the disk is low and the positioning speed of the head is slow, even if the values of the mechanical section and the circuit elements are changed to some extent, the seek control is reliable. It had little effect on sex.

That is, in the mechanism section, for example, there is a change in the magnetic force of a magnet used in a motor, a change in the bearing tightness, and the like, and in a circuit element, there are mainly changes in the characteristics of a semiconductor element. Even if a device abnormality was reported, the cause was easily found because the degree of change was large.

Therefore, conventionally, as a type of device abnormality, it has only a function of reporting a seek error and a function of recording a history of seek errors.

[0009]

As described above, in the past, since the seek error is reported and the history thereof is only recorded, even if the seek control state changes gradually within the device, it is It is impossible to detect, and unless a certain amount of change is accumulated, the change is not superficially reported until a seek error occurs.

After the seek error is reported,
Since the device does not operate normally, it becomes impossible to save the data stored in the disk. In addition, even when investigating the cause of the abnormality, the higher the recording density in the radial direction of the disk, the smaller the amount of change in the mechanical control unit and the circuit element of the seek control system, and the more factors that influence the seek control state. , There is a problem that the investigation becomes difficult because they interact with each other.

In view of such a problem, the present invention records the seek control state in the apparatus so that the possibility of occurrence of a failure can be judged and data can be saved and the occurrence of the failure can be prevented. The purpose is to be able to prevent.

At the same time, when a failure occurs, the purpose is to provide a history of the seek control status up to that point and facilitate the cause investigation.

[0013]

FIG. 1 is a block diagram for explaining the principle of the present invention. The seek control circuit is head 1
A position signal indicating the position of the head 1 and a track cross signal indicating that the head 1 has crossed a track are created based on the servo information read by the head 1. From this position signal and the track cross signal, the head 1 is detected. The position error of the head 1 is detected and the positioning control of the head 1 is performed.

The position error detecting means 2 for detecting that the head 1 has moved beyond the predetermined range from the center of the target track by the position signal, and the head 1
Has arrived at the target track from the track cross signal, and the determination means 3 is instructed to the target track, and the determination means 3 sends the target track arrival notification of the head 1. Based on
The control means 4 is provided for monitoring the detection result of the position error detection means 2 and recording it in the non-volatile storage means 5.

Each time the seek control is performed, the detection result of the position error detecting means 2 is monitored, and after the head 1 reaches the target track, a predetermined range from the center of the target track is monitored. The number of seek controls when moving over and the total number of seek controls are recorded in the non-volatile storage means 5.

[0016]

With the above-described configuration, the number of seek control operations that have been in an abnormal state relative to the total number of seek control operations can be read from the non-volatile storage means 5, so the state of change in the seek control frequency in an abnormal state can be read. By predicting the occurrence of a failure corresponding to the above, it is possible to save the data and prevent the occurrence of the failure in advance.

By obtaining the seek state history, the cause investigation can be facilitated.

[0018]

2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of FIG.

The processor 8 operates by reading the program stored in the ROM 6, and when a target track for positioning the head 1 is designated together with a seek command from a host device (not shown), the head is sent to the counter 14 via the register 9. Set the distance traveled by 4 in number of tracks.

When the processor 8 drives the motor through a motor driving circuit (not shown) to move the head 1, the head 1 reads the servo information of the disk and demodulates the circuit 13.
Send to.

The demodulation circuit 13 creates a position signal and a track cross signal from the servo information read by the head 1, and outputs the position signal to the minus terminal of the comparator 11 and the plus signal of the comparator 12.
Send to the terminal.

This position signal has a waveform as shown in the position signal of FIG. 3, and when the head 1 is following the track, the voltage of the position signal is near 0, but the head 1 moves to the disk. When it moves to the inner circumference side, for example, a position signal in which the positive voltage value sequentially increases in proportion to the amount of movement is transmitted.

Then, when the position of the head 1 passes near the midpoint between the adjacent tracks, the voltage polarity of the position signal is inverted, and a voltage having a high negative polarity is sent out.
Voltage decreases with the movement of the track No., and when the voltage further moves across the adjacent track, the voltage becomes positive again. Therefore,
This amplitude represents one track width.

FIG. 3A shows a state in which the head 1 has moved by two tracks, and such a position signal is supplied to the comparators 11 and 12 as described above. The comparator 11 divides the + 12V power source by the resistors R1 and R2 to obtain a comparison voltage + R.
The EFV is compared with this position signal, and the comparator 12 outputs -1.
A comparison voltage -REFV obtained by dividing the 2V power source by the resistors R3 and R4 is compared with this position signal, and FIG.
The on-track signal as shown in the on-track signal of FIG.

That is, the voltage of the position signal is + REFV and -R.
If the voltage is between EFV, set the logic "1" to register 9
And if it is outside the range of + REFV and -REFV,
The logic “0” is sent to the register 9.

The counter 14 subtracts the number of tracks set by the processor 8 one by one in response to a pulse-shaped track cross signal sent by the demodulation circuit 13 each time the head 1 crosses a track, and the count value becomes 0. Then, Fig. 3
As shown in the target track signal of (A), a logic "1" is sent to the register 9.

The processor 8 monitors the logical value of the register 9, and when the count value of the counter 14 becomes 0, it is judged that the head 1 is positioned on the target track, and then the logical value of the on-track signal is "1". Then, the internal timer is started to monitor the change in the logical value of the on-track signal for a certain period of time.

When the position control of the head 1 is executed normally, the voltage of the position signal is + REFV as shown in FIG. 3 (A).
After the target track signal rises, the on-track signal once rises and remains at the logic "1" and does not change.

When the processor 8 recognizes this state, E
Only the number of seeks is updated and recorded in the EPROM 7. If the position control of the head 1 is bad,
As shown in (B), after the head 1 overruns and the target track signal rises, the on-track signal once rises and falls to the logic "0" as shown by.

When the processor 8 detects this state,
The number of defective seeks and the number of seeks are both updated and recorded in the EEPROM 7. FIG. 4 is a diagram for explaining a data recording state.

The EEPROM 7 records the total number of seeks and the number of seek failures that occur during the number of seeks. For example, when the total number of seeks recorded in the area shown in (a) reaches 10,000. , The address is updated, and the total number of seeks and the number of seek failures that occurred during the seeks are recorded in the area shown in (b) below.

When such recording is executed and the area shown in (n) is recorded, the processor 8 overwrites the area shown in (a) and sequentially updates old data to new data.

Therefore, for example, if n is 30, the EEPROM 7 records data showing the transition of the number of seek defect occurrences every 10,000 times with respect to the seek control of 300,000 times. .

Processor 8 registers 9 if instructed.
After that, this data is displayed on the display device 10. Incidentally, the processor 8 simultaneously displays the recording address of the latest data in order to indicate up to which area of the EEPROM 7 the old data has been updated by the overwrite.

FIG. 5 is a flow chart for explaining the operation of FIG. The processor 8 monitors the reception of the seek command in step (1), and when receiving the seek command, sets the movement distance of the head in the counter 14 in the number of tracks in step (2). Then, in step (3), it waits until the count value of the counter 14 becomes 0, and in step (4), it is checked whether the on-track signal has become logical "1".

When the on-track signal becomes logic "1" in step (4), the processor 8 starts the timer in step (5) and checks whether the on-track signal becomes logic "0" in step (6). .

When the on-track signal becomes logical "0" in step (6), the processor 8 proceeds to EEPR in step (7).
If 1 is added to the count value of the number of seek failures recorded in the OM7 and written in the EEPROM 7, and if the on-track signal does not become the logic "0" in step (6), step
Check whether a certain time has passed in (8) by referring to the timer started in step (5).

The processor 8 returns to the process of step (6) if the predetermined time has not elapsed in step (8), and if the predetermined time has elapsed, the processor 8 executes the EEPROM in step (9).
1 is added to the count value of the number of seeks recorded in 7, the data is written in the EEPROM 7, and the timer is stopped.

Then, in step (10), it is checked whether the total number of seeks has reached a certain number, and if not, step
Return to the process of (1), and if reached, EE in step (11)
After setting a new write address of the PROM 7, the process returns to the step (1).

[0040]

As described above, according to the present invention, since it is possible to record and display the number of seek control operations that were in an abnormal state relative to the total seek control number in the non-volatile storage means 5, the abnormal state can be displayed. It is possible to save data according to the number of seek control operations, predict a failure occurrence, and prevent the failure occurrence in advance.

Since the seek state history is obtained, the cause investigation is facilitated, so that the reliability of the seek control circuit can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating the operation of FIG.

FIG. 4 is a diagram for explaining a data recording state.

5 is a flowchart illustrating the operation of FIG.

[Explanation of symbols]

 1 Head 2 Position Error Detection Means 3 Judgment Means 4 Control Means 5 Nonvolatile Storage Means 6 ROM 7 EEPROM 8 Processor 9 Register 10 Display Device 11, 12 Comparator 13 Demodulation Circuit 14 Counter

Claims (1)

[Claims] 1. A position signal indicating the position of the head (1) based on servo information read by the head (1) and the head (1).
A track cross signal indicating that (1) has crossed a track is created, and a position error of the head (1) is detected from the position signal and the track cross signal, and the head (1) is detected.
In the seek control circuit for performing the positioning control of (1), position error detection means (2) for detecting that the head (1) has moved beyond a predetermined range from the center of the target track, and the head (1) ) Has arrived at the target track based on the track crossing signal, and the head for sending out the target track to the determination means (3) while instructing the target track to the determination means (3). Based on the target track arrival notification of (1), a control means (4) for monitoring the detection result of the position error detection means (2) and recording it in the nonvolatile storage means (5) is provided, and the seek control is performed. Each time it is performed, the detection result of the position error detection means (2) is monitored, and when the head (1) moves beyond the predetermined range from the center of the target track after reaching the target track. The number of seek control of A seek control reliability detection circuit characterized by recording the total number of seek controls.