JPH06259574A - Graphic rendering system - Google Patents

Abstract

PURPOSE:To accelerate plotting processing by performing the parallel processing of a header part and a feature point data part which comprises graphic element data. CONSTITUTION:This system is comprised in such a way that a CPU 1 stores the header part 12 set as a plotting processing target by transferring to shared memory 8 sequentially by using the graphic element data 11 consisting of the header part 12 which represents the specification of a graphic element and the feature point data part 13 provided with the coordinate value, shading, and color, etc., of the feature point of the graphic element and data 17 for linkage. and also, notifies an execution command for each of them to a rendering processor 6 via a communication control part 7, and also, a DMA controller 5 receiving the data 17 for linkage in the shared memory 8 DMA-transfers the feature point data part 13 specified by the data to a FIFO buffer 4, respectively by the operation of the communication control part 7, and the header part 12 in the shared memory 8 and the feature point data part 13 in the buffer 4 can be loaded on the rendering processor in a form of parallel processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic rendering system, and more particularly to the format of graphic element data for individually expressing each graphic element forming an arbitrary graphic, such as the type of the graphic element and display conditions. A header part showing the overall attributes,
A data format including a feature point data section indicating individual attributes such as coordinate values, shadows, colors, etc. of feature points of the graphic element is used, and a rendering processor draws based on the graphic element data transferred from the main storage device. The present invention relates to a graphic rendering method in which the graphic is stereoscopically displayed by performing processing.

In recent years, in the field of computer graphics for performing graphic processing using a computer, not only is a flat figure generated by simply combining various graphic elements such as polygonal lines, basic polygons and arcs generated and displayed, By performing a rendering process based on the graphic element data to hide invisible lines and surfaces of the display object, and by adding light and shadow to the display object in consideration of the position of the line of sight and the light source,
BACKGROUND ART Displaying a three-dimensional realistic image on a display is performed.

This graphics processing tends to be used not only in industrial fields such as design of automobiles, buildings and clothes, but also in a wide range of fields such as medical care, art and education. There is a demand for the construction of a system that realizes a high-speed and high-performance image processing algorithm by pipeline processing of data, and the present invention meets such a demand.

[0004]

2. Description of the Related Art Generally, a drawing object figure in computer graphics processing is expressed by combining various figure elements such as broken lines and polygonal rows as shown in FIG.
The format of the graphic element data at this time is as follows: the header section showing the overall attributes such as the type of the graphic element and the overall drawing processing conditions (reflection condition, transparent condition, etc.), and the coordinates of each feature point of this graphic element. A data format is used that includes a feature point data section that indicates individual attributes such as values, shades, and colors.

FIG. 9 shows an outline of a conventional graphic rendering system. 61 is a CPU, 62 is a main storage device for storing various commands and graphic element data necessary for drawing processing, and 63.
Is a system bus, 64 is a communication control unit that sends and receives a start command and an end command to and from the CPU 61, 65 is a FIFO buffer to which graphic element data to be rendered is input from the main memory 62, and 66 is A rendering processor, 67 is a ROM / RAM for storing application programs and processing results of the rendering processor 66, 68 is an image memory, and 69 is a display device.

Here, the CPU 61 sets a window for specifying the drawing range on the display device 69, sends a start command to the communication control unit 64, and sets the drawing element data to be drawn in the execution order. Therefore F
It is stored in the IFO buffer 65.

The rendering processor 66 activated by the communication control unit 64 executes the drawing processing in the window based on the graphic element data fetched from the FIFO buffer 65, and the result is the image memory 68. Stored in. The communication control unit 64 notifies the CPU 61 of the completion of the processing in the rendering processor 66 and the forced termination.

The control when the graphic element data is input from the main memory device 62 to the rendering processor 66 via the FIFO buffer 65 is controlled by the CPU 61 or DMA.
A method or the like used by a controller (not shown) is used.

[0009]

As described above, according to the conventional graphic rendering method, the header portion and the feature point data portion of the graphic element to be rendered are processed as a single data group via the FIFO buffer 65. In this input process, the CPU 61 does not recognize the next rendering process target header part (following the feature point data part whose final data address is not visible). Can not.

Therefore, even when the CPU 61 uses the DMA controller to shorten the time constrained by the input processing, only one graphic element data is subject to the DMA, and the CPU 61 or the rendering processor 66 can D for the next drawing processing target graphic element data
When the MA is activated, it is necessary to synchronize with the drawing process being executed.

Therefore, there is a problem in that the processing of the header portion and the characteristic point data portion in the rendering processor 66 cannot be pipelined, and the high speed and high performance of the entire system cannot be realized.

Therefore, according to the present invention, the header part and the feature point data part of each graphic element data can be handled as independent data, and the header part and the feature point data part are processed in parallel in the rendering processor. By doing so, it is intended to speed up the drawing process.

[0013]

According to the present invention, graphic element data in a form in which link data such as a start address of a feature point data portion and a data word length is set in a part of a header portion is stored in a main storage device. On the rendering processor side, first, the header parts of a plurality of graphic elements are collectively fetched from the main storage device, and then the DM of the corresponding feature point data part is obtained based on the link data of each of the header parts.
The A transfer is sequentially executed.

FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a CPU, 2 is a main memory device, 3 is a system bus, 4 is a FIFO buffer, 5 is a DMA controller,
6 is a rendering processor, 7 is a communication controller, 8 is a shared memory, and 9 is an image memory.

Here, the graphic element data 11 stored in the main storage device 2 has a header portion similar to the conventional example shown in FIG.
12 and the feature point data section 13, the former fixed-length area 14 is set with data indicating the overall attributes such as the type of graphic element, the overall drawing processing conditions (reflection condition, transparent condition, etc.), and the latter. The segment data 18 consisting of coordinates for each characteristic point of the graphic element, a normal vector designating individual attributes such as shading and color at that point, and color data is set.

The difference from the conventional graphic element data is that a part of the header part 12 has a DMA start address 15 indicating the start position of the feature point data part 13 and a data word length 16 indicating the word length of the segment data 18. That is, the link data 17 consisting of and has been set. The SOD is connected to the next segment data 18, and the EO is recorded at the end of the feature point data section 13.
D is set respectively

[0017]

As described above, according to the present invention, the main storage device is formed in such a manner that the header portion 12 and the feature point data portion 13 forming the graphic element data 11 can be connected by the link data 17 provided in a part of the former. In the drawing processing based on the graphic element data 11, the header section 12 is input to the shared memory 8 and the feature point data section 13 is input to the FIFO buffer 4.

Then, the rendering processor 6 uses C
Based on the activation command sent from the PU 1 to the communication control unit 7, the header unit 12 is sequentially fetched from the shared memory 8 and the drawing process of each graphic element is started.

Further, the communication control section 7 takes out the link data 17 (DMA head address 15) of the header section 12 stored in the shared memory 8 and sends it to the DMA controller 5, and the DMA controller 5 which received it receives the data. The feature point data unit 13 in the address area specified by the DMA start address 15 is sequentially taken out from the main storage device 2 and input to the FIFO buffer 4, and this output data is supplied to the rendering processor 6.

Therefore, the header section 12 and the feature point data section 13 for a plurality of graphic elements are respectively provided in the shared memory 8.
And the FIFO buffer 4 are stored in a discriminated form, and the rendering processor 6 can execute parallel processing on both data.

Further, the CPU 1, after sending an instruction to start the rendering process to the rendering processor 6 to the communication control unit 7, performs a release process until the rendering process for the header unit 12 stored in the shared memory 8 is completed. It will be possible.

[0022]

Embodiments of the present invention will be described with reference to FIGS. FIG. 2 is an explanatory diagram showing an outline of the graphic rendering system of the present invention. In FIG. 2, a selector 21 for outputting either DMA transfer data or an interrupt bit which will be described later and a feature point data section 13 are shown in FIG. The SOD and EOD are detected and the output signal thereof is used to select the selector 21 and the DMA controller 5.
The configuration is such that an EOD / SOD determination unit 22 for controlling the operation of and the data counter 23 for checking the word length of the segment data 18 are added.

Here, the communication control unit 7 is about to execute the DMA
The data word length 16 of the transferred feature point data portion 13 is taken out from the shared memory 8 and set in the data counter 23.

The data counter 23 is the main memory 2
The word length of the segment data 18 DMA-transferred from is counted, and when the value matches the previous set value, an output signal to that effect is sent to the EOD / SOD determination section 22, and then the EOD / SOD determination section. 22 determines whether the next DMA transfer data is SOD or EOD.

The output signal of the EOD / SOD determination unit 22 when the SOD or EOD is detected controls the selector 21 and the DMA controller 5 as described later. Based on this, the DMA controller 5 starts the next DMA transfer process.

The communication control section 7 executes processing sequence control, preceding DMA control, interrupt handler control, etc., which will be described later, based on a start instruction from the CPU 1, and the shared memory 8 has a rendering processor in addition to the header section 12 in addition to the header section 12. The application program 6 is stored, and a work area, a ZBuffer indicating depth information when viewed from a viewpoint, a work area, and the like are set.

Next, FIG. 3 is an explanatory view showing the multiple buffering and pipelining of the header part.
In addition to the FIFO buffer 4 and the rendering processor 6, a FIFO port 31, status register 32, decoder 33, internal status register 34, command register 35, AND circuit 36, counter 37, current pointer
38 and the command buffer 39 are used. The status register 32 to the current pointer 38 are components of the communication controller 7, and the command buffer 39 is a component of the shared memory 8.

The command buffer 39 is an n + 1 fixed size area set in the communication area of the shared memory 8,
Header areas 12 including link data 17 in each of the graphic element data 11 are stored in the individual areas identifiable by the numbers n to n in the drawing processing order.

The loading (PUT) of each header portion 12 into the command buffer 39 and the pickup of the header portion into the rendering processor 6 are executed according to the rotation queue method described later.

Here, the CPU 1 instructs the processing for the header part 12 of the area number x by writing "1" to the EXECx bit corresponding to the area number x of the command buffer 39 among the respective bits of the command register 35. is doing.

Further, the rendering processor 6 stores the header stored in the area number x of the command buffer 39 based on the output signal of the AND circuit 36 (the AND output of the value'x 'of the current pointer 38 and the EXECx bit). The part 12 is read, and the feature point data part 13 corresponding to the header part 12 is received from the FIFO port 31 to execute a predetermined drawing process. The FIFO buffer 4 has a feature point data section 13 corresponding to each header section 12
DMA transfer has been performed (see FIG. 4).

After the drawing process is completed, the completion status is set in the internal status register 34, the current pointer 38 is automatically incremented, and the process for the next header section 12 is started.

Along with the setting of the end status, "1" is written in the corresponding ENDx bit of the status register 32, and in association with this writing process, the corresponding EXECx bit of the command register 35 is "1". Will be cleared to '0'.

Next, FIG. 4 is an explanatory diagram showing the concept of the DMA transfer logic. The command register 35, the command buffer 39, the DMA controller 5, and the EOD / SOD determination section.
22, outside the data counter 23 and the FIFO buffer 4,
An event input control circuit 41, a DMA event queue 42 and an address counter 43 are used. The DMA event queue 42 is virtual.

Here, the event input starting process is executed as "1" is written in the EXEC _n bit of the command register 35 by the write access from the CPU 1.
For example, when "1" is written to both the EXEC ₂ bit and the EXEC ₃ bit, the No. 2 area and No.
The DMA transfer processing for the feature point data section 13 corresponding to each of the header sections 12 stored in the three areas is started.

That is, the event input control circuit 41 obtains the start address (in the command buffer 39) of the portion where each DMA start address 15 of the No. 2 area and No. 3 area is stored by the calculation formula shown, Based on this head address, the event data (DMA head address 15 and data word length 16) of each of No. 2 area and No. 3 area is extracted and stored in the corresponding queue area of the DMA event queue 42. In the above calculation formula, the DMA start address 15
And the data word length 16 are both 4 bytes.

The event data stored in the DMA event queue 42 is sent to the address counter 43 and the data counter 23 from the smaller area number n. The data counter 23 creates a timing signal S ₁ for detecting the SOD / EOD of the feature point data unit 13 transferred by DMA based on the data word length 16 in the event data. With function.

Therefore, the DMA controller 35 first receives the event data (the DMA head address 15 and the data word length 16) in the No. 2 queue area and starts the DMA processing for the main storage device 2. The feature point data section 13 specified by the data is the FIFO buffer 4, the data counter 23 and the EOD / SOD determination section in order.
Entered in each of the 22.

The data counter 23 receives data from the main memory 2 through D.
Data word length of segment data 18 transferred by MA 16
Has already been received from the DMA event queue 42,
When the segment data 18 of this length is counted, the timing signal S ₁ is output.

Further, the EOD / SOD judging section 22 determines that the transfer data specified by the timing signal S ₁ is EO.
If it is "YES" by judging whether or not it is D, that is, if it is recognized that all of the feature point data section 13 corresponding to the No. 2 area of the command buffer 39 is stored in the FIFO buffer 4, the DMA controller is once 5 is stopped and the processing for the event data of the next No. 3 queue area is instructed.

A Valid bit is prepared in each queue area of the DMA event queue 42, and the event data
The valid bit of the area storing the data (DMA head address 15 and data word length 16) is set to "1". Further, for convenience of explanation, it is assumed that the DMA processing for the No1 queue area is completed.

Next, FIGS. 5 and 6 are explanatory views showing the processing procedure in the CPU, the communication control unit and the rendering processor. That is, the processing procedure in the CPU 1 is such that a command buffer having an area from "0" to "n" is provided for an arbitrary number of header parts 12 (commands) according to the execution order.
Sequentially store in 39 and proceed to the next step. Of the EXEC _x bits (starting bits) of the command register 35, if the command is stored in the area of the command buffer 39 corresponding to this suffix x (0 to n), write "1" and then Go to step. It is judged whether the command is stored in all the areas from "0" to "n" of the command buffer 39, and "YE
If "S", proceed to the next step, and if "NO", return to step. Note that this step is performed after confirming that the processing of the previous command has been completed. Judge whether "1" is set for the END _x bit (rendering end bit of area x) of the status register 32. If "YES", proceed to the next step. If "NO", make this determination. Repeat (communication control unit 7
See step '). Clear this END _x bit to '0' and return to the step. The command register is linked to this clear.
The 35 corresponding EXEC _x bits are also reset to '0'. Has become.

Further, the processing procedure in the communication control unit 7 is to set the value'x 'of the current pointer 38 which points to the processing target area in the command buffer 39 to "x = 0", and proceed to the next step. . 'By checking the output of the AND circuit 36, it is judged whether or not the EXEC _x bit of the command register 35 is set to "1". If "YES", proceed to the next step, and if "NO", This determination is repeated (see step of CPU1). 'The counter 37 is updated with the value'x' of the current pointer 38, and the process proceeds to the next step. ′ Determine whether the data (END) of the internal status register 34 is “1”. If “YES”, proceed to the next step, and if “NO”, repeat this determination (rendering). (See step 6 of processor 6.) 'Set END _x bit of status register 32 to "1",
Also, set the EXEC _x bit of the command register 35 to "0", and proceed to the next step. 'The value'x' of the current pointer 38 is incremented by "+1" and the process returns to the step '. The value of'x 'is "0 to n", and "0" is set after "n". Has become.

Further, the processing procedure in the rendering processor 6 reads "the value of the counter 37 and proceeds to the next step. (Refer to the step 'of the communication control section 7)""Whether this value is valid, That is, "0
~ N "is in the range, then" YES "
In the case of, the process proceeds to the next step, and in the case of “NO”, the process returns to the step “.” The header section 12 taken out from the No.x (0 to n) area of the command buffer 39 is loaded and the next step is executed move on. ″ From the FIFO buffer 4 (corresponding to this header section 12 command), one segment of data in the feature point data section 13
Data and proceed to the next step. "The drawing process based on the header portion 12 and the segment data 18 is executed and the process advances to the next step." The data following the segment data 18 is loaded from the FIFO buffer 4 and the process advances to the next step. ″ Determine whether this input data is SOD,
If "YES", the process returns to step ", and if" NO ", the process proceeds to the next step. ″ Determine if this input data is EOD,
In the case of "YES", the process proceeds to the next step, and in the case of "NO", processes such as interrupt control described later are executed according to the input data. ″ Data of internal status register 34 (END)
Is set to "1" and the process returns to step ".

Next, FIG. 7 is an explanatory view showing the concept of interrupt control in response to a movement request from the CPU side regarding the shared resource use right of the image memory, etc., and the DMA controller 5, the selector 21, the SOD / EOD judging section. In addition to the data counter 23, the FIFO buffer 4 and the FIFO port 31, the interrupt handler 51 of the communication control unit 7 and the internal status register 34 and internal control register 52 therein are used.

Here, when it becomes necessary for the CPU 1 to move the usage right of the image memory 9 or the like, which is a shared resource with the rendering processor 6, to the self, the CPU 1 executes the interrupt control as described below.

That is, the CPU 1 side first sets "1" in the control bit 53 of the internal control register 52 corresponding to the interrupt type, and then requests the rendering processor 6 to temporarily freeze the drawing process, , There is a notification of shared resource release from the rendering processor 6 (PAU of the internal status register 34).
Wait until the SE bit 54 is set to '1', then execute the necessary processing for the shared resource, then clear the control bit 53 of the internal control register 52 to '0' is doing.

On the side of the interrupt handler 51 are: -Control bit 53 of the internal control register 52
If "1" is set to any of the above, the selector 21 is switched at the time when the next SOD / EOD in the DMA transfer data is detected, and the interrupt bit 55 is inserted before this SOD / EOD to cause the interrupt. The bit 55 is input to the FIFO buffer 4, and at the same time, the DMA controller 5 is instructed to suspend its operation to facilitate the acquisition of the bus right of the CPU 1, and the control bit of the internal control register 52. It waits for all 53 to be cleared to "0" by the CPU 1, and then sends a signal instructing the DMA controller 5 to restart the operation.

Further, the rendering processor 6 side: When the interrupt bit 55 is received from the FIFO port 31, the PAUSE bit of the internal status register 34 at the time when the processing regarding the shared resource currently in use is completed.
By setting "1" in 54, the notification of shared resource release is given, and thereafter, the processing related to shared resources is suspended until the next SOD / EOD is received.

[0050]

As described above, according to the present invention, both the header portion and the feature point data portion constituting the graphic element data are stored in the main storage device in such a manner that they can be combined by the link data provided in a part of the former. The header parts of a plurality of graphic element data to be rendered are first stored in the shared memory, and the characteristic point data parts are stored in the FIFO buffer by DMA transfer based on the link data of the header part. is doing.

Therefore, on the rendering processor side, parallel processing is performed on the header portion and the feature point data portion of the plurality of graphic elements, and the rendering system as a whole can be speeded up.

Further, the CPU sends only the header parts relating to a plurality of graphic elements to be rendered to the rendering processor side and, after activating them, the CPU is released from the rendering process and can shift to another event process early. it can.

This enables a well-balanced transition between processes when implementing a multi-client / server system via a network represented by UNIX-OS.

Further, in the case of an interrupt request from the CPU for the shared resource, SOD or EO indicating a delimiter between segment data, which is the basic unit of the feature point data portion, etc.
When D is DMA-transferred, the interrupt bit is stored in the FIFO buffer, and the rendering processor that receives this interrupt bit releases the shared resource at the time when the processing regarding the shared resource currently in use is completed. There is.

Therefore, the transfer of the shared resource usage right to the CPU side is always synchronized with the end of the processing unit of the rendering processor, and the drawing processing in the segment data unit of the feature point data portion can be secured.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram showing an outline of a graphic rendering method of the present invention.

FIG. 3 is an explanatory diagram showing multiple buffering and pipelining of a header part of the present invention.

FIG. 4 is an explanatory diagram showing the concept of a DMA transfer logic of the present invention.

FIG. 5 is an explanatory diagram (No. 1) showing a processing procedure in the CPU, the communication control unit, and the rendering processor of the present invention.

FIG. 6 is an explanatory diagram (No. 2) showing the processing procedure in the CPU, the communication control unit, and the rendering processor of the present invention.

FIG. 7 is an explanatory diagram showing the concept of interrupt control in response to a move request from the CPU side regarding a shared resource usage right according to the present invention.

FIG. 8 is an explanatory diagram showing a state of a drawing target figure in general computer graphics processing.

FIG. 9 is an explanatory diagram showing an outline of a conventional graphic rendering method.

[Explanation of symbols]

 In FIG. 1, 1 ... CPU 2 ... Main storage device 3 ... System bus 4 ... FIFO buffer 5 ... DMA controller 6 ... Rendering processor 7 ... Communication control unit 8 ...・ Shared memory 9 ・ ・ ・ Image memory

Claims (4)

[Claims] 1. A format of graphic element data for individually expressing each graphic element constituting an arbitrary graphic, a header section showing overall attributes such as the type of the graphic element and display conditions, and A data format consisting of a feature point data section showing individual attributes such as coordinate values of feature points, shading, and color, and a rendering processor performing drawing processing based on the graphic element data transferred from the main storage device. Thus, in the figure rendering method in which the figure is three-dimensionally displayed, the link data for associating the header part and the feature point data part for an arbitrary graphic element is set in the header part. Then, the CPU sequentially transfers and stores the header section for the graphic element to be rendered from the main storage device to the shared memory and stores the header part. An execution command for each header section is sent to the communication control section, and the communication control section informs the rendering processor of the header section to be processed next based on this execution command, and in an independent form from this, The link data set in the header section is taken out from the shared memory and notified to the DMA controller, and the DMA controller stores the feature point data section specified by the link data. The rendering processor executes DMA transfer such as sequentially reading from the main storage device and storing in a buffer, and the rendering processor loads the header portion of the graphic element data to be processed from the shared memory, and the graphic element data. The feature point data part of is loaded from the buffer. Graphic rendering method that. 2. The SOD indicating the delimiter between the segment data having the same data word length and set for each feature point and the next segment data in the feature point data section, and And an EOD indicating the end of the characteristic point data section, wherein the link data is a DMA address indicating the start address of the characteristic point data section stored in the main storage device, and 2. A graphic rendering system according to claim 1, wherein the data word length of the segment data is used, and a FIFO buffer is used as the buffer. 3. The feature point data portion DMA-transferred from the main memory and a counter output indicating which number of data words of the feature point data portion DMA-transferred are input. , A judging section having a function of detecting the SOD or EOD based on these input signals is provided, and the judging section receives data of only the data word length of the feature point data section. After that, the next data is the SO.
If the result is EOD, the DMA controller determines whether it is D or EOD, and if the result is EOD, the DMA of the feature point data part corresponding to the next header part stored in the shared memory. The graphic rendering method according to claim 2, wherein the transfer is executed. 4. When the transfer request of the usage right regarding the shared resource with the rendering processor is transferred from the CPU and the control bit of the communication control unit is set to a predetermined value, the determination unit then performs the SOD or EOD. At the time of detecting the above, the input signal to the buffer is switched from the feature point data section to the interrupt bit, and the DMA
The rendering processor, which has instructed to stop the operation of the controller and has loaded this interrupt bit, sets the pause bit of the communication control unit to a predetermined value when the processing relating to the shared resource currently in use is completed, and the CPU After confirming the setting of the pause bit, the process for the shared resource is executed, and after that, the control bit is cleared, and the communication control unit confirms the clear, and then the DM
The graphic rendering system according to claim 3, wherein an instruction to restart the operation of the A controller is issued.