JPH06259324A - Cache disconnection controller - Google Patents

Abstract

PURPOSE:To provide a device which securely evade the operation stop of a system due to a software error as to a device which performs cache memory disconnection control. CONSTITUTION:This cache disconnection controller is provided with error counters 12 prepared by ways or way groups of a cache memory 10, a means 14 which detects the occurrence of a cache error from read data of the cache memory 10, a means 16 which updates the value of the error counter 12 prepared for the way or way group where the cache error occurs, disconnection request output latches 18 which are provided by the error counters 12 and output requests to disconnect the ways or way group prepared for the error counter 12 when the values of the corresponding error counters 12 reach a predetermined value, and a means 20 which rest all the error counters 12 at the same time each time a certain time is elapsed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache disconnection control device for controlling disconnection of a cache memory.

Many computer systems use a cache memory to speed up the processing of the CPU. Generally, the cache memory has a multi-way configuration, and the way portion in which the hardware error exists is separated by this type of device.

[0003]

2. Description of the Related Art In FIG. 4, 16 ways (WAY0-WAY
The cache memory of 15) is shown, and data is stored at the line address corresponding to the hash address.

When different addresses have the same line address as a result of hashing, the data is stored in another way, and a plurality of different data are held at the same line address.

An error counter is provided for each way of the cache memory or for each way group. When a parity error is detected during reading of the cache memory, the value of the corresponding error counter is incremented.

Further, after the corresponding cache content is once invalidated (Abandon Buffer), the data in the real memory is stored again in the cache memory and read from the cache memory (instruction retry). When the error detected at that time is caused by a soft one, the instruction execution is successful in most cases by one retry.

On the other hand, when the detected error is permanent due to a hardware failure, the operation of incrementing the value of the error counter and retrying the instruction is repeated.

As a result, the value of the error counter reaches a preset value, a disconnection request is output from this way or way group, and the way or way group is disconnected.

After that, the separated way or way group becomes unusable (cache,
Degrade), another way or way group is used.

Therefore, the system can continue to operate safely using only the normal cache portion. Note that the OS can be interrupted by machine check (can be suppressed)
Will be reported to inform you of the system degradation.

[0011]

The RAM constituting the cache memory is being integrated. Therefore, R
It becomes increasingly difficult to secure the data holding capacity of AM, and as the data holding capacity decreases, the probability of occurrence of a 1-bit error in RAM (due to bit inversion due to α ray) increases.

Further, an increasing number of systems are operated 24 hours a day without stopping for 24 hours. Therefore, in a system that has a large-capacity cache memory composed of highly integrated RAM and is operated without interruption, after a long time (for example, 2 to 3 months) has elapsed from the start of operation, the values of all error counters are The number of times of disconnection is reached, and the entire cache memory becomes unusable.

In that case, since the processing speed of the system is extremely reduced (substantially system down), it is necessary to stop the clock and then perform a hard reset beyond the degradation (stop the operation). Equivalent to restart, the hardware control information is also reset).

The present invention has been made in view of the above conventional circumstances, and an object thereof is to provide a cache switching control device capable of reliably avoiding a system operation stop due to a soft error.

[0015]

In order to achieve the above object, an apparatus according to the present invention is constructed as shown in FIG.
In the figure, the device of the first invention is a cache memory 10
Error counter 12 prepared for each way or for each way group, cache error detection means 14 for detecting the occurrence of a cache error from the read data of the cache memory 10, and a way or a way group for which a cache error has occurred. An error number updating means 16 for updating the value of the error counter 12, and a way provided for each error counter 12 and provided with the error counter 12 when the corresponding value of the error counter 12 reaches a predetermined value. Alternatively, it has a disconnection request output latch 18 for continuously outputting the disconnection request of the way group, and an error counter reset means 20 for resetting all the error counters 12 at the same time every time a predetermined time has elapsed. .

In the figure, the device according to the second invention detects the occurrence of a cache error from the error counter 12 prepared for each way or each way group of the cache memory 10 and the read data from the cache memory 10. The cache error detecting means 14, the error number updating means 16 for updating the value of the error counter 12 prepared for the way or way group in which the cache error has occurred, and the error counter 12 provided for each error counter 12 have the corresponding value of the error counter 12. A disconnection request output latch 18 that continuously outputs a disconnection request of a prepared way or way group when the error counter 12 reaches a predetermined value, and an error counter every time a predetermined time elapses. Error counter resetting means 20 for resetting all 12 at the same time , Latch reset means 2 to reset all the dissection required output latch 18 at the same time forcibly stop the output of the separating request when a predetermined command is given
2 and.

[0017]

Operation While hard errors occur continuously, soft errors are sudden and occur sporadically.

Therefore, all the error counters prepared for each way or way group are reset with a constant synchronization,
The separation of the cache part (way / way group) due to a soft error is prevented.

When a large number of cache parts are cut off due to frequent occurrence of soft errors and the processing speed of the system is significantly reduced, a predetermined command is input. When this command is input, all of the latches 18 are reset, the output of the disconnection request is forcibly stopped, and all of the cache parts that have been disconnected due to the frequent occurrence of soft errors are recovered (reusable).

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a cache disconnection control device according to the present invention will be described below with reference to the drawings.

FIG. 2 illustrates the configuration of the embodiment,
The cache memory 10 has a 16-way configuration, and each way (WAY0 to WAY15) has 8 groups [0, 1],
[2,3], [4,5], [6,7], [8,9],
It is divided into [10, 11], [12, 13], and [14, 15].

Each way group is provided with a 3-bit error check counter 12 and a 1-bit latch 18, and the latch 18 is set when the value of the error check counter 12 reaches 5.

When the latch 18 is set, a disconnection request for the way group provided with the latch 18 is output, and the CPU (not shown) recognizes the request. Further, the cache read data is the parity check circuit 14
The number of the way for which the data has been read is input to the selection circuit 16 together with the output of the parity check circuit 14.

The output of the selection circuit 16 is obtained when an output indicating the occurrence of an error is given from the parity check circuit 14, and is transmitted to the way group to which the way indicated by the input number belongs.

In the way group in which the output of the selection circuit 16 is obtained, the value of the error counter 12 is incremented. However, since the hard error is continuously detected and the latch 18 is immediately set, the soft error is sporadically detected and therefore the latch 18 is not set in one day.

The output of the counter reset circuit 20 is supplied to these error counters 12, and all of the error counters 12 are simultaneously reset by the output of the counter reset circuit 20.

Further, the counter reset circuit 20 shown in FIG.
# In TOD (Time Of Day)
16 to # 37 are referenced every 3.3 seconds (due to interruption), and when all of these bits # 16 to # 37 become "1", the output of the counter reset is obtained.

Bits # 16 to # 37 of this TOD are about 1
Every 9.09 hours, all the bits become "1" for 16.384 seconds, and during the 16.384 seconds, the counter reset circuit 2
0 refers to TOD at least once.

Therefore, all the error counters 12 are reset every about 19.09 hours. That is, as described above, since soft errors do not occur four times a day, disconnection of way groups due to soft errors is reliably avoided, and only abnormal way groups in which hard errors have occurred are separated (abnormal way groups). Is held by the latch 18).

However, when a predetermined command is given from the external SVP 24 to the latch reset circuit 22, its output is supplied to each latch 18 via the clock synchronization circuit 26 (which synchronizes the clock with the SVP 24 side). It

As a result, all of the latches 18 are reset at the same time, and the way group disconnection request output is forcibly stopped and controlled, and all the way groups that have been separated until then can be used again.

This command is input when the operator or service engineer confirms that the processing speed of the system has decreased due to frequent occurrence of soft errors. Therefore, the cache memory 10 is returned to the initial operating state while the system is operating. It becomes possible.

As described above, according to the present embodiment, the separation of the way group due to the soft error can be effectively prevented, and the separated way group due to the frequent occurrence of soft errors can be recovered. It is possible to avoid the substantial system down caused by the above and to realize the continuous system operation more completely.

[0034]

As described above, according to the present invention, the separation of the cache memory due to the soft error can be effectively prevented, and the portion separated by the frequent occurrence of the soft error can be freely restored, which causes the soft error. It is possible to reliably avoid a system shutdown.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the invention.

FIG. 2 is an explanatory diagram of a configuration of an embodiment.

FIG. 3 is an explanatory diagram of TOD.

FIG. 4 is an explanatory diagram of a configuration of a cache memory.

[Explanation of symbols]

 10 cache memory 12 error counter 14 parity check circuit 16 selection circuit 18 latch 20 counter reset circuit 22 latch reset circuit 24 SVP 26 clock synchronization circuit

Claims (2)

[Claims] 1. An error counter (1) prepared for each way or for each way group of a cache memory (10).
2) and cache error detecting means (1) for detecting the occurrence of a cache error from the read data of the cache memory (10).
4), error number updating means (16) for updating the value of the error counter (12) prepared for the way or way group in which the cache error occurs, and the error counter (12) provided for each error counter (12). A disconnection request output latch (18) for continuously outputting a disconnection request of a way or a way group for which the error counter (12) is prepared when the value of 12) reaches a predetermined value; And an error counter resetting means (20) for resetting all of the error counters (12) at the same time every time the above time elapses. 2. Each way of the cache memory (10)
Or an error counter (1 for each way group)
2) and cache from the read data of the cache memory (10)
Cache error detection means for detecting the occurrence of an error (1
4) and the way or way group where the cache error occurred.
Update the value of the prepared error counter (12)
The error count updating means (16) and the error counter (12) are provided for each corresponding error.
When the value of the counter (12) reaches a predetermined value
From the way in which the error counter (12) is prepared or
Detach request that continuously outputs the way group disconnect request
Output latch (18) and error counter (12)
Error counter resetting means
(20) and a disconnection request output latch when a predetermined command is given
Reset all of (18) at the same time and output the disconnection request
Latch reset means (22) for forcibly stopping, and cache disconnection control means characterized by: