JPH06259174A - Memory power supplying method - Google Patents

Abstract

PURPOSE:To attain the reading/writing of data of a non-volatile memory by supplying a power source from an outside device regardless of the on/off of the power source of a computer system. CONSTITUTION:A power source collision evading circuit 13a evades the collision of a power supply voltage from a main power source 11 with the power supply voltage from an outside device 2a at the time of connecting the outside device 2a to a computer system 1. Therefore, the power supply voltage from the outside device 2a is supplied to the computer system 1 regardless of the on/off of the main power source 11, so that the reading/writing operation of a non-volatile memory 4 can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory power supply method for reading / writing data in a non-volatile memory by supplying power from an external device.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a configuration of a conventional memory power supply method. In FIG. 8, 1 is a computer system and 2a is an external device connected to the computer system 1. In the computer system 1, 3 is a central processing unit (hereinafter CPU).
4 is a non-volatile memory, and 5 is a connection determination circuit that determines whether or not the external device 2a is connected and outputs a connection determination signal 6 to the bus switching circuit described below. 7 is C
Address signal 8 output from PU3 and external device 2a
a, 8b, control signals 9a, 9b, and input / output data signals 10a, 10b are switched by the connection determination signal 6 from the connection determination circuit 5 to change the address signal 8c, the data signal 1
0c, a bus switching circuit for giving the control signal 9c to the nonvolatile memory 4, 11 is a main power supply.

Next, the operation will be described. External device 2a
Is connected to the computer system 1 and the main power supply 11 is turned on. The connection determination circuit 5 outputs to the bus switching circuit 7 that it is connected to the external device 2a as a connection determination signal 6. Bus switching circuit 7 to which connection judgment signal 6 is input
Are address signals 8c, data signals 10c, and data signals 9c supplied to the non-volatile memory 4, address signals 8a output from the CPU 3, control signals 9a, and address signals output from the external device 2a from the input / output data signals 10a. 8b, control signal 10b and input / output data signal 9b. Through the above processing, the reading / writing of the data of the non-volatile memory 4 is performed from the external device 2a.

Note that as a document describing a technique related to the reading / writing of data from / to a nonvolatile memory by such a conventional memory power supply method, for example, JP-A-4-130977 and JP-A-4-188347.
There is a bulletin, etc.

[0005]

Since the computer system adopting the conventional memory power supply method is configured as described above, unless the main power is turned on, the data in the non-volatile memory is transferred from the external device. There is a problem that reading / writing is not possible.

The present invention has been made in order to solve the above problems, and a memory capable of reading / writing data in a non-volatile memory from an external device regardless of whether the main power source of the computer system is turned on or off. The purpose is to obtain a power supply method.

[0007]

The first invention comprises a power supply collision avoidance circuit 13a for avoiding a collision between the power supply voltage from the main power supply 11 and the power supply voltage from the external device 2a when connected to the external device 2a. The power supply voltage is supplied from the external device 2a regardless of whether the main power supply 11 is turned on or off to enable the read / write operation of the memory 4.

A second aspect of the invention is a power supply collision avoidance circuit 13b for supplying a power supply voltage from the external device 2a to only a minimum number of components required for memory operation when the external device 2a is connected.
The power supply voltage is supplied from the external device 2a regardless of whether the main power supply 11 is turned on or off, and the read / write operation of the memory 4 is enabled.

A third aspect of the invention comprises a voltage determination circuit 14 which determines whether or not the voltage of the main power source 11 is higher than a reference voltage and outputs a voltage determination signal, and when the main power source 11 is "ON", The power supply voltage is not supplied from the external device 2b according to the voltage determination signal at this time, and the power supply voltage is supplied from the external device 2b according to the voltage determination signal at this time when the main power supply 11 is "OFF". It enables read / write operations.

[0010]

In the first aspect of the invention, even when the main power source 11 is "OFF", when the external device 2a is connected, the power source voltage from the external device 2a is transferred to the memory 4 and the memory 4 via the power source collision avoidance circuit 13a. It is supplied to all other components. This enables the read / write operation of the memory 4.

In the second invention, when the external device 2a is connected when the main power supply 11 is "off", the power supply voltage from the external device 2a is supplied to the memory 4 and the memory 4 via the power supply collision avoidance circuit 13b. It is supplied only to the minimum components necessary for other memory operations. This enables the read / write operation of the memory 4.

In the third aspect of the invention, when the main power supply 11 is "off" and this voltage is equal to or lower than the reference voltage, the external device 2b follows the voltage determination signal of the voltage determination circuit 14 at this time.
Is supplied to the memory 4 and the like. This enables the read / write operation of the memory 4.

[0013]

【Example】

Example 1 (corresponding to claim 1). 1 is a block diagram showing a configuration of a memory power supply method according to a first embodiment of the present invention. 1, the same reference numerals as those in FIG. 8 indicate the same or corresponding parts. In FIG. 1, 1
2 is a power supply terminal that receives power from the external device 2a, 1
Reference numeral 3a is a power supply collision avoidance circuit that supplies a power supply voltage to the entire computer system 1 by avoiding a collision between the voltage of the main power supply 11 and the voltage of the power supply from the external device 2a.

Next, the operation will be described. External device 2a
To the computer system 1. Power is supplied to the entire computer system 1 from the external device 2a through the power supply terminal 2 and the power supply collision avoidance circuit 13a regardless of whether the main power supply 11 is turned on or off. When power is supplied, the connection determination circuit 5 outputs to the bus switching circuit 7 a connection determination signal 6 indicating that the external device 2a is connected. The bus switching circuit 7 to which the connection determination signal 6 is input receives the address signal 8c, the data signal 10c, and the control signal 9c to the nonvolatile memory 4 from the CPU 3
The output address signal 8a, the control signal 9a and the input / output data signal 10a are switched to the address signal 8b output from the external device 2a, the control signal 9b and the input / output data signal 10b. Through the above processing, the reading / writing of the data of the non-volatile memory 4 is performed from the external device 2a.

FIG. 2 shows a circuit configuration example of the connection determination circuit 5. In FIG. 2, when the external device 2a is connected, the connection signal 100 is at "L" level and the buffer 101
Entered in. The connection determination signal 6, which is the output of the buffer 101, becomes "L" level. When the external device 2 is not connected, the connection signal 100 becomes “H” level by the pull-up resistor 102 and is input to the buffer 101.
The connection determination signal which is the output of the buffer 101 becomes "H" level. By such an operation, it is determined whether or not the external device 2a is connected to the computer system 1.

Embodiment 2 (corresponding to claim 2). In the first embodiment, the power supply collision avoidance circuit 13a supplies the power from the external device 2a to the entire computer system 1, but as the second embodiment, it is the minimum necessary for reading / writing data in the nonvolatile memory 4. You may make it supply only to a component.

FIG. 3 is a block diagram showing the configuration of a memory power supply method in the case of the second embodiment. In FIG.
The same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In FIG. 3, 13b avoids a collision between the voltage of the main power source 11 and the voltage of the power source from the external device 2a, and the main power source 11 supplies the entire computer system 1, and the power source from the external device 2a is non-volatile. This is a power supply collision avoidance circuit that supplies power only to the memory 4, the connection determination circuit 5, and the bus switching circuit 7, that is, only to the components necessary for the memory operation.

With this configuration, the computer system 1 receives the minimum required power supply from the external device 2a.
The data in the nonvolatile memory 4 can be read / written.

Embodiment 3 (corresponding to claim 3). In the first and second embodiments, the power is supplied from the external device 2a regardless of whether the main power supply 11 is turned on or off.
If is "ON", it is not necessary to supply power from the external device 2a.

FIG. 4 is a block diagram showing the configuration of a memory power supply method in the case of the third embodiment. 4, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In FIG. 4, reference numeral 14 is a voltage determination circuit that determines whether or not the voltage of the main power supply 11 is higher than a reference voltage for determining whether or not the power supply is in the “ON” state and outputs the voltage determination signal 15. Reference numeral 2b is an external device to which the voltage determination signal 15 which is the output of the voltage determination circuit 14 is input and which does not supply power when the main power supply 11 is "ON" and which supplies power when the main power supply 11 is "OFF". .

FIG. 5 shows a circuit configuration example of the voltage determination circuit 14. In FIG. 5, 201 is a main power supply voltage, 202 is a variable resistor for setting the reference voltage 203, 204 is a comparator for comparing the main power supply voltage 201 with the reference voltage 203, and 205 is a pull-up resistor. With such a configuration, when the main power supply 11 is “ON”, the main power supply voltage 201
Is higher than the reference voltage 203, the comparator 20
The voltage determination signal 15 which is the output of No. 4 becomes "L" level. Further, when the main power supply 11 is “off”, the main power supply voltage 201
Is equal to or lower than the reference voltage 203, the comparator 204
The voltage determination signal 15 from is at "H" level.

FIG. 6 shows an example of the configuration of the power supply section of the external device 2b. In FIG. 6, the voltage determination signal 15 output from the voltage determination circuit 14 and the external device power source 302 are input to the relay switch 301 of the external device 2b, and the voltage determination signal 15 is at the “L” level (main power source “ON”). State), the external device 2b does not supply power to the computer system 1 in this case. Also, the voltage determination signal 15 is "H".
At the level (main power “off” state), the relay 301 is turned on, and the external device 2b supplies power to the computer system 1.

With this configuration, the main power source 1
When 1 is "ON", no power is supplied from the external device 2b, and when the main power supply 11 is "OFF", power is supplied from the external device 2b, and the data in the nonvolatile memory 4 can be read / written.

In each of the above embodiments, the case where the external device is provided with the power supply for generating the voltage of the same level as the main power supply voltage of the computer system has been described.
When the power supply voltage of the external device is different from the power supply voltage of the computer system, the DC-DC converter 300 is provided in the computer system 1 as shown in FIG.
The power supply voltage of 1 may be matched with the power supply voltage of the computer system. In FIG. 7, 13 is a power supply collision avoidance circuit, 2 is an external device, and FIGS.
Power source collision avoidance circuits 13a and 13b shown in FIG.
It corresponds to a and 2b for explanation.

In the case of FIG. 7, the DC-DC converter 300 is provided on the computer system 1 side.
The C-DC converter 300 may be provided on the external device 2 side.

[0026]

As described above, according to the first invention, by providing the power supply collision avoidance circuit, the power supply voltage can be supplied from the external device regardless of whether the main power supply of the computer system is turned on or off. There is an effect that the memory read / write operation can be performed without worrying about the power on / off operation.

According to the second aspect of the present invention, by providing the power supply collision avoidance circuit, the power supply voltage is supplied from the external device to only the minimum components including the memory regardless of whether the main power supply of the computer system is turned on or off. Therefore, the same effect as described above can be obtained, and the power from the external device can be saved.

According to the third invention, when the main power supply of the computer system is "ON", the power supply voltage is not supplied from the external device according to the voltage judgment signal of the voltage judgment circuit at this time, and the main power supply is " When the power is turned off, the power supply voltage is supplied from the external device according to the voltage determination signal at this time.
There is also an effect that the writing operation becomes possible and, in this case, the power source of the external device can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory power supply method according to a first embodiment of the present invention.

2 is a circuit diagram showing a circuit configuration example of a connection determination circuit in FIG.

FIG. 3 is a block diagram showing a configuration of a memory power supply method according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a memory power supply method according to a third embodiment of the present invention.

5 is a circuit diagram showing an example of the circuit configuration of the voltage determination circuit in FIG.

6 is a circuit diagram showing an example of a circuit configuration of a power supply unit of the external device in FIG.

FIG. 7 is an explanatory diagram of a DC-DC converter provided when the power supply voltage of the external device is different from the power supply voltage of the computer system in the present embodiment.

FIG. 8 is a block diagram showing a configuration of a conventional memory power supply method.

[Explanation of symbols]

 1 Computer System 2a, 2b, 2 External Device 3 CPU 4 Nonvolatile Memory 5 Connection Judgment Circuit 6 Connection Judgment Signal 7 Bus Switching Circuit 8a, 8b, 8c Address Signal 9a, 9b, 9c Control Signal 10a, 10b, 10c Data Signal 11 Main power supply 12 Power supply terminals 13a, 13b, 13 Power supply collision avoidance circuit 14 Voltage judgment circuit 15 Voltage judgment signal 100 Connection signal 101 Buffer 102 Pull-up resistance 201 Main power supply voltage 202 Variable resistance 203 Reference voltage 204 Comparator 205 Pull-up resistance 300 DC- DC converter 301 Relay switch 302 External device power supply

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[Procedure amendment]

[Submission date] June 10, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (3)

[Claims] 1. A memory for storing data, a central processing unit for reading / writing data from / to this memory, and a connection for outputting a connection determination signal by determining whether or not it is connected to an external device. If the determination circuit and the connection determination signal indicate non-connection, the input / output bus of the central processing unit is connected to the memory, and if the connection determination signal indicates connection, the input / output bus of the external device is connected to the memory. In a computer system including a bus switching circuit connected to, and a main power supply for supplying a power supply voltage to each of the above components,
A power supply collision avoidance circuit for avoiding a collision between the power supply voltage from the main power supply and the power supply voltage from the external device when connecting to the external device is provided, and the power supply voltage from the external device is supplied regardless of whether the main power supply is turned on or off. And a read / write operation of the memory is enabled. 2. A memory for storing data, a central processing unit for reading / writing data from / to this memory, and a connection for outputting a connection determination signal by determining whether or not it is connected to an external device. If the determination circuit and the connection determination signal indicate non-connection, the input / output bus of the central processing unit is connected to the memory, and if the connection determination signal indicates connection, the input / output bus of the external device is connected to the memory. In a computer system including a bus switching circuit connected to, and a main power supply for supplying a power supply voltage to each of the above components,
A power supply collision avoidance circuit that supplies a power supply voltage from the external device to only the minimum components necessary for the memory operation when connecting to the external device is provided, and the external device is connected regardless of whether the main power supply is turned on or off. A memory power supply method characterized by supplying a power supply voltage to enable read / write operations of the memory. 3. A memory for storing data, a central processing unit for reading / writing data from / to this memory, and a connection for outputting a connection determination signal by determining whether or not it is connected to an external device. If the determination circuit and the connection determination signal indicate non-connection, the input / output bus of the central processing unit is connected to the memory, and if the connection determination signal indicates connection, the input / output bus of the external device is connected to the memory. In a computer system including a bus switching circuit connected to, and a main power supply for supplying a power supply voltage to each of the above components,
A voltage determination circuit for determining whether or not the voltage of the main power source is higher than a reference voltage and outputting a voltage determination signal is provided, and when the main power source is “ON”, the external device according to the voltage determination signal at this time. When the main power supply is "off", the power supply voltage is supplied from the external device according to the voltage determination signal at this time to enable the read / write operation of the memory. Characteristic memory power supply method.