JPH06252792A - Reception circuit - Google Patents

Abstract

PURPOSE:To provide a reception circuit dispensing with any adjustment at the time of manufacture and adjustment for a temperature change or an change even when a current consumption is reduced. CONSTITUTION:The reception circuit 10 is formed in a synthesizer system. A PLL 30 is made up of a VCO 31, a variable frequency divider circuit 33, a phase comparator circuit 34 and a loop filter 37. An AFc circuit 50 is formed by a storage circuit 57, a voltage comparator circuit 53 and the VCO 31. When one of plural channels is selected for the reception, a frequency divider ratio N corresponding to a reception object channel is set to the variable frequency divider circuit 33 to select an object channel. When the PLL 30 acquires an object channel to inactivate the PLL 30 and to actuate the AFC circuit 50 and the AFC circuit 50 latches the channel acquired by the PLL 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synthesizer type receiving circuit.

[0002]

2. Description of the Related Art A mobile station of a cellular type mobile telephone system is constructed, for example, as shown in FIG.

That is, in FIG. 5, 1 is a transmitting / receiving antenna, 10 is a receiving circuit, and 20 is a transmitting circuit. The receiving circuit 10 is configured in the double superheterodyne system, and the FM signal SRX of the downlink channel received by the transmitting / receiving antenna 1 is passed through the bandpass filter 11 and the high frequency amplifier 12 having the passbands in all the downlink channels. The oscillation signal S31 having a predetermined frequency is supplied from the VCO 31 while being supplied to the first mixer circuit 13, and the oscillation signal S31 is supplied to the mixer circuit 13 as a first signal.
The FM signal SRX supplied as the local oscillation signal is frequency-converted into the first intermediate frequency signal.

Then, the first intermediate frequency signal is supplied to the second mixer circuit 15 through the first intermediate frequency amplifier 14 composed of, for example, a crystal filter and a wide band amplifier, and at the same time, the second local oscillator circuit 16 outputs a second signal. The local oscillation signal is supplied to the mixer circuit 15, and the first intermediate frequency signal is frequency-converted into the second intermediate frequency signal. Then, the second intermediate frequency signal is supplied to the FM demodulation circuit 18 through the second intermediate frequency amplifier 17 composed of, for example, a ceramic filter and a wide band amplifier, and the voice signal of the communication partner and data and commands from the base station are transmitted. Demodulation signal S
18 is taken out to the terminal 19.

Further, in the transmission circuit 20, the voice signal of the user of the mobile station and the signals such as data and commands to the base station are supplied from the terminal 21 to the VCO 22 constituting the PLL, and the FM signal (intermediate frequency signal). Converted to S22. The FM signal S22 is supplied to the mixer circuit 23, the oscillation signal S31 of the VCO 31 is supplied to the mixer circuit 23 as a local oscillation signal, and the FM signal S22 is generated.
Is frequency-converted into an FM signal STX of the upstream channel which forms a pair with the FM signal SRX of the downstream channel, and this FM signal STX is transmitted to the antenna 1 through the transmission amplifier 24 and the band pass filter 25 having the pass bands of all the upstream channels. It is supplied and transmitted from the antenna 1 to the base station.

In this case, the VCO 31 has the circuit 3
A PLL 30 is configured together with 2 to 37. That is, the signal S31 from the VCO 31 is divided into a frequency of 1 / n in the prescaler 32, and then the variable frequency dividing circuit 3
3 and is further divided into a frequency of 1 / N, and this divided signal is supplied to the phase comparison circuit 34, and
The oscillation signal of the reference frequency f35 is taken out from the oscillation circuit 35, this oscillation signal is supplied to the comparison circuit 34, and the comparison output thereof is the charge pump circuit 36 and the loop filter 37.
Is supplied to the VCO 31 as its control voltage through.
The charge pump circuit 36 converts the comparison output of the comparison circuit 34 into a level suitable for the filtering process of the loop filter 37.

Therefore, in the steady state, the frequency-divided signal from the frequency-dividing circuit 33 and the oscillating signal of the oscillating circuit 35 have the same frequency. Therefore, the frequency f31 of the oscillating signal S31 at this time is f31 = n × N. × f35. Therefore, by changing the frequency division ratio N of the frequency dividing circuit 33,
Can be changed at the same time. And this division ratio N
Is changed or controlled by the microcomputer 40 for system control according to an instruction from the base station. The above is the general or basic configuration of the mobile station of the cellular mobile telephone system.

By the way, when the mobile station is a mobile phone, since the power source is a built-in secondary battery, the power consumption is required to be as small as possible. That is, if the power consumption is low, the mobile phone can be used for a long time.

Therefore, the portable telephone (mobile station) of FIG. 5 is further provided with an AFC circuit 50. That is, the output signal S18 of the demodulation circuit 18 is supplied to the voltage comparison circuit 53 through the resistor 51, a predetermined reference voltage VREF from the potentiometer 52 is transistorized and supplied to the comparison circuit 53, and the comparison output thereof is the charge pump circuit. At 54, the level is converted and then supplied to the loop filter 37. In this case, the demodulation circuit 18
The DC component V18 of the output signal S18 of
As shown in FIG. 6, FM changes to S-shape or N-shape.
When the center frequency fCEN of the signal SRX is the predetermined center voltage VC
However, the reference voltage VREF becomes equal to the center voltage VCEN corresponding to the center frequency fCEN (VREF = V
CEN) is set.

When the call channel is changed to the control channel (when the call state is changed to the standby state)
When the channel to be used is changed, such as when the control channel is changed to the call channel (when the standby state is changed to the call state), the AFC circuit 50 is deactivated and the PLL 30 is activated. . Therefore, as described above, the channel corresponding to the frequency division ratio N of the frequency dividing circuit 33 is selected.

When the PLL 30 promotes the channel corresponding to the frequency division ratio N, the PLL 30 is deactivated and the AFC circuit 50 is activated. Then, at this time, with the voltage VREF as a reference, the AFC circuit 50 operates so that the center voltage of the signal S18 becomes equal to the reference voltage VREF, and the voltage VREF has a center frequency fC.
Since the voltage VCEN corresponding to EN is set, the receiving frequency of the receiving circuit 10 is locked from the base station to the center frequency fCEN of the FM signal SRX, and the channel promoted by the PLL 30 has an accelerating state of the AFC circuit. Held by 50.

The holding of the channel by the AFC circuit 50 is continued until the next channel change, and at the time of the next channel change, the channel change is executed by the PLL 30 as described above.

In this way, in the mobile phone of FIG. 5, the change and the promotion of the channel are executed by the PLL 30, and when the channel is promoted, the holding of the channel is executed by the AFC circuit 50.

Then, the prescaler 32 and the frequency dividing circuit 3
3, the comparison circuit 34, the oscillation circuit 35, and the charge pump circuit 36 consume a total current of about 5 to 10 mA.
When the C circuit 50 is operating, these circuits 32 to
The power supply of 36 can be turned off, and the comparison circuit 53 and the charge pump circuit 54 consume a current less than 1 mA.

Therefore, after the PLL 30 promotes the channel, the current consumption can be reduced by holding the channel by the AFC circuit 50 and turning off the power sources of the circuits 32 to 36 thereafter. In particular, during actual use, the period during which the promoted channel is held in a certain channel is much longer than the period until the channel is changed and promoted, so that the current consumption is reduced. The effect is great.

[0016]

However, in the mobile phone of FIG. 5, the reference voltage VREF of the AFC circuit 50 is obtained from the potentiometer 52. Therefore, when the mobile phone is manufactured, the potentiometer 52 is adjusted to adjust the reference voltage VRE.
It is necessary to match F with the voltage VCEN corresponding to the center frequency fCEN.

Further, since the potentiometer 52 is used, the reference voltage VREF may change in temperature, and it is necessary to take measures against it in an actual telephone. Further, although the reference voltage VREF may change over time due to the change over time of the potentiometer 52, in order to readjust the potentiometer 52, the telephone must be opened, which is disadvantageous to the change over time.

The present invention is intended to solve the above problems.

[0019]

For this reason, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, a receiving circuit for selecting and receiving one of a plurality of channels is provided. , VCO31, a mixer circuit 13 that frequency-converts the received signal SRX into an intermediate frequency signal S13 by the oscillation signal S31 of the VCO31, and a demodulation circuit 18 that demodulates the intermediate frequency signal S13 from the mixer circuit 13. The super-heterodyne type receiving circuit 10 is configured, and the variable frequency dividing circuit 33 to which the oscillating signal S31 is supplied and the phase comparing circuit 34 for phase-comparing the frequency dividing signal of the variable frequency dividing circuit 33 and the signal of the reference frequency. And a loop filter 37 to which the output signal of the phase comparison circuit 34 is supplied, and the loop filter 37
The output voltage of the VCO 31 is supplied to the VCO 31 as its control voltage to configure the PLL 30, and the memory circuit 57 that stores the voltage V18 obtained by frequency-discriminating the intermediate frequency signal S13 and the intermediate frequency signal S
A voltage comparison circuit 53 that compares the voltage V18 obtained by frequency-discriminating 31 with the voltage V18 stored in the storage circuit 57 is provided, and the output voltage of this voltage comparison circuit 53 is VCO.
When the AFC circuit 50 is supplied to the AFC circuit 31, and one of the plurality of channels is selected for reception, the frequency division ratio N corresponding to the channel intended for the reception is changed by the variable frequency division circuit 33. When the target channel is selected by setting to, and the target channel is promoted by the PLL 30, the PLL 30 is deactivated and the AF
The C circuit 50 is brought into an operating state, and the AFC circuit 50 holds the channel promoted by the PLL 30.

[0020]

When the channel is changed, a new channel is selected and promoted by the PLL 30, and when the new channel is promoted, the channel is replaced by the AFC circuit 5
It is held by 0.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, an AFC circuit 50 is provided with a voltage comparison circuit 53 and a charge pump circuit 54, and an output signal S18 of an FM demodulation circuit 18 is supplied to a resistor 51.
Is supplied to the comparison circuit 53 through.

Further, 55 is a low-pass filter,
The low-pass filter 55 extracts the DC component V18 from the output signal S18 of the demodulation circuit 18. Also, 5
6 is an A / D converter, 57 is a latch or memory,
Reference numeral 58 represents a D / A converter. In this case, the memory 57
The reading and writing of is controlled by the microcomputer 40. Further, the power supplies of the circuits 32 to 36 of the PLL 30 are also controlled by the microcomputer 40 as described above.

When the channel to be used is changed, the microcomputer 40 deactivates the AFC circuit 50 and activates the PLL 30. Therefore, as described above, the PLL 30 selects the target channel. As well as being encouraged. And
At this time, since the PLL 30 is accelerating the target channel, V18 = VCEN, but this voltage VC
EN is supplied to the A / D converter 56 and A / D converted into digital data DCEN indicating the magnitude of the voltage VCEN, and this data DCEN is supplied to the memory 57 and stored in the memory 57.

Next, the microcomputer 40 turns off the power of the circuits 32 to 36 of the PLL 30 to bring the PLL 30 into the non-operating state and the AFC circuit 50 into the operating state. Further, from this time, the memory 57 is set to the read mode, and the data D
CEN is read out, and this data DCEN is supplied to the D / A converter 58 and is D / A converted into an analog voltage of the magnitude indicated by the data DCEN, that is, the voltage VCEN at the time of accelerating after the channel change. VCEN is the comparison circuit 5
3 is supplied as a reference voltage VREF.

Therefore, when the PLL 30 promotes the channel, the AFC circuit 50 thereafter performs the AFC operation with reference to the DC voltage VCEN at the time of channel promotion, and at this time, the voltage VCEN corresponds to the center frequency fCEN. Therefore, the AFC circuit 50 holds the channel promoted by the PLL 30.

The holding of the channel by the AFC circuit 50 is continued until the next channel is changed, and at the time of changing the next channel, the changing of this channel causes the PLL 30 to operate as described above. At the same time, the AFC circuit 50 is deactivated and executed.

Thus, according to this mobile phone, the PL
When the channel is changed and promoted by L30 and the channel is promoted, thereafter, by the AFC circuit 50,
The channel promoted by the PLL 30 is held on the basis of the voltage VCEN obtained from the demodulation circuit 18 at the time of promotion. Therefore, after the channel promotion, the circuit 32 of the PLL 30
Since the power supplies of ~ 36 can be turned off, current consumption can be reduced.

Further, each time the PLL 30 promotes a channel, the voltage VCEN at the time of the promotion is stored in the memory 57 and used as the reference voltage VREF when the AFC circuit 50 holds the channel. At that time, it is not necessary to adjust the reference voltage VREF. Further, the reference voltage VREF (= VCEN) of the AFC circuit 50 is updated each time the PLL 30 replenishes the channel according to the surrounding condition at that time, so that the reference voltage VREF (= VCEN) can be adjusted with respect to changes over time and temperature. No need to do.

The routine 100 of FIGS. 2 and 3 shows an example of a routine executed by the microcomputer 40 when the mobile phone enters the standby mode on the control channel and when the mobile phone is in the standby mode. That is, in this routine 100, when the power of the mobile phone is turned on, the microcomputer 4
The processing of 0 starts from step 101, and then, in step 102, the control ratio of 24 channels is sequentially scanned by changing the frequency division ratio N of the PLL 30. Then, at the time of this scan, in step 103, it is checked whether or not there is a receivable downlink control channel signal SRX from the base station, for example, by checking the level of the second intermediate frequency signal. At 104, the control channel having the maximum reception level is set to the reception state. Thus, when the power is turned on, the control channel with the highest reception level is promoted.

In step 103, when the FM signal SRX of the downlink control channel cannot be received, the process proceeds to step 109, and thereafter, for example, it is displayed that the mobile phone cannot be used, and this routine is once terminated.

Then, in step 111, it is checked whether the word sync can be promoted from the demodulated signal S18 in the control channel promoted in step 104. If the word sync can be promoted, the process proceeds to step 112. In step 112, it is checked whether or not the signal of the incoming call request from the base station is received. If not received, the process proceeds from step 112 to step 113. In this step 113, it is determined whether or not the reception level is changed. Checked. If the reception level has not changed, the process proceeds to step 11
From 3 to step 114, in step 114, it is checked whether or not a predetermined period (for example, several minutes) has elapsed since step 104 was executed, and if not, the process proceeds from step 114 to step 111. Return.

If the word sync cannot be promoted in step 111, the process returns from step 111 to step 102. Further, when the signal of the incoming call request from the base station is received in step 112, the process proceeds from step 112 to step 190,
This step 190 shifts to the call mode. If the reception level is changing in step 113, the process proceeds from step 113 to step 111.
Return to.

In this way, steps 111 to 114 are repeated, and the F of the control channel selected in step 104 is
It is checked whether the M signal SRX can be stably received for a predetermined period.

Then, when the reception level is stable for a predetermined period, the process proceeds from step 114 to step 121. In step 121, the memory 57 is set to the write mode, and the A / D at this time is set.
The output data of the converter 56 is stored in the memory 57. In this case, since the PLL 30 is locked to the control channel currently used, the data stored in the memory 57 is the data DCEN indicating the center voltage VCEN of the demodulated signal S18.

Then, in step 122, the memory 57 is set to the read mode. Therefore, thereafter, the data DCEN stored in step 121 is continuously fetched from the memory 57, and the comparison circuit 53 causes the comparison circuit 53 to store the voltage stored in the memory 57, that is, P
Demodulated signal S when LL30 has prompted the control channel
The center voltage VCEN of 18 is applied to the comparison circuit 53 by its reference voltage VREF.
Supplied as.

Then, in step 123, the PLL
The power of the circuits 32 to 36 of 30 is turned off and the PLL 30
Is deactivated and the circuits 53, 54, 58 are
Is turned on to activate the AFC circuit 50. Therefore, from this time point, the control channel promoted by the PLL 30 is held by the AFC circuit 50.

Next, in step 131, it is checked whether or not the word sync is being promoted. If the word sync is being promoted, the processing is from step 131 to step 132.
Then, in step 132, it is checked whether or not the signal of the incoming call request from the base station is received. If not, the process proceeds from step 132 to step 133, in which step 123 is executed. It is checked whether or not a predetermined time limit (for example, several minutes) has elapsed since the start, and if not, the process proceeds from step 133 to step 131.
Return to. Thus, if the predetermined time limit has not elapsed since the execution of step 123, step 13
1 to 133 are repeated. Therefore, the control channel is promoted by the PLL 30, and thereafter the AFC circuit 50
Holds the control channel, and enters the standby mode on this control channel.

Then, in this standby mode, when an incoming call request signal from the base station is received, this is detected in step 132, and the process proceeds from step 132 to step 141. In this step 141,
The power supply of the circuits 32 to 35 of the PLL 30 is turned on and PL
L30 is activated, and the frequency dividing circuit 33 is set to the frequency dividing ratio N corresponding to the channel promoted in step 104, that is, the channel held by the AFC circuit 50 so far. Further, the power supplies of the circuits 53, 54, and 58 of the AFC circuit 50 are turned off, and the AFC circuit 50 is deactivated. Therefore, from this point, the original control channel is in a state of being promoted by the PLL 30. Then, the process then proceeds to step 190.
In step 190, the call mode is entered.

When the steps 131 to 133 are repeated to enter the standby mode, when a predetermined time limit elapses, this is detected in step 133 and the process proceeds from step 133 to step 151. In this step 151, Similar to 141, PLL30
Is set to the operating state, the AFC circuit 50 is set to the non-operating state, and the original control channel is set to the state in which it is being promoted by the PLL 30. Then, after that, the process returns to step 111, and if the signals SRX from the base station can be stably received by steps 111 to 114, step 121 and subsequent steps are executed again.

Furthermore, when steps 131 to 133 are repeated and the standby mode is not reached, if word sync cannot be obtained, this is detected in step 131, and the process proceeds from step 131 to step 151. In this step 151, , The original control channel is being promoted by the PLL 30,
After that, the process returns to step 111, and this step 1
The processing after 11 is repeated.

In this way, in this routine 100, the control channel is promoted by the PLL 30, and when the control channel is promoted, the control channel becomes AF.
It is held by the C circuit 50, and the standby mode is continued while the AFC circuit 50 holds the control channel.
However, when in the standby mode, the PLL 30 is activated and the signal S from the base station is activated every predetermined period.
The reception state of RX is checked, and if the reception state is stable, the state in which the AFC circuit 50 holds the control channel is executed again.

FIG. 4 shows an example of a routine 200 executed by the microcomputer 40 when the mobile phone is in a call state. That is, when a call is made or a call is received, the PLL 30
The frequency division ratio N of is changed, the channel to be used thereafter shifts to the communication channel instructed by the base station, and thereafter,
A predetermined process is executed to enter the call mode. Then, when the call mode is entered, the call with the other party is made possible through the base station as described above, but immediately after the call mode is entered, the PLL 30 is in the operating state and the AFC circuit 50 is in the inactive state. .

When the call mode is entered, the processing of the microcomputer 40 starts from step 201, and then, at step 202, another PLL (not shown) is locked to the SAT signal included in the demodulated signal S18. If it is locked, the process proceeds from step 202 to step 203, and step 2
At 03, it is checked if the reception level has changed. Then, when the reception level has not changed, the process proceeds from step 203 to step 204,
In this step 204, it is checked whether or not a predetermined period has elapsed since the execution of step 201. If not, the process returns from step 204 to step 202. If the reception level has changed in step 203, the process returns from step 203 to step 202.

In this way, steps 202 to 204 are repeated, and it is checked whether or not the current communication channel can be stably received for a predetermined period.

When the reception level is stable for a predetermined period, step 1 of routine 100
The same processing as 21 to 123 is executed. That is, the processing of the microcomputer 40 is performed from step 204 to step 211.
In step 211, the memory 57 is set to the write mode, and the A / D converter 5 at this time
The output data of No. 6 is stored in the memory 57. in this case,
The data stored in the memory 57 is the data DCEN indicating the center voltage VCEN of the demodulated signal S18 because the PLL 30 is locked to the currently used communication channel.

Then, in step 212, the memory 57 is set to the read mode. Therefore, thereafter, the data DCEN stored in step 211 is continuously taken out from the memory 57, and the voltage stored in the memory 57 in step 211, that is, P
Demodulated signal S when LL30 promotes a call channel
The center voltage VCEN of 18 is applied to the comparison circuit 53 by its reference voltage VREF.
Supplied as.

Then, in step 213, the PLL
The power of the circuits 32 to 36 of 30 is turned off and the PLL 30
Is deactivated and the circuits 53, 54, 58 are
Is turned on to activate the AFC circuit 50. Therefore, from this point in time, the speech channel promoted by the PLL 30 is held by the AFC circuit 50.

Next, in step 221, for example, the second
By checking the level of the intermediate frequency signal, it is checked whether or not the reception level of the currently received FM signal SRX is larger than the specified value, and if it is larger, the process proceeds from step 221 to step 222, and this step 222 In the same way as in step 202, PL
It is checked whether or not L is locked to the SAT signal, and when it is locked, the process proceeds from step 222 to step 223, and in this step 223, a predetermined time limit (for example, 5 minutes) is executed after step 213 is executed. ) Has passed, and if not, the process returns from step 223 to step 221. In this way, when the predetermined time limit has not elapsed since the execution of step 213, steps 221-223 are repeated. Therefore, P
The call channel is promoted by LL30, and AF
The call circuit is held by the C circuit 50, and the call mode is continued on the call channel.

Then, when the reception level of the signal SRX from the base station becomes smaller than the specified value in this call mode, this is detected in step 221, and the process proceeds from step 221 to step 231. Further, when the SAT signal is unlocked in the call mode, this is detected in step 222, and the process proceeds from step 222 to step 231. In addition, if the time limit has expired while in call mode, this is step 2
23, the process proceeds from step 223 to step 231.

Then, in step 231, as in step 141, the power of the circuits 32 to 35 of the PLL 30 is turned on to bring the PLL 30 into the operating state, and the frequency divider circuit 33 is provided with the AFC circuit 50 so far. The frequency division ratio N corresponding to the held channel is set, and the power supplies of the circuits 53, 54, and 58 of the AFC circuit 50 are turned off to bring them into a non-operating state. Therefore, from this time, the original call channel is in a state of being promoted by the PLL 30. Then, thereafter, the process returns to step 202.

Thus, in the call mode, the PLL
When the call channel is promoted by 30, the call channel is held by the AFC circuit 50.
The call mode continues with the circuit 50 holding the call channel. However, in this call mode, the PLL 30 is activated and the reception state of the signal SRX from the base station is checked every predetermined period, and if the reception state is stable, the AFC circuit 50 determines that the communication channel The state of holding is executed again.

Then, when the SAT signal is unlocked in such a call mode, this is the step 2
22 or step 202, the process proceeds from step 222 to step 231, 202 or from step 202 to step 241. In this step 241, is the SAT signal unlocked for, for example, 5 seconds or more? If it is less than 5 seconds, the process returns from step 241 to step 202. If it is 5 seconds or more, the process proceeds from step 241 to step 290, and this step 290 is executed.
At, enter standby mode. In this standby mode, step 102 and subsequent steps of the routine 100 are executed.

Thus, according to the routine 200, PL
When the call channel is promoted by L30, the call channel is held by the AFC circuit 50 and the AF
The call mode is continued while the C circuit 50 holds the call channel. However, in this call mode, the PLL 30 is activated and the reception state of the signal SRX from the base station is checked every predetermined period, and if the reception state is stable, the AFC circuit 50 determines that the communication channel The state of holding is executed again.

In the above description, the present invention is applied to a mobile phone, and one of a plurality of channels is selected for a call such as a transceiver or a cordless phone handset. The present invention can be applied to any transmitter / receiver that performs the above operation, or any receiver that selects a reception frequency by a synthesizer circuit to perform reception.

[0055]

According to the present invention, the channel is changed and promoted by the PLL 30, and when the channel is promoted, the voltage VCEN obtained from the demodulation circuit 18 at the time of the promotion is thereafter controlled by the AFC circuit 50. PLL30 as standard
Since the channel that has been promoted is retained, the power of the circuits 32 to 36 of the PLL 30 can be turned off after the channel is promoted, and the current consumption can be reduced.

Further, each time the PLL 30 promotes a channel, the voltage VCEN at the time of the promotion is stored in the memory 57 and used as the reference voltage VREF when the AFC circuit 50 holds the channel. At that time, it is not necessary to adjust the reference voltage VREF. Further, the reference voltage VREF (= VCEN) of the AFC circuit 50 is updated each time the PLL 30 replenishes the channel according to the surrounding condition at that time, so that the reference voltage VREF (= VCEN) can be adjusted with respect to changes over time and temperature. No need to do.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of the present invention.

FIG. 2 is a flowchart showing a part of an example of a processing routine in the present invention.

FIG. 3 is a flowchart showing an example of a continuation of the routine of FIG.

FIG. 4 is a flowchart showing another example of the processing routine in the present invention.

FIG. 5 is a system diagram showing an example of a mobile phone.

FIG. 6 is a diagram showing an example of FM demodulation characteristics.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmitting / receiving antenna 10 Reception circuit 13 1st mixer circuit 14 1st intermediate frequency amplifier 15 2nd mixer circuit 16 2nd local oscillation circuit 17 2nd intermediate frequency amplifier 18 FM demodulation circuit 20 Transmitting circuit 22 PLL 23 VCO 24 Mixer circuit 30 PLL 31 VCO 32 Prescaler 33 Variable frequency divider circuit 34 Phase comparison circuit 35 Oscillation circuit 36 Charge pump circuit 37 Loop filter 40 Microcomputer 50 AFC circuit 53 Voltage comparison circuit 54 Charge pump circuit 55 Low-pass filter 56 A / D converter 57 Memory 58 D / A converter

Claims (5)

[Claims] 1. A receiving circuit for selecting and receiving one of a plurality of channels, a VCO, a mixer circuit for frequency-converting a received signal into an intermediate frequency signal by an oscillation signal of the VCO, A super-heterodyne receiving circuit is configured by providing a demodulation circuit that demodulates the intermediate frequency signal from the mixer circuit, a variable frequency dividing circuit to which the oscillation signal is supplied, and a frequency dividing signal of the variable frequency dividing circuit. And a phase comparison circuit that compares the phase of the reference frequency signal and a loop filter to which the output signal of the phase comparison circuit is supplied, and the output voltage of the loop filter is supplied to the VCO as its control voltage. And a storage circuit that stores a voltage obtained by frequency-discriminating the intermediate frequency signal, and a voltage obtained by frequency-discriminating the intermediate frequency signal. , And a voltage comparison circuit that compares the voltage stored in the storage circuit with each other, and supplies the output voltage of the voltage comparison circuit to the VCO.
When the FC circuit is configured and one of the plurality of channels is selected for reception, the frequency division ratio corresponding to the channel intended for this reception is set in the variable frequency division circuit to set the above-mentioned purpose. Select the channel you want to use, and if the PLL prompts for the desired channel,
A receiving circuit in which the PLL is deactivated and the AFC circuit is activated so that the AFC circuit holds the channel promoted by the PLL. 2. The receiving circuit according to claim 1, wherein when the AFC circuit holds the channel promoted by the PLL, the receiving state is checked every predetermined period, and as a result of this check, A receiving circuit configured to set the AFC circuit to a non-operating state and to set the PLL to an operating state to receive the original channel when the receiving state is out of a prescribed state. 3. The receiving circuit according to claim 1 or 2, wherein the demodulation circuit is an FM demodulation circuit, and an output signal of the FM demodulation circuit is supplied to a low pass filter to obtain the frequency discriminated voltage. The receiving circuit that did. 4. The receiving circuit according to claim 1, wherein the frequency-discriminated voltage is A / D converted and supplied to the storage circuit, and the storage circuit includes: A receiving circuit having a D / A converter for D / A converting the stored voltage and supplying the voltage to the voltage comparison circuit. 5. The receiving circuit according to claim 1, further comprising a transmitting circuit, to which the oscillation signal of the VCO is supplied as a local oscillation signal to form a transmitting / receiving device. The receiving circuit that did.