JPH06252750A - Reset control signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a clock circuit able to prevent malfunction of an information processor or the like by providing a lock detection section monitoring a voltage at an input of a voltage controlled oscillator of a phase locked loop(PLL) to control a reset signal. CONSTITUTION:When a reference clock signal 16 is inputted to a phase comparator 11 at application of power, an output signal 17 of a clock circuit passes through a frequency divider 15 and is compared with the reference clock signal 16 at the phase comparator 11. A difference pulse being an output of the phase comparator 11 is fed back to an input of a voltage controlled oscillator 13 through a low pass filter 12. A lock detection section 14 detects an fed back error voltage. When a PLL is made stable and an input to the voltage controlled oscillator 13 is smaller than a predetermined voltage, the lock detection section 14 detects the lock state of the PLL to make a reset control signal 18 active. Thus, a reset signal at application of power is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the invention relates to a reference clock signal oscillation technique.

[0002]

2. Description of the Related Art A sine wave oscillator has a relatively stable oscillation frequency, but is not suitable for a circuit that requires a high frequency.
Therefore, in an information processing device such as a computer, a PLL (Ph
as Look Loop).

Further, in a reset signal generating circuit at the time of turning on the power of an information processing apparatus such as a computer, a method of turning off the reset signal at a certain time interval after turning on the power, after counting a certain number of pulses of a clock signal, There is a method of turning off the reset signal.

However, there are cases where the oscillation frequency is not actually stable even if a fixed time interval and a fixed number are counted. In addition, the oscillation frequency may not be stable due to noise from the outside. This causes malfunction of information processing devices such as computers.

[0005]

However, in the current PLL technology, the time until the oscillation frequency is stabilized by locking when the power is turned on is not constant. In the worst case, it may not be stable and may diverge. Therefore, the method of counting the fixed time or the fixed number of clock pulses and releasing the reset after the power is turned on as in the prior art may cause an abnormal operation of the system.

It is an object of the present invention to provide a clock circuit which prevents an erroneous operation of an information processing device or the like by judging an input of a voltage controlled oscillator of a PLL and controlling a reset signal. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

In the PLL, the oscillation frequency of the voltage controlled oscillator is controlled. When the PLL is operating stably, only a small voltage corresponding to the stationary phase error component generated by the difference between the free-running frequency of the voltage controlled oscillator and the reference frequency is applied to the input of this voltage controlled oscillator. However, when the power is turned on, the PLL is out of synchronization, and in an unstable state, a large voltage is applied to the input of the voltage controlled oscillator.

By utilizing this property, it is detected whether or not the input voltage of the voltage controlled oscillator exceeds a certain level, and this is used for controlling the reset signal such as turning off the reset signal when the power is turned on. .

[0009]

According to the above-mentioned means, the reset signal is turned on while the PLL is out of synchronization and a large voltage is applied to the input of the voltage controlled oscillator, so that the PLL is stable and the input of the voltage controlled oscillator is stable. The reset signal is turned off only when the voltage reaches a certain level. As a result, a stable signal can always be obtained even after the power is turned on, and malfunction of an information processing device such as a computer can be reduced.

[0010]

FIG. 1 shows the configuration of a clock circuit which is an embodiment of the present invention. The PLL is a closed loop servo mechanism including a phase comparator 11, a reduction filter 12, a voltage controlled oscillator 13, and the like. The lock detector 14 detects the input signal of the voltage controlled oscillator 13 and determines the locked state of the PLL. The frequency divider 15 divides the output of the voltage controlled oscillator 13 by a frequency division ratio that is arbitrarily determined. The reference clock signal 16 is a PLL input signal. The output 17 of the PLL becomes, for example, a clock input signal for a microprocessor, peripheral circuits and the like. Also, reset control signal 1
8 is an input signal of the reset signal generation circuit of the microprocessor, for example.

The operation in FIG. 1 will be described. When the reference clock signal 16 is input when the power is turned on, the reference clock signal 16 is output through the phase comparator 11, the low-pass filter 12, and the voltage controlled oscillator 13, and the output signal 17 passes through the frequency divider 15 for phase comparison. It is compared with the reference clock signal 16 in the instrument 11. The differential pulse, which is the output of the phase comparator 11, has the high-pass component removed by the low-pass filter 12, and then, again,
It feeds back to the input of the voltage controlled oscillator 13. The lock detection unit 14 detects the fed back error voltage. When the PLL becomes stable and becomes smaller than a certain voltage input to the voltage controlled oscillator, the lock detector 14 detects the locked state of the PLL and activates the reset control signal 18. In addition, the frequency division ratio of the frequency divider 15 is 1 / N
Then, the PL of the frequency N times the reference clock signal 16
The L output 17 will be obtained.

FIG. 2 shows a timing chart of the reset control signal 18 when the power is turned on and the reset signal 21 generated by the reset signal generating circuit or the like. Here, the reset signal generation circuit of the microprocessor, the reset signal generation circuit such as the processor peripheral circuit clock generation circuit, and the like keep the reset signal active after the power is turned on. However, when the reset control signal 18 is released, The reset signal 21 released in response to the falling edge of the reset control signal 18
Stands up.

FIG. 3 shows changes in the input voltage of the voltage controlled oscillator 13 when the power is turned on. Several ideal waveforms are shown with the time constant of the low-pass filter as a parameter. The voltage b32 is the input voltage of the voltage controlled oscillator 13 with the PLL locked. Since all the waveforms are converged to the voltage b32 with time, it is determined in a certain voltage range that the PLL is in the locked state.
This is done by confirming that the input voltage of 3 has settled. The lock detector 14 assumes a voltage a32 higher than the point b and a voltage c33 lower than the point b, and determines whether the input voltage of the voltage controlled oscillator 13 is within the voltage range. Then, the reset control signal is generated.
In such a case, the voltage a assumed above
The voltage 32 and the voltage c33 can be formed by a Zener diode or the like that obtains a constant voltage by utilizing the breakdown characteristic. In Figure 4,
A specific example of a PLL circuit provided with the lock detection unit of the above method will be shown. The lock detector 44 includes a voltage comparator a41, a voltage comparator b42, and a waveform shaping circuit 43. The voltage comparator a41 and the voltage comparator b42 determine whether or not the input voltage of the voltage controlled oscillator 13 is within the range of the voltage a31 and the voltage c33. The respective outputs of the voltage comparator a41 and the voltage comparator b42 are guided to the waveform shaping circuit 43, and their outputs become reset control signals.
Further, the reset signal generation circuit 45 is controlled by the reset control signal 18 to generate the reset signal 2
1 is a reset signal for peripheral circuits such as CPU and MPU.

FIG. 5 shows an embodiment of the waveform shaping circuit 43. In such a case, the output pulse of the waveform shaping circuit 43 becomes a plurality of pulses, and it is necessary to fill the gaps between the pulses into one large pulse before guiding the plurality of pulses to the reset control circuit. Therefore, the OR circuit 53
An integrating circuit 51 is placed at the output of the circuit to generate a voltage that fills the gap of the pulse, but an intermediate value is output to the voltage only by passing through the integrating circuit 51, so a Schmitt trigger
A waveform adjusting circuit 52 having hysteresis in the input of a type buffer or the like receives and shapes the waveform into a digital waveform.

FIG. 6 is an output waveform diagram of the voltage comparator a41, the voltage comparator b42, and the waveform shaping circuit 43 when the input voltage of the voltage controlled oscillator 13 converges while performing damping oscillation. In addition, a case is shown in which the output pulse 61 of the voltage comparator a41 and the output pulse 63 of the OR circuit 53 combined by the output pulse 62 of the voltage comparator b42 are a plurality of pulses. The integration circuit 51
Output 64 and the output 65 of the waveform adjusting circuit 52 are shown.
In such a case, the output 65 of the waveform adjusting circuit 52 falls near the threshold voltage of the falling portion of the output 64 of the integrating circuit 51.

FIG. 7 is a modification of FIG. A delay element 71 is arranged at the output of the lock detecting section 14, the reset control signal 18 is sent, and a time margin is provided for releasing the reset signal.

FIG. 8 is a modification of FIG. Focusing on the point that the input voltage of the voltage controlled oscillator 13 converges while performing damping oscillation, the number of voltage comparators of the lock detection unit 14 is reduced to one. Further, a delay element 61 is provided at the output of the voltage comparator 81 in order to send the reset control signal 18 and allow a time margin for releasing the reset signal.

FIG. 9 is a block diagram showing the principle of the reset signal generating circuit 45. Although not particularly limited, the reset signal generation circuit 45 uses the power-on reset circuit 93 that activates the reset signal when the power is turned on. Therefore, the reset signal generation circuit 45 keeps the reset signal active after the power is turned on, but when the reset control signal 18 is released, the reset signal 21 rises in response to the falling edge thereof. By providing the external switch circuit 91, the reset signal can be controlled by an external switch or the like. By using the reset signal generation circuit 45, the reset signal 21 can be controlled by the reset control signal 18, the external switch circuit 91, and the power-on reset circuit 93.

FIG. 10 shows an example in which the clock circuit of the present invention is used in a single-chip microcomputer. This single-chip computer is not particularly limited, but CPU 1, interrupt control circuit 2, 16k
Byte EEPROM 3, 16 kbyte ROM 4, 1 kbyte RAM 5, input / output circuit (timer 61, serial communication interface (SCI) 62, A / D
The converter 63, the first to ninth input / output ports 71 to 79, and the clock pulse generator (CPG) 8) are formed on one semiconductor substrate by a known semiconductor manufacturing technique. Such a single-chip microcomputer uses a ground level (Vs
s), power supply voltage level (Vcc) terminal, and other dedicated control terminals such as reset (RES) and standby (STB)
Y), mode control (MD0, MD1, MD2), interrupt terminal (NMI), clock input (EXTAL, XTA)
L) has a terminal. CPU1 and 16 kbyte EEPR
OM3, 16kbyte ROM4, 1kbyte RAM5,
Input / output circuit 6, first to ninth input / output ports 71 to 79
Are mutually connected by an internal bus 9 and read / write is performed under the control of the CPU 1. The internal bus includes an address bus, a data bus, a read signal, a write signal, a functional block selection signal, a system clock and the like.

The system clock is appropriately generated by the CPG with reference to a crystal oscillator (not shown) connected to the EXTAL terminal and the XTAL terminal. The interrupt control circuit 2 controls an interrupt request signal output from the input / output circuit (timer 61, serial communication interface (SCI) 62, A / D converter 63) and the ninth input / output port 79, and interrupts the CPU 1. Request.

The input / output port is also used for address bus output, data bus input / output, bus control signal input / output, interrupt request signal input, and the like. These combined functions are selected by the operation mode and software. For example, when the extended mode is selected as the operation mode, the first and second modes are selected.
The input / output port serves as an address bus output, the third input / output port serves as a data bus input / output, and the fourth port serves as a bus control signal input / output terminal, and an external memory (not shown) connected to the outside can be read / written.

The reset control signal generating circuit according to the present invention is the clock pulse generator (CPG) described above.
The reset signal is sent to the CPU 1 through the reset circuit 9.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Since the reset signal is released after the PLL oscillates at a stable frequency, cold reset of the system can be surely performed, and even if it takes time to synchronize due to noise etc. at power-on, the system Can be surely reset.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a PLL clock circuit according to the present invention.

FIG. 2 is a timing diagram showing a reset control signal at power-on and an operation of the reset signal.

FIG. 3 is a timing diagram showing the operating principle of the lock detection unit.

FIG. 4 is a principle configuration diagram of an embodiment of a PLL clock circuit according to the present invention.

5 is a principle configuration diagram of a waveform shaping circuit 43. FIG.

FIG. 6 is a waveform diagram showing outputs of a voltage comparator, an OR circuit, an integrating circuit, etc. when the input voltage of the voltage controlled oscillator converges while performing damping oscillation.

FIG. 7 is a principle configuration diagram of an embodiment of a PLL clock circuit according to the present invention.

FIG. 8 is a principle configuration diagram of an embodiment of a PLL clock circuit according to the present invention.

FIG. 9 shows a reset signal generation circuit 4 according to the present invention.
It is a principle block diagram of 5.

FIG. 10 is an example in which the clock circuit of the present invention is used in a single-chip microcomputer.

[Explanation of symbols]

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigezumi Matsui 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (4)

[Claims] 1. A lock circuit comprising a lock detector for monitoring a voltage input to a voltage controlled oscillator of a phase locked loop. 2. An information processing apparatus provided with a clock circuit according to claim 1, wherein the output of the lock detector is used for releasing a reset signal. 3. The clock circuit according to claim 1, wherein the lock detector is realized by at least one voltage comparator. 4. A clock circuit according to claim 1, wherein a delay element is provided at the output of said lock detector.