JPH06252745A - Nonvolatile counter - Google Patents

Abstract

PURPOSE:To provide a nonvolatile counter by which the reliability of stored data are always secured. CONSTITUTION:A counter section 41 consists of 200 bits, data are written sequentially by one bit each time a distance of 1km elapses and the data are entirely erased for each 200km. An integration section 42 has a storage area by 3 words (integration values A-C) to the same data. One word of a flag section 43 is prepared for each of 3-lines of data for rewrite (integration values A-C) of the integration section 42 and one word of the flag section 43 is provided for data erasure of the counter section 41. Then the erasure for carry to the counter section 1 and rewrite to the integration section 42 are implemented only after a relevant flag word is written. Thus, even when the operation of data write/ erasure by the counter section 41 and the integration section 42 is interrupted due to various reasons midst of the operation, data and a flag word are retrieved at application of power to read correct stored data at interruption of power to obtain final data surely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile counter that updates the data stored in an electrically erasable / writable nonvolatile memory element based on a predetermined count value and performs a count operation. In particular, the present invention relates to a non-volatile counter characterized by a data updating method.

[0002]

2. Description of the Related Art Conventionally, the problems to be solved by the invention
For example, an electrically erasable / writable non-volatile storage element such as an EEPROM is used as a means for saving data when the power is turned off in a system having no backup power supply. As an example, an EEPROM (an EEPROM is used as a representative of a nonvolatile memory element in the following description) is arranged in parallel with a counting circuit that counts the number of pulses, and when the value of the counter changes, the value is stored in the nonvolatile memory. Non-volatile counters that write to devices are known.

However, in order to secure the authenticity of the stored data in the EEPROM, it is necessary to consider the following two points. The first point is that it usually takes a few ms or more to write / erase data to / from the EEPROM. If the power is turned off or noise is superimposed during this operation and the data write / erase operation is interrupted, the data becomes indeterminate and the reliability of the stored data is extremely reduced. If the EEPROM has a bit failure,
The determination of whether the data is 1 or 0 depends only on the data processing method. Then, as a method of improving this, for example, a plurality of (for example, three) storage areas are provided for one type of data, and three storage areas are provided.
It is a method of judging the data by the majority vote of one data.

Another point is that the number of rewriting times of the EEPROM is limited. At present, the number of rewrites is about tens of thousands in consideration of reliability, and if data is rewritten over this number of rewrites, there is a high possibility that the EEPROM will suffer a bit failure, and the reliability of the stored data is extremely reduced. To do. As a method of improving this, for example, a proposal has been made to provide a plurality of storage areas for one type of data, change the storage area each time rewriting to reduce the number of rewrites per bit, and increase the reliability of the stored data. Has been done.

The present invention has been made in view of such circumstances, and an object thereof is to provide a non-volatile counter capable of always ensuring the authenticity of stored data, and to provide various non-volatile counters during a write / erase operation. Non-volatile counter that always secures the reliability of the stored data even if the operation is interrupted due to the reason, and the reliability of the stored data is secured when the number of rewrites exceeds the limit limited by the process capability. (EN) Provided are a non-volatile counter and a non-volatile counter capable of always ensuring the credibility of stored data even when the operation is interrupted during a write / erase operation or the number of times of rewriting exceeds the limit due to process capability.

[0006]

A non-volatile counter according to claim 1, which is formed to achieve this object, is an electrically erasable / writable non-volatile memory element as shown in FIG. A non-volatile counter that updates the data stored in the memory based on a predetermined count value and performs a counting operation, wherein the non-volatile memory element is provided in three or more for one type of data. Areas and flag word storage areas provided corresponding to the respective data storage areas, and when rewriting data in the data storage areas, predetermined flags are provided in the corresponding flag word storage areas. Rewriting means for rewriting data after writing a word, and erasing for erasing the written flag word after the rewriting of data by the rewriting means is completed Characterized by comprising a stage, a.

On the other hand, the non-volatile counter according to a second aspect of the present invention, as illustrated in FIG. 2, uses data stored in an electrically erasable / writable non-volatile storage element based on a predetermined count value. A non-volatile counter for updating and performing a counting operation, wherein the non-volatile storage element is provided for each section divided into a plurality of sections with a maximum count digit number in a digit order,
A data storage area for upper digits provided for a section corresponding to a predetermined upper digit and a section corresponding to a predetermined lower digit are provided, and data is sequentially written bit by bit in accordance with an event for each predetermined count value. And a flag word storage area provided corresponding to the lower digit data storage area and having a predetermined number in the lower digit data storage area. When data is written in the cell corresponding to the carry number of and is erased for carry, after writing a predetermined flag word in the flag word storage area, the data in the data storage area of the lower digit corresponding section is written. And carry means for erasing the data, and erasing means for erasing the written flag word after the data erasing by the carry means is completed. And it said that there were pictures.

Further, as shown in FIG. 3, the non-volatile counter according to a third aspect of the invention stores data stored in an electrically erasable / writable non-volatile storage element based on a predetermined count value. A non-volatile counter for updating and performing a counting operation, wherein the non-volatile storage element is provided for each section divided into a plurality of sections with a maximum count digit number in a digit order,
For a predetermined upper digit corresponding division, three or more upper digit data storage areas are provided for one type of data, and for a predetermined lower digit corresponding division, one bit depending on an event for each predetermined count value. A lower digit data storage area composed of a plurality of cells for writing data one by one, an upper digit flag word storage area provided corresponding to each of the upper digit data storage areas, and And a lower digit flag word storage area provided corresponding to the lower digit data storage area, and when rewriting the data in the upper digit data storage area, the corresponding upper digit flag word After writing a predetermined upper digit flag word in the storage area, rewriting means for rewriting data, and after the data rewriting by the rewriting means ends, In the upper digit erasing means for erasing the entered upper digit flag word, and in the data storage area of the lower digit corresponding section, data is written in cells corresponding to a predetermined carry number, and erased for carry. At this time, after writing a predetermined lower digit flag word in the lower digit flag word storage area, carry means for erasing data in the lower digit data storage area and data erasing by the carry means. Is completed, the erasing means for upper digits erases the written flag word for lower digits.

[0009]

The non-volatile counter of the present invention having the above-mentioned structure is for performing the count operation by updating the data stored in the electrically erasable / writable non-volatile memory element based on the predetermined count value. Yes, and is characterized by updating data by erasing / writing.

According to the nonvolatile counter of the first aspect, one type of data is written in each of the three or more data storage areas, and when the data in the data storage area is rewritten, the rewriting means sets each data. After writing a predetermined flag word in the flag word storage area corresponding to the storage area, the data is rewritten, and after the data rewriting by the rewriting means is completed, the erasing means erases the written flag word.

In the past, for example, there were three data storage areas, and it was possible to detect and correct the garbled data of one data by the majority decision of the three data, but the rewriting of the data to be rewritten second. If a problem such as power-off occurs during operation, if all three data are different, it cannot be corrected.

On the other hand, according to this non-volatile counter, when the power is turned on, the data and the flag word in the data storage area are searched, and the correct stored data is read when the power is turned off, thereby obtaining a reliable final data. It is possible. Therefore, even if the data write / erase operation in the data storage area is interrupted for various reasons, the reliability of the stored data can be always ensured.

On the other hand, according to the nonvolatile counter of the second aspect, in the lower digit data storage area provided for a section corresponding to a predetermined lower digit, each cell is responded to an event for each predetermined count value. The data is sequentially written bit by bit. Then, when data is written in cells corresponding to a predetermined carry number in the lower digit data storage area and erased for carry, the carry means writes a predetermined flag word in the flag word storage area. After that, the data in the lower digit data storage area is erased, and after the data has been erased by the carry means, the erase means erases the written flag word.

Therefore, for example, it is adopted in an odometer, and the data storage area for the lower digit is composed of 200 bits.
If data is sequentially written every 1 km with m as the predetermined count value, in this case, all erasing is performed every 200 km, and the number of rewriting is once every 200 km. This is because the number of rewriting of the least significant digit is 10 when counting up to 200 km per 1 km in binary code, for example.
The number of times of rewriting is reduced compared with 0 times. Also,
Even if the lower digit data storage area is not composed of 200 bits, the effect of reducing the number of rewrites is sufficient even if it is about 50 bits or 10 bits.

As described above, even when the number of times of rewriting exceeding the limit limited by the process capability is required, it can be dealt with. For example, if the lower digit data storage area is 200
When it is composed of bits, it has substantially 100 times the counting ability as in the case of the binary code, which contributes to securing the credibility of the stored data.

Further, even if the data write / erase operation for the lower digit data storage area is interrupted for various reasons, the lower digit data and the flag word are searched when the power is turned on. By reading the correct stored data when the power is off, it is possible to obtain reliable final data.
Therefore, also in this respect, the authenticity of the stored data can be secured.

According to the non-volatile counter of the third aspect, one kind of upper digit corresponding data is written in each of the three or more upper digit data storage areas provided for a predetermined upper digit corresponding section. , The lower digit data storage area provided for the division corresponding to the predetermined lower digit,
One bit of data is sequentially written in each cell in response to an event for each predetermined count value.

Then, data is written in cells corresponding to a predetermined carry number in the lower digit data storage area,
When erasing for carry, the carry means erases the data in the lower digit data storage area after writing a predetermined flag word in the flag word storage area, and after the data erase by the carry means is completed. , The lower digit erasing means erases the written flag word.

On the other hand, when rewriting the data in the upper digit data storage area, the rewriting means writes a predetermined upper digit flag word in the upper digit flag word storage area corresponding to each data storage area. After the data is rewritten and the data rewriting by the rewriting means is completed, the upper digit erasing means erases the written upper digit flag word.

As described above, when the upper digit data and the lower digit data are both rewritten or erased for carry, they are performed only after writing the corresponding flag words. Therefore, even if the operation is interrupted for various reasons during the data write / erase operation in the upper digit or lower digit data storage area, the corresponding data and flag word are searched for when the power is turned on and the power is turned on. By reading the correct stored data when it is turned off, it is possible to obtain reliable final data. Therefore, the authenticity of the stored data can always be ensured.

Further, as for the lower digit where the number of times of rewriting is inevitably increased, like the nonvolatile counter of the above-mentioned claim 2, even when the number of times of rewriting exceeding the limit limited by the process capability is requested, it can be dealt with. , Contribute to ensuring the authenticity of stored data. As described above, this non-volatile counter can always ensure the reliability of the stored data even if the operation is interrupted during the write / erase operation or the number of times of rewriting exceeds the limit due to the process capability. .

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 4 is a schematic block diagram of a system in which a nonvolatile counter according to an embodiment of the present invention is applied to an electronic odometer (odometer). This system is a well-known CP
A U10, a ROM 20, a RAM 30, and an EEPROM 40 as an electrically erasable / writable non-volatile storage element are configured as the center of the electronic control unit, and a signal from the vehicle speed sensor 50 is input to the CPU 10 via an input circuit 60. Is input, and the output from the CPU 10 is displayed on the display 80 via the drive circuit 70.

The vehicle speed sensor 50 generates n pulses (n ≧ 1) every rotation of the tire. The input circuit 60 inputs a signal from the vehicle speed sensor 50 and performs waveform shaping and noise processing. The CPU 10 counts the number of pulses input from the input circuit 60 and stores it in a predetermined address of the RAM 30.

Further, the CPU 10 rewrites the data of the predetermined address of the EEPROM 40 each time the data in the RAM 30 reaches a preset value. Further CPU 10
Converts the above data into data required by the display 80 and transfers the data to the drive circuit 70. The ROM 20 contains a program for controlling the system.

FIG. 5 shows a memory map in the EEPROM 40. The EEPROM 40 includes a counting unit 41 and an integrating unit 4
2, the flag unit 43 is provided, and in the memory map example in FIG. 5, the counting unit 41 is 5 bits × 40 words of 200 bits, and the integrating unit 42 is 5 bits × 12 words of 6 bits.
The 0 bit and the flag portion 43 are composed of 20 bits of 5 bits × 4 words. The shaded bits in FIG. 5 indicate unused bits.

When the above configuration is used for an odometer, a vehicle speed pulse signal of several shots per one rotation of the tire is input to the input circuit 60 as a sensor signal generated by the vehicle speed sensor 50, and the input circuit 60 outputs a square wave. Waveform is shaped into CPU
Input to 10. The CPU 10 increments the “pulse count value” of the predetermined address in the RAM 30 by “1” each time the vehicle speed pulse signal is input. Also CPU
Reference numeral 10 compares the pulse count value with the “count value per 100 m” already stored in the ROM 20, and if they match, increments the “100 m unit count value” at a predetermined address in the RAM 30 by “1”. .

Here, the "count value per 100 m" is 1
It is the number obtained by dividing the value of 00 m by the circumference length of the standard tire by the number of pulses per rotation. The resolution of a normal odometer is 100 m. Further, the CPU 10 stores the “100 m unit count value” in the ROM 20 as “1 k”.
"Count value per m", and if they match, RAM3
The "1 km unit count value" of the predetermined address within 0 is incremented by 1. At the same time, the EEPROM 40 described later
The rewriting sequence of is performed.

The counting unit 41 is composed of 200 bits as described above, and every time 1 km from 1 km to 199 km elapses, 1-bit data is sequentially written (hereinafter, such data is embedded code. All data will be erased every 200 km.

The reason why the embedded code data method is adopted is to reduce the number of rewritings per bit, and in this case, the number of rewritings of each bit at the completion of one million km travel is 5000 times per bit. Become. At the time of reading, the write data is read in order from RK _1-1 , and the unwritten bit is searched for. At this time, a failure of 1 bit or more can be relieved by taking a majority decision of continuous read data of 5 bits or more.

A specific example of this majority vote processing will be described. First, the reading process in the normal state will be described with reference to FIG. The read rules are the following four. The search starts from the least significant bit (LSB) and sequentially shifts to the most significant bit (MSB).

The position where the number of “0” becomes 3 or more (4 or more does not actually exist) is set as the final position. The counter is incremented by 1 for each shift. The count value read in the above sequence, and R
When the value of AM30 is different, the value of RAM30 is set to the true value.

Then, in order to adopt the above rule, L
Virtual bits for data processing are set only in the lower two bits of SB and the upper two bits of MSB. 2 bits of "1" are set in the lower data processing virtual bits of the LSB, and "0" is set in the upper data processing virtual bits of the MSB.
Is set to 2 bits.

As shown in FIG. 6, starting from the case where the reading window for 5 consecutive bits includes 2 bits of the lower data processing virtual bits of the LSB, 2 bits of the higher data processing virtual bits of the MSB are started. It ends when it includes minutes. In addition, in the present embodiment, the counting unit 41 erases every count value 200, so that it is not written in the MSB.

Next, the reading process when there is an abnormal bit is shown in FIG.
Will be described with reference to. There are the following two assumed modes of abnormality. (B) "1" failure ... There are bits that cannot be erased. (B) "0" failure ... There is a bit that cannot be written.

First, in the case of the "1" failure of (a) above, as shown in FIG. 7, it exists three bits ahead of the final write bit from the case immediately next to the final write bit. Until then, the count by shifting the reading window is normal (R
It is 1 larger than the value of AM30). Also, "1"
Failure is 4 bits (or more) of last written bit
If it exists first, it will be equal to the normal value.

Further, in the case of the "0" failure of the above (b), as shown in FIG. 7, from the case where it exists in the final write bit itself to the case where it exists 2 bits after the final write bit. Is smaller than the normal value (value of the RAM 30) by 1 by the shift of the reading window. Also,
If a "1" fault exists 3 bits (or more) after the last written bit, then it equals the normal value.

In this way, the normal value and +1 and -1, respectively.
If the result is different, the value of the RAM 30 is written according to the above rule. However, when the power is turned on, the EEPROM follows the procedure from the above rules to.
The value of 40 is read and the value is stored in the RAM 30.

On the other hand, the integrating section 42 is composed of BCD code data of upper 3 digits and embedded code data of lower 1 digit. Further, it has a storage area for each 3 words of the same data. This is to make a majority decision of 3 words in order to increase the credibility of the data. The upper 3 digits are BC
The reason for using the D code is to facilitate conversion into the data for the numerical segment of the display.

The reason why the lower 1 digit (in this case, the order of 100 km) is the embedded code data is 10
This is to reduce the number of rewrites after the completion of traveling of 0,000 km.
Writing can be done bit by bit, but erasing is done in one row (4 words)
You can only do it one by one. If all 4 digits are composed of BCD code, it is necessary to rewrite every 100 km.
The number of rewrites at the completion of running of, 000,000 km is 50 per 1 bit in the least significant bit of the least significant digit where rewriting is performed the most.
It is 00 times.

On the other hand, when the lowest digit is composed of embedded code data, one bit is embedded every 200 km up to 800 km and erased every 1000 km. The number of times is 1000 times per bit (a comparison of both is shown in FIG. 6).

Rewriting of each line is performed one line at a time. In the following description, for each of the three rows of the integrating unit 42, as shown in FIG. 5, RS _1-1 to RS
_1-4 are referred to as integrated values A, similarly RS _2-1 to RS _2-4 are referred to as integrated values B, and RS _{3-1 to} RS _3-4 are referred to as integrated values C.

Further, the flag section 43 is prepared for each word for rewriting each data (integrated values A to C) of the three rows of the integrating section 42 and for one word for erasing the data of the counting section 41. In FIG. 5, the flag word RF _1-1 is for erasing the counting unit 41,
RF _1-2 is for rewriting integrated value A, RF _1-3 is for rewriting integrated value B, and RF _1-4 is for rewriting integrated value C.

First, the flag word R for erasing the counting section 41
In F _1-1 , all 1's are written before erasing the counting data every 200 km, and the flag word RF _1-1 is erased after confirming the erasing of the counting data. By this operation, even if a problem such as power failure occurs immediately before or during the erase operation of the counting section data and the data becomes indeterminate, the flag word RF _1-1 that has already been written is searched when the power is turned on. By doing so, it is possible to know the occurrence of trouble.

Even if the same trouble occurs when writing or erasing the flag word RF _1-1 , the reliability of the data can be confirmed by searching the counting section data which has already been erased or written. Saved. As described above, when the power is turned on, the counter data and the flag word RF are
By searching _1-1 , it is possible to read the correct saved data when the power is off.

Next, the integrated value rewriting flag word RF _1-2
～RF _1-4 Similarly, write all 1's to rewrite before each integrated value A through C, it is erased after rewriting completion of the integration unit 42 data. The integrating unit 42 uses only the three words of the integrated values A to C,
It is possible to detect and correct the garbled data of one word by the majority decision, but it is impossible to correct when the data becomes different for all three words. If a trouble such as power-off occurs during the rewriting operation of the word (for example, integrated value B) to be rewritten second, the three words may have different data.

On the other hand, when the power is turned on, the integration unit 42 data and the integration value rewriting flag word RF of the flag unit 43 are rewritten.
By searching _{1-2 to} RF _1-4 , it is possible to read the correct stored data when the power is off. The reason why each flag word RF _{1-1 to} RF _1-4 of the flag unit 43 is composed of 5 bits is to relieve its own bit failure.

7 and 8 are flowcharts of the rewriting sequence of the EEPROM 40 described above. FIG. 7 is a flowchart showing the rewriting sequence in the normal time.
In step 100 (hereinafter, simply referred to as S100. The same applies hereinafter), the count value data is read from the counter 41, and S1 is read.
At 10 and 120, the result is incremented and written in the counting unit 41 while performing the majority decision process in consideration of the bit failure. Then, in S130, it is determined whether or not the distance is 200 km (that is, whether or not all the data is embedded in the counting unit 41). If the distance is not 200 km, S1 is determined.
At 40, the integrated values A to C are read out, and the process is once terminated.

On the other hand, when the value reaches 200 km in S130 (when all the data is embedded in the counting unit 41), S
In step 150, the integrated values A to C are read, the majority process is performed in consideration of the bit failure, and the result is incremented. Then, first, in S160, the flag word RF _1-1 for erasing the counting unit 41 is written, and then in S170, the entire counting unit 41 is erased.

The integrated values A to C are rewritten in subsequent S180 to S230. First, the integrated value A is rewritten after the flag word RF _1-2 for rewriting the integrated value A is written (S180, 190). ) Similarly, after writing the flag word RF _1-3 for rewriting the integrated value B, rewriting the integrated value B (S200, 210), after writing the flag word RF _1-4 for rewriting the integrated value C Then, the integrated value C is rewritten (S220, 230).

After that, all the flag words RF _{1-1 to} RF _1-4 of the flag section 43 are erased, and this processing is ended. On the other hand, FIG. 8 is a flowchart showing a rewriting sequence when the power is turned on. First, in S300, the flag unit 4
The values (flag values) of the respective flag words RF _{1-1 to} RF _1-4 of 3 are read, and in S310 to S340, whether the counting unit 41 is erasing (S310) or whether the integrated value A is being rewritten. (S320), whether the integrated value B is being rewritten (S3)
30), and it is determined whether the integrated value C is being rewritten (S340).

Then, in the case of all negative determinations in S310 to S340, that is, the counting unit 41 and the integrating unit 42.
If no interruption is being made during erasing or rewriting, the count value is read out in S350 and the integrated values A to C are read out in S360, and the process is temporarily terminated.

On the other hand, when an affirmative determination is made in S310 to S340, the processing subsequent to each case is S370 to S40.
After performing the process of 0, in each case, the process of S410 and subsequent steps is performed. First, when the counting unit 41 is erasing (S31
In the case of 0: YES, the integrated values A to C are read, the majority process is performed, and the result is incremented (S37).
0). When the integrated value A is being rewritten (S320: YE
Also in S), the integrated values A to C are read, a majority process is performed, and the result is incremented (S380). In this case, since the integrated value A is being rewritten and only the integrated value A is uncertain, it can be confirmed by majority processing of the integrated values A to C.

On the other hand, when the integrated value B is being rewritten (S33
0: YES), the integrated values A to C are read and the integrated value C
Is incremented and then a majority process is performed (S39
0). In this case, the integrated value B is being rewritten and is indeterminate. Further, the integrated value A is confirmed and the rewriting is completed.
The integrated value C is fixed and before rewriting. Therefore, the integrated value C
Can be determined by incrementing and performing majority processing of the integrated values A to C.

When the integrated value C is being rewritten (S34
If 0: YES), the integrated values A to C are read out and a majority process is performed (S400). In this case, the integrated value C is being rewritten and is indeterminate. Further, since the integrated values A and B are fixed, they can be fixed simply by performing a majority process of the integrated values A to C.

After this, the processing of S410 to S490 is
Since it is the same as the processing of S160 to S240 in the flowchart (FIG. 9) showing the above-described normal rewriting sequence, description thereof will be omitted. It should be noted that the present embodiment relates to the invention according to claim 3, and a brief description of the correspondence with each means shown in FIG. 3 will be made when S160 in FIG.
The execution of the processing of 170 functions as a carry means, and S180
Execution of the process of S230 works as a rewriting means. Also,
Execution of the process of S240 works as an erasing unit for upper digits and an erasing unit for lower digits.

On the other hand, the counting unit 41 in FIG. 5 corresponds to the lower digit data storage area, and the integrating unit 42 corresponds to the upper digit data storage area. Accordingly, the flag word RF _1-1 for erasing the counting section of the flag section 43 functions as a flag word for lower digits, and the integrated value rewriting flag words RF _{1-2 to} RF _1-4.
Acts as the flag word for the upper digits.

The present invention is not limited to the embodiments as described above, and can be carried out in various modes without departing from the scope of the present invention. Although the EEPROM 41 is used as a representative of the non-volatile storage element in the above-described embodiment, other storage elements such as a floppy disk and a magnetic tape which may cause data destruction during data rewriting. If it can be applied effectively.

[0058]

As described above in detail, according to the non-volatile counter of the first aspect, even if the data write / erase operation in the data storage area is interrupted due to various reasons. , Can always ensure the authenticity of the stored data.

Further, according to the non-volatile counter of the second aspect, even when the number of rewrites exceeding the limit limited by the process capability is requested, it can be dealt with, and it contributes to secure the credibility of the stored data. , Even if the operation of writing / erasing data in the lower digit data storage area is interrupted, the lower digit data and flag words are searched when the power is turned on and the correct saved data is read when the power is turned off. By doing so, it is possible to obtain reliable final data. Therefore, also in this respect, the authenticity of the stored data can be secured. Further, according to the nonvolatile counter of the third aspect, writing / writing of data in the data storage area for the upper digit or the lower digit is performed.
Even if the operation is interrupted during the erase operation, it is possible to obtain reliable final data by searching the corresponding data and flag word when the power is on and reading the correct stored data when the power is off. Therefore, the authenticity of the stored data can always be ensured. In addition, for the lower digit, which inevitably has a large number of rewrites, even if the number of rewrites exceeding the limit limited by the process capability is requested, it is possible to contribute to ensuring the authenticity of the stored data.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a nonvolatile counter according to claim 1.

FIG. 2 is a block diagram illustrating a basic configuration of the nonvolatile counter according to claim 2;

FIG. 3 is a block diagram illustrating a basic configuration of the nonvolatile counter according to claim 3;

FIG. 4 is a schematic block diagram of a system in which a nonvolatile counter according to an embodiment of the present invention is applied to an electronic odometer.

FIG. 5 is an explanatory diagram showing a memory map in the EEPROM of this embodiment.

FIG. 6 is an explanatory diagram showing a normal reading process in a specific example of the read data majority decision process.

FIG. 7 is an explanatory diagram showing a read process when an abnormal bit exists in a specific example of the read data majority decision process.

FIG. 8 is an explanatory diagram showing an example of a comparison of the number of times of rewriting of BCD code and embedded code in the case of forming data.

FIG. 9 is a flowchart showing a rewriting sequence in a normal time.

FIG. 10 is a flowchart showing a rewriting sequence when the power is turned on.

[Explanation of symbols]

A to C ... Accumulated value, RF _1-1 ... Flag word for erasing counting section, RF _{1-2 to} RF _1-4 ... Flag word for rewriting accumulated value, 41 ... Counting section, 42 ... Accumulation section, 43 ... Flag section , 50 ... Vehicle speed sensor, 60 ... Input circuit, 70 ...
Drive circuit, 80 ... Indicator

Claims (3)

[Claims] 1. A non-volatile counter that updates the data stored in an electrically erasable / writable non-volatile memory element based on a predetermined count value and performs a counting operation. The element has three or more data storage areas for one type of data, and flag word storage areas provided corresponding to the respective data storage areas, and the data of the data storage area When rewriting, the rewriting means for rewriting the data after writing a predetermined flag word in the corresponding flag word storage area, and the written flag word after the data rewriting by the rewriting means are completed. A non-volatile counter, comprising: an erasing unit for erasing. 2. A non-volatile counter that updates the data stored in an electrically erasable / writable non-volatile memory element based on a predetermined count value and performs a count operation. An element is provided for each division into which the maximum number of digits is divided into a plurality of divisions in order of digits, and corresponds to the upper digit data storage area provided for the division corresponding to the predetermined higher digit and the predetermined lower digit. It corresponds to the lower digit data accommodating area, which is provided for each section and is composed of a plurality of cells for sequentially writing data bit by bit according to an event for each predetermined count value, and the lower digit data accommodating area. And a flag word storage area provided in the lower digit data storage area, and data is written in a cell corresponding to a predetermined carry number in the lower digit data storage area and erased for carry. In this case, after writing a predetermined flag word in the flag word storage area, carry means for erasing the data in the data storage area of the lower digit corresponding section, and the data erasing by the carry means are completed. And a erasing unit that erases the written flag word later. 3. A non-volatile counter that updates the data stored in an electrically erasable / writable non-volatile memory element based on a predetermined count value and performs a count operation. An element is provided for each division into which the maximum number of digits is divided into a plurality of divisions in order of digits, and for a given upper digit corresponding division, three or more upper digit data storage is provided for one type of data. As for the area and the predetermined lower digit corresponding division, a lower digit data storage area composed of a plurality of cells for sequentially writing data bit by bit according to an event for each predetermined count value, and each of the above upper digits An upper digit flag word storage area provided corresponding to the digit data storage area, and a lower digit flag word storage area provided corresponding to the lower digit data storage area. At the same time, when rewriting the data in the upper digit data storage area, a rewriting means for rewriting the data after writing a predetermined upper digit flag word in the corresponding upper digit flag word storage area, respectively. After the data rewriting by the rewriting means is completed, the upper digit erasing means for erasing the written upper digit flag word and the predetermined digit carry number in the data storage area of the lower digit corresponding section When data is written in a cell and erased for carry, after writing a predetermined lower digit flag word in the lower digit flag word storage area,
Carry means for erasing the data in the lower digit data storage area, and lower digit erasing means for erasing the written lower digit flag word after the data erasing by the carry means is completed. A non-volatile counter characterized by being provided.