JPH06252741A - Compound semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To adopt a high power supply voltage for a integrated circuit device and to avoid the effect of power supply voltage fluctuation by providing a 2nd load resistor in parallel with a drive FET(field-effect transistor(TR)). CONSTITUTION:A 1st load resistor 11 is connected in series with a source and a drain of a drive FET 1 being an n-channel enhancement PN junction FET to form an E/R DCFL circuit (direct coupled FET logic circuit). A 2nd load resistor 12 is connected in parallel with the drive FET 1. Since a logic 1 level is extracted as a voltage dividing a power supply voltage, even when an, e.g. 2V generally used for a silicon semiconductor integrated circuit is adopted for a power supply voltage, an output voltage is selected to be 1.0V or below. Furthermore, a power supply voltage is selected to be within a permissible voltage changing rate to avoid injection of positive holes being a problem in the FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor integrated circuit device, particularly a direct coupling type FET (field effect transistor).
Logic (Direct Coupled FET Logic) circuit (hereinafter DCFL
Circuit) as a logic gate.

[0002]

2. Description of the Related Art FIG. 4 shows an E / R type DCFL circuit 1 including a conventional GaAs enhancement type n channel junction type FET 1 for driving and a load resistor 2 connected in series to its source and drain. The basic circuit configuration of the element is shown.

The logic gate integrated circuit of the E / R type DCFL circuit has high speed and low power consumption, and at the same time, has a large logic amplitude and a large logic amplitude as compared with this type of circuit using an n channel type Schottky junction type FET. Since it has a noise margin, it is suitable for ultra-high speed LSI.

By the way, in the DCFL circuit of FIG. 4, the output from the output terminal T _OUT is input to the input terminal T _IN of the DCFL circuit of the next stage. In this DCFL circuit, if the power supply voltage does not exceed the forward turn-on voltage of the PN junction of the junction FET, the logic 1 level becomes substantially equal to the positive power supply voltage. When the power supply voltage is 1.2 V or more, the E / R type D by this junction type FET shown in FIG.
As can be seen from the switching speed with respect to the power supply voltage evaluated from the ring oscillator oscillation of the CFL circuit, the switching speed becomes slow.

When the power supply voltage is 1.0 V, the so-called eye pattern of the output is relatively well opened as shown in FIG. 6A with respect to the input voltage waveform shown in FIG. 6A, but the power supply voltage is 1.2 V. Then, for the same input voltage waveform shown in FIG. 7A, the shape of the output eye pattern of FIG. 7B becomes blunt.

In the E / R type DCFL circuit,
When a PN junction type FET is used as the driving FET, the power source voltage becomes large, and an output corresponding to this is given to the enhancement type FET gate in the next stage, so that a voltage of 1.2 V or more is applied to this junction. Then,
This is because holes are injected from the gate electrode of this FET into the GaAs substrate and accumulated.

In addition, there is a case where normal circuit operation is hindered by a so-called side gate effect in which neighboring FETs are affected by the similar hole accumulation effect.

Therefore, in the E / R type DCFL circuit using this kind of PN junction type FET as a driving FET, the power supply voltage is set to 1.0 V at which the above-mentioned injection of holes hardly occurs. It is desirable that the fluctuations of the power supply voltage should not exceed 1.2V.

However, in the case of actually configuring various electronic devices, it is often necessary to use this GaAs compound semiconductor integrated circuit in combination with a semiconductor integrated circuit made of Si, and a power supply generally used in the Si semiconductor integrated circuit. Since the voltage is 2V, 3.3V, or 5V, there is a problem in using this power supply as a dual purpose.

In order to avoid such a problem, a DCFL circuit using an n-channel Schottky junction type FET which does not have the problem of hole injection as described above may be used.
In this case, it is possible to use a power supply of 2V as the power supply voltage.

However, in this case, there is a problem that the noise margin is relatively small as described above.

Therefore, the above-described GaAs n-channel P
It is desirable to use a DCFL circuit having an N-junction FET as a driving FET and to prevent the logic 1 level applied to the FET gate section from exceeding 1.0 V inside the semiconductor integrated circuit.

Therefore, for example, it is conceivable to provide a constant voltage circuit of 1 V in an integrated circuit of a DCFL circuit. In this case, not only the disadvantage of the circuit configuration due to the provision of the low voltage circuit but also the operating state of the DCFL circuit Since the load impedance of the constant voltage circuit changes due to this, it is practically difficult to constantly maintain the power supply voltage stably at a voltage of 1V.

Incidentally, an E / R type DC by a junction type FET
Regarding the advantage of the logic amplitude in the FL circuit, looking at the conventional circuit of FIG. 4, it is now confirmed that the power supply voltage is higher than the forward turn-on voltage of the PN junction of the FET, V _DD = 0V, V _SS.
In the case of = -2V, the logic 1 level of the output is about -0.8V which is higher than the negative power supply voltage V _SS by the PN junction forward turn-on voltage (about 1.2V). And
The logic 0 level is set so that the voltage drop due to the load resistance R is equal to or lower than the FET threshold voltage, and is normally about -1.8V, which is about 0.2V higher than the negative power supply voltage. Therefore, the logical amplitude in this case is about 1V.

On the other hand, when a Schottky junction type FET is used instead of the above-mentioned junction type FET, the logic 1 level is about -1.3V and the logic 0 level is about -1.8V.
V, and the logical amplitude is about 0.5V. That is, in the E / R type DCFL circuit using the junction type FET, the logical amplitude thereof is about twice that in the case of the Schottky junction type FET.

[0016]

DISCLOSURE OF THE INVENTION The present invention provides a driving FE.
In a compound semiconductor integrated circuit by a DCFL circuit using a PN junction type FET as T, for example, a general-purpose power supply voltage of 2 V, for example, in a Si semiconductor integrated circuit can be used, and the output fluctuation due to the fluctuation of the power supply voltage causes The above problems are solved based on the injection and accumulation of holes from the gate electrode of the stepped FET.

[0017]

According to a first aspect of the present invention, as shown in FIG. 1 which is a basic circuit diagram of one element of an example of the device of the present invention, a direct circuit having at least one enhancement type PN junction type FET 1 is provided. In the compound semiconductor integrated circuit device of the coupled FET logic circuit, the load resistance 12 is connected in parallel with the FET 1.

Further, the second aspect of the present invention is to provide at least one enhancement type PN junction type FET, that is, a driving FET 1 and a first load resistor 1 connected in series thereto.
In the compound semiconductor integrated circuit device of the direct coupling type FET logic circuit having 1, the E / R type DCFL circuit,
The second load resistor 12 is connected in parallel with ET1.

Then, in this FET 1, the maximum voltage at which the injection of holes is not significantly generated, that is, the voltage immediately before the start of significant injection when increasing the voltage is V _cr , and the power supply voltage is Vs (the positive power supply voltage V _DD -negative power supply voltage V _SS ),
When the fluctuation rate of the power supply voltage is a and the first and second resistance values are R ₁ and R ₂ , the formula (1) below is selected.

[0020]

[ _Formula 2] V _cr = Vs · (1 + a) · R ₂ / (R ₁ + R ₂ ) ... (1)

[0021]

According to the above-described configuration of the present invention, the logic 1 is provided by providing the second resistor in parallel with the driving PN junction type FET.
Since the level is extracted as a voltage obtained by dividing the power supply voltage, the output voltage can be set to 1.0 V or less, for example.

Further, in the E / R type DCFL circuit configuration, the resistance value R _{1 of} the first and second resistors 11 and 12 is
When R ₂ and R ₂ are selected so that the above equation (1) is satisfied, the output of the power supply voltage Vs is suppressed to a voltage V _cr or less within the range of the fluctuation rate a to avoid hole injection which causes a problem in the FET. You can do it.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the device of the present invention will be described with reference to FIG. In this example, n-channel enhancement type GaA
In the E / R type DCFL circuit in which the first load resistor R ₁ is connected in series with the source and drain of the driving FET 1 of the s PN junction type FET, the second load resistor R is connected in parallel with the driving FET. Connect ₂

In this case, if the output impedance is selected in the same manner as in the conventional case of FIG. 4, that is, if the operating speed when hole injection is not considered is made equal to that of the conventional case, the resistance of the load resistor 2 in FIG. When the value is R, it may be selected according to the relation of the expression (2) of the following mathematical expression 3.

[0025]

## EQU3 ## 1 / R = (1 / R ₁ ) + (1 / R ₂ ) ... (2)

Then, in consideration of hole injection, selection is made so as to simultaneously satisfy the above expression (1).

Now, the voltage at which hole injection in the driving FET begins to occur remarkably, that is, the maximum voltage V _{cr at} which hole injection does not affect the switching speed or cause the side gate effect is 1.0 V. , And the power supply voltage Vs is 2.0 V which is a general-purpose power supply voltage in a Si semiconductor integrated circuit, the fluctuation rate a of the power supply voltage is 0.
If it is 1 (10%), the logical 1 level can be guaranteed to be -1.0 or less if the formula (1a) of the following formula 4 is satisfied from the formula (1).

[0028]

[Formula 4] 1.0 = 2.0 (1 + 0.1) · R ₂ / (R ₁ + R ₂ ) ... (1a)

Load resistances R ₁ and R satisfying these conditions
_{When 2} is set, the logical amplitude for a power supply voltage of -2V is about 0.8V. Therefore, it is possible to use a general-purpose power supply without causing problems of operating speed and side gate while maintaining the superiority of the noise margin when using this PN junction type FET.

Next, the respective constants of the circuit will be specifically shown in FIG.
And the circuit of FIG. 4 are compared. 2 and 3 are inverter transfer characteristics of the circuit of the present invention and the conventional circuit shown in FIGS.

In this case, in the circuit of FIG. 1 of the present invention, the positive power supply voltage was fixed at 0 V with the general power supply voltage of -2.0 V as the standard voltage. FIG. 1A shows the case where the standard power supply voltage is used, and FIGS. 1B and 1C show the case where the standard power supply voltage is increased and decreased by 10%. In this case, paying attention to the logic 1 level when the power supply voltage is increased by 10%, the negative power supply voltage has not risen to 1.0 V or more.

That is, it can be seen that the problem of hole injection can be avoided even when the power supply voltage of -2 V fluctuates by 10%.

In FIG. 3A, in the conventional circuit of FIG. 4, the positive power supply voltage is set to + 1V which does not cause the problems described in FIGS. 5 and 6, and this is set as a standard voltage, and the negative power supply voltage is 0V.
Fixed to. 3B and 3C show the case where the standard power supply voltage is increased and decreased by 10%, respectively.

As can be seen from the results of FIG. 3, the logic 1 level in the circuit of FIG. 4 is almost equal to the positive voltage, and in this case, the above-mentioned problems occur when the power supply voltage increases by 10%. Is afraid.

In the above-mentioned example, the present invention is an E / R type D.
Although it is a CFL circuit, it should be applied to a compound semiconductor integrated circuit device by a so-called E / D type DCFL circuit in which a depletion type FET is connected in series with an enhancement type PN junction type FET as a driving FET 1. You can also

[0036]

According to the above-mentioned configuration of the present invention, the driving P
By providing the second load resistor 12 in parallel with the N-junction type FET 1, the logic 1 level is taken out as a voltage obtained by dividing the power supply voltage, so that the power supply voltage is output even if it is, for example, a general-purpose 2V of Si semiconductor integrated circuit. The voltage can be, for example, 1.0 V or less, which is less than or equal to V _cr .

Further, in the E / R type DCFL circuit configuration, the resistance value R _{1 of} the first and second resistors 11 and 12 is
When R ₂ and R ₂ are selected so as to satisfy the above formula (1), it is possible to avoid the hole injection which causes a problem in the FET within the range of the allowable voltage change rate of the power supply voltage Vs.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of a device of the present invention.

FIG. 2 is an inverter transfer characteristic diagram of an example of the device of the present invention.

FIG. 3 is an inverter transfer characteristic diagram of a conventional device.

FIG. 4 is a circuit diagram of a conventional device.

FIG. 5 is a diagram showing a measurement result of dependency of a switching speed of a DCFL circuit on a power supply voltage.

FIG. 6 is a diagram showing a relationship between a pulse response of an inverter of a conventional device and a power supply voltage.

FIG. 7 is a diagram showing a relationship between a pulse response of an inverter of a conventional device and a power supply voltage.

[Explanation of symbols]

 1 FET for driving 11 First load resistance 12 Second load resistance

Claims (2)

[Claims] 1. A compound semiconductor integrated circuit device of a direct coupling type FET logic circuit having at least one enhancement type PN junction type FET, wherein a load resistance is connected in parallel with said FET. Integrated circuit device. 2. A compound semiconductor integrated circuit device of a direct coupling type FET logic circuit having at least one enhancement type PN junction type FET and a first load resistor connected in series to the enhancement type PN junction type FET. A second load resistance is connected to the FET so that the maximum voltage at which holes are not significantly injected in the FET is V _cr , the power supply voltage is Vs, the fluctuation rate of the power supply voltage is a, and the first and second When the respective resistance values are R ₁ and R ₂ , the compound semiconductor integrated circuit is characterized by selecting the following formula 1 V _cr = Vs · (1 + a) · R ₂ / (R ₁ + R ₂ ). apparatus.