JPH06249053A - Analog/digital conversion method - Google Patents

Abstract

PURPOSE:To execute the analog/digital conversion of the crank synchronization to be generated at an irregular period while maintaining the equi-temporal interval of the analog/digital conversion to be executed at a regular period. CONSTITUTION:A request for the crank angle sensor synchronization A/D conversion is checked (S1007), and when no request for the crank angle sensor synchronization A/D conversion is made, the channel of the conversion order table ADC-N value to be indicated by the pointer ADC-I is set (S1008), and the pointer ADC-I is increased by 1 (S1009). When a request for the crank angle sensor synchronization A/D conversion is present, the request for the crank angle sensor synchronization A/D conversion is reduced by 1 (S1010), and the channel for the crank synchronization conversion is set (S1011). Namely, when the request for the crank angle sensor synchronization A/D conversion is made, the crank synchronization conversion is made without increasing the pointer ADC-I, the subsequent A/D conversion order is delayed by 1, and the period of 8 channels are kept by the loop counter ADC-C to maintain the equi-temporal interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion method for achieving both analog / digital conversion at equal time intervals and crank-synchronized analog / digital conversion.

[0002]

2. Description of the Related Art In recent years, microcomputers have been introduced into vehicles such as automobiles, and it has become possible to control engines, power trains and the like with high precision. Therefore, in the development of the vehicle control system, the software development of the microcomputer has become a major factor, and the efficiency of the processing on the control algorithm has become an important issue.

The microcomputer is mounted on a vehicle as an electronic control unit (ECU) including a constant voltage circuit and various peripheral circuits. For example, the intake air amount is calculated, the fuel injection amount is set, and the ignition timing is set. The job is executed every predetermined time cycle and every predetermined crank angle.

In this case, the ECU receives, for example, analog signals from an intake air amount sensor, a throttle opening sensor, a cooling water temperature sensor, an intake pipe pressure sensor, etc., and a digital signal from a crank angle sensor, an idle switch, etc. Is input, an analog / digital (A / D) converter for converting an analog signal into a digital signal is provided. Normally, in engine control, sampling of data by this A / D converter is performed. , At a fixed time cycle and a non-fixed cycle timing synchronized with a predetermined crank angle.

Therefore, the A / D conversion of the above two timings may interfere with each other to cause a trouble. Therefore, for example, Japanese Patent Laid-Open No. 57-109002 discloses A /
When the crank-synchronized A / D conversion request is made while monitoring the operating state of the D converter and executing the A / D conversion in a fixed time period, without destroying the A / D conversion being executed,
A technique of A / D converting one of them first is disclosed.

[0006]

By the way, in the A / D conversion in a constant time period, more accurate equidistant property is required than the subsequent calculation processing, and for example, the throttle opening, the intake air amount, etc. are changed. From the fast analog signal to the cooling water temperature,
A / D conversion of multiple items up to an analog signal with a relatively slow change such as voltage needs to be executed at equal intervals, while crank-synchronized A / D conversion of a non-constant cycle requires conversion. It should be executed when the request is made.

However, if the crank synchronous conversion is simply interrupted at the time when the conversion request is generated, the A / D conversion of a plurality of items that should be executed at equal intervals is not possible. The periodicity of A / D conversion is impaired,
It becomes difficult to realize A / D conversion at equal intervals.

The present invention has been made in view of the above circumstances, and is capable of performing crank-synchronous analog / digital conversion that occurs in a non-constant cycle while maintaining the equal time interval characteristic of the analog / digital conversion that should be performed in a constant cycle. It is an object to provide an analog / digital conversion method that can be implemented.

[0009]

SUMMARY OF THE INVENTION The present invention is an analog / digital conversion method in which the channels of an analog / digital converter having a plurality of input channels are sequentially driven to perform a preset number of analog / digital conversions at preset time intervals. The conversion order of each channel starts from the channel corresponding to the equal time interval analog / digital conversion in which the conversion is performed at regular time intervals within the set time, and the crank synchronous analog / The channel corresponding to digital conversion is set to be the last, and within the set time, the analog / analog
If the timing for executing the crank-synchronized analog / digital conversion is reached before the conversion on all the channels corresponding to the digital conversion is completed, the crank-synchronized analog / digital conversion is executed on the corresponding channel, and It is characterized in that the conversion order of the channels corresponding to the analog / digital conversion at equal time intervals is delayed by one from the preset conversion order.

[0010]

According to the present invention, the conversion order of the channels in the analog / digital converter having a plurality of input channels is started from the channel corresponding to the analog / digital conversion at equal time intervals in which the conversion is performed at fixed time intervals within the set time. The channel corresponding to the crank-synchronized analog / digital conversion that performs conversion at a predetermined crank position of the engine is preset to be the last, and the analog / digital conversion is performed a set number of times at each set time. If the timing for executing the crank-synchronized analog / digital conversion comes before the conversion on the channel corresponding to the analog / digital conversion at equal time intervals is completed within the set time, the crank-synchronized analog for the corresponding channel is executed. / Digital conversion is executed, and the conversion order of the channels corresponding to subsequent analog / digital conversion at equal time intervals is delayed by one with respect to the preset conversion order, and the number of analog / digital conversion executions within the set time is not changed. In this way, the equality of analog / digital conversion at equal time intervals is maintained.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a flowchart of an A / D conversion subroutine, FIG. 2 is a flowchart of a periodic interrupt process every 0.5 ms, FIG. 3 is a flowchart of classen interrupt process, and FIG. 4 is a job priority process. 5 is a partial flowchart 1 of the job execution subroutine, FIG. 6 is a partial flowchart 2 of the job execution subroutine, FIG. 7 is a partial flowchart 3 of the job execution subroutine, and FIG. 8 is a partial flowchart 4 of the job execution subroutine. Is a flowchart of a crank position calculation subroutine, FIG. 10 is a flowchart of a half rotation time estimation subroutine, and FIG. 11 is CCAS / RCA.
FIG. 12 is a flowchart of an S determination subroutine, FIG. 12 is a flowchart of a Krasen timer overflow interrupt process, FIG. 13 is a flowchart of a read and SSHB store process subroutine, FIG. 14 is an explanatory diagram showing a job execution state, and FIG. FIG. 16 is an explanatory diagram of crank position variables, FIG. 17 is an explanatory diagram showing changes in a job execution flag and an overlap counter, and FIG.
8 is an explanatory view of a classen interval table, FIG. 19 is an explanatory view of a cylinder / crank position state map, FIG. 20 is an explanatory view of a conversion order table, FIG. 21 is an explanatory view of an SSHB store address table, and FIG. 22 is a system shift buffer. Explanatory diagram, FIG. 23 is an explanatory diagram of dream mode variables, FIG. 24 is a time chart showing a crank position and an engine stroke, FIG. 25 is a schematic configuration diagram of an engine system, FIG. 26 is a front view of a crank rotor and a crank angle sensor, FIG. 27 is a front view of the cam rotor and the cam angle sensor, and FIG. 28 is a circuit configuration diagram of the electronic control system.

In the engine control system of this embodiment, the engine system shown in FIG. 25 is controlled by an electronic control unit (ECU) 50 having a microcomputer shown in FIG. 28 as a core, and fuel injection control, ignition timing control, etc. are performed. Be done.

The microcomputer of the ECU 50 has an operating system (O) based on a new concept.
S) is installed, and a job for each control item such as a signal input process from each sensor, an engine speed calculation process, an intake air amount calculation process, a fuel injection amount setting process, an ignition timing setting process, etc. is executed by this OS. It is managed and executed efficiently.

First, the equipment configuration of the engine system controlled by the ECU 50 will be described.

As shown in FIG. 25, an engine 1 (a horizontally opposed four-cylinder engine is shown in the figure) has an intake manifold 3 communicated with an intake port 2 a of a cylinder head 2, and an intake manifold 3 is provided upstream of the intake manifold 3. A throttle passage 5 communicates with the chamber 4.
An air cleaner 7 is attached to the upstream side of the throttle passage 5 via an intake pipe 6, and the air cleaner 7 is in communication with an air intake chamber 8 which is an intake port for intake air.

An exhaust pipe 10 is connected to the exhaust port 2b via an exhaust manifold 9, and a catalytic converter 11 is connected to the exhaust pipe 10 and is connected to a muffler 12. On the other hand, a throttle valve 5a is provided in the throttle passage 5, and an intercooler 13 is provided in the intake pipe 6 immediately upstream of the throttle passage 5,
Further, a resonator chamber 14 is interposed downstream of the air cleaner 7 in the intake pipe 6.

Further, an idle speed control valve (IS) is provided in a bypass passage 15 which connects the resonator chamber 14 and the intake manifold 3 and bypasses the upstream side and the downstream side of the throttle valve 5a.
CV) 16 is interposed. Furthermore, this ISCV1
A check valve 17 which is opened immediately downstream of 6 when the intake pressure is a negative pressure and which is closed when the intake pressure becomes a positive pressure by being supercharged by a turbocharger 18 is interposed.

In the turbocharger 18, a compressor is installed downstream of the resonator chamber 14 of the intake pipe 6, and a turbine is installed in the exhaust pipe 10. Further, a wastegate valve 19 is provided at the turbine housing inlet of the turbocharger 18, and a wastegate valve actuating actuator 20 is connected to the wastegate valve 19.

The waste gate valve actuating actuator 20 is partitioned into two chambers by a diaphragm, one of which forms a pressure chamber communicating with the waste gate valve controlling duty solenoid valve 21, and the other of which forms the waste gate valve 19. A spring chamber is formed that houses a spring that urges in the closing direction.

The wastegate valve controlling duty solenoid valve 21 is interposed in a passage that connects the resonator chamber 14 and the compressor downstream of the turbocharger 18 of the intake pipe 6, and is a control output from the ECU 50. The pressure on the resonator chamber 14 side and the pressure on the compressor downstream side are adjusted according to the duty ratio of the signal, and the pressure is supplied to the pressure chamber of the waste gate valve operating actuator 20.

That is, the wastegate valve controlling duty solenoid valve 21 is controlled by the ECU 50, and the wastegate valve operating actuator 20 is controlled.
Is operated to adjust the exhaust gas relief by the waste gate valve 19, so that the supercharging pressure by the turbocharger 18 is controlled.

An absolute pressure sensor 22 is connected to the intake manifold 3 through a passage 23, and the passage 2
3, an intake pipe pressure / atmospheric pressure switching solenoid valve 24 that selectively communicates the absolute pressure sensor 22 with the intake manifold 3 or the atmosphere is interposed.

Further, an injector 25 is provided immediately upstream of each intake port 2a of each cylinder of the intake manifold 3.
Further, an ignition plug 26a whose tip is exposed to the combustion chamber is attached to each cylinder of the cylinder head 2, and an igniter 27 is connected to an ignition coil 26b connected to the ignition plug 26a. .

The injector 25 includes a fuel tank 2
Fuel is pressure-fed from an in-tank type fuel pump 29 provided inside 8 through a fuel filter 30, and the pressure is regulated by a pressure regulator 31.

An intake air amount sensor 32 of a hot wire type or a hot film type is provided immediately downstream of the air cleaner 7 of the intake pipe 6, and the throttle valve 5a is connected to a throttle opening sensor 33a. Throttle sensor 33 with built-in idle switch 33b
Are lined up.

Further, a knock sensor 34 is attached to the cylinder block 1a of the engine 1, and a cooling water temperature sensor 36 is exposed to a cooling water passage 35 which connects the left and right banks of the cylinder block 1a to the exhaust pipe 10. O2 at the collecting part of the above exhaust manifold 9
The sensor 37 is exposed.

A crank rotor 38 is rotatably mounted on the crank shaft 1b supported by the cylinder block 1a, and a crank angle sensor 39 including an electromagnetic pickup is provided on the outer periphery of the crank rotor 38. Further, a cam angle sensor 41 for discriminating a cylinder, which is composed of an electromagnetic pickup or the like, is provided opposite to a cam rotor 40 connected to the cam shaft 1c of the engine 1. still,
The crank angle sensor 39 and the cam angle sensor 41
Is not limited to a magnetic sensor such as an electromagnetic pickup, but may be an optical sensor.

As shown in FIG. 26, the crank rotor 38 has protrusions 38a, 38b and 38c formed on the outer periphery thereof, and these protrusions 38a, 38b and 38c are attached to the cylinders (# 1, # 2 and #). Before # 3, # 4 compression top dead center (BTD
C) It is formed at the positions of θ1, θ2, θ3, and in the present embodiment, θ1 = 97 ° CA, θ2 = 65 ° CA, θ3.
= 10 ° CA.

The protrusions of the crank rotor 38 are detected by the crank angle sensor 39, and the BTDC 97
Crank pulse of °, 65 °, 10 ° is 1/2 engine
It is output every rotation (every 180 ° CA). Then, the input interval time of each signal is counted by a timer, and the engine speed is calculated.

The protrusion 38b serves as a reference crank angle when setting the ignition timing, and the protrusion 38c serves as a reference crank angle for the injection start timing at the start and a crank angle indicating the fixed ignition timing at the start. .

Further, as shown in FIG. 27, on the outer circumference of the cam rotor 40, there are protrusions 40a, 40b for cylinder discrimination,
40c is formed, and the protrusion 40a is formed at the position after compression top dead center (ATDC) θ4 of the # 3 and # 4 cylinders.
b is composed of three protrusions, and the first protrusion is A for cylinder # 1.
It is formed at the position of TDCθ5. Furthermore, the protrusion 40
c is formed by two protrusions, and the first protrusion is A for cylinder # 2.
It is formed at the position of TDC θ6. In this embodiment, θ4 = 20 ° CA, θ5 = 5 ° CA, θ6 = 20 °
It is CA.

When each protrusion of the cam rotor 40 is detected by the cam angle sensor 41 and the combustion stroke sequence of each cylinder is # 1 → # 3 → # 2 → # 4, the combustion stroke sequence and Cylinder discrimination is made based on the pattern of the cam pulse from the cam angle sensor 41 and the value counted by the counter.

On the other hand, the ECU 50 shown in FIG. 28 is mainly composed of two computers, that is, a main computer 51 for controlling fuel injection and ignition timing, and a dedicated sub computer 52 for performing knock detection processing.
A constant voltage circuit 53 for supplying a predetermined stabilizing power source and various peripheral circuits are incorporated in each unit.

The constant voltage circuit 53 includes an ECU relay 54.
The relay coil of the ECU relay 54 is connected to the battery 55 via an ignition switch 56.
Further, the constant voltage circuit 53 is directly connected to the battery 55, and further, the fuel pump 29 is connected via a relay contact of a fuel pump relay 57.

That is, the constant voltage circuit 53 supplies control power when the ignition switch 56 is turned on and the relay contact of the ECU relay 54 is closed, and the ignition switch 56 is turned off.
Supply the power for backup when

The main computer 51 has a CPU 5
8 (hereinafter, referred to as main CPU 58), ROM 59,
RAM 60, the ignition switch 56 is OFF
Backup RAM 6 which holds data by being supplied with backup power from the constant voltage circuit 53 even when
1, a counter / timer group 62, a serial communication interface SCI 63, and an I / O interface 64 are connected to each other via a bus line 65.

The counter / timer group 62 includes various counters such as a free-run counter, a cam angle sensor (hereinafter, abbreviated as "CamSens") signal counting counter, a fuel injection timer, an ignition timer, and the like. A periodic interrupt timer for generating a periodic interrupt every 0.5 ms described later, a crank angle timer for inputting a crank angle sensor (hereinafter, abbreviated as "clasen") signal interval, and a watchdog timer for system abnormality monitoring For the sake of convenience, the various types of timers such as the above are collectively referred to, and various other software counters and timers are used in the main computer 51.

In the sub computer 52, the CPU 71 (hereinafter referred to as the sub CPU 71), the ROM 72, the RAM 73, the counter / timer group 74, the SCI 75, and the I / O interface 76 are connected to the bus line as in the main computer 51. The microcomputer is a microcomputer connected via 77, and the main computer 51 and the sub computer 52 are the SCI 63, 7
They are connected to each other via a serial communication line via 5.

The I / O interface 64 of the main computer 51 has an intake port, an intake air amount sensor 32, a throttle opening sensor 33a, and a water temperature sensor 3 at its input ports.
6, O2 sensor 37, absolute pressure sensor 22, vehicle speed sensor 4
2 and battery 55 are A / D of 8 channel input
The idle switch 33b, the crank angle sensor 39, and the cam angle sensor 41 are connected together via the converter 66.
Is connected, and further, a starter switch 43 is connected to detect the starting state.

In the present embodiment, the A / D converter 66 uses inputs for 7 channels, and the remaining 1
The channel is reserved.

An igniter 27 is connected to the output port of the I / O interface 64, and further,
Through the drive circuit 67, the ISCV16, the injector 2
5, the relay coil of the fuel pump relay 57, the waste solenoid valve controlling duty solenoid valve 21, and the intake pipe pressure / atmospheric pressure switching solenoid valve 24 are connected.

On the other hand, the I / O of the sub computer 52
The interface 76 has an input port to which the crank angle sensor 39 and the cam angle sensor 41 are connected, and
The knock sensor 34 is connected via the D / D converter 78, the frequency filter 79, and the amplifier 80. The knock detection signal from the knock sensor 34 is amplified to a predetermined level by the amplifier 80, and then the frequency filter 79. The necessary frequency components are extracted by the A / D converter 78.
At, it is converted into a digital signal and input.

The main computer 51 processes the detection signals from the sensors and calculates the fuel injection pulse width, the ignition timing and the like. That is, the intake air amount sensor 32
The intake air amount is calculated from the output signal, and the fuel injection amount corresponding to the intake air amount is calculated based on various data stored in the RAM 60 and the backup RAM 61, and the ignition timing and the like are calculated.

Then, a drive pulse width signal corresponding to the fuel injection amount is output to the injector 25 of the corresponding cylinder at a predetermined timing via the drive circuit 67 to inject fuel, and at the predetermined timing, the igniter 27 is also used. To the ignition plug 26a of the corresponding cylinder.

As a result, the air-fuel mixture supplied to the corresponding cylinder explodes and burns, the oxygen concentration in the exhaust gas is detected by the O2 sensor 37 facing the collecting portion of the exhaust manifold 9, and the waveform of this detection signal is shaped. After that, the main CPU 58 compares the reference voltage (slice level) with
It is determined whether the engine air-fuel ratio state is on the rich side or lean side with respect to the target air-fuel ratio, and feedback control is performed so that the air-fuel ratio becomes the target air-fuel ratio.

On the other hand, in the sub computer 52, a sample section of the signal from the knock sensor 34 is set based on the engine speed and the engine load, and the signal from the knock sensor 34 is A / D at high speed in this sample section. Then, the vibration waveform is faithfully converted into digital data to determine whether knock has occurred.

The output port of the I / O interface 76 of the sub computer 52 is connected to the input port of the I / O interface 64 of the main computer 51, and the knock determination result of the sub computer 52 is I / O. It is output to the interface 76. Then, in the main computer 51, when the sub computer 52 outputs a determination result indicating that knock has occurred, the knock data is read from the serial communication line via the SCI 63, and the ignition timing of the corresponding cylinder is immediately read based on the knock data. Delay and avoid knocks.

In such engine control, in the main computer 51, various programs for each item such as signal input processing from each sensor, engine speed calculation, intake air amount calculation, fuel injection amount calculation, ignition timing calculation, etc. Is efficiently executed under the control of one OS. This OS has various management functions for vehicle control and an internal strategy closely related to this management function, and systematically combines various jobs.

As the management function of the above OS, (1-1) priority processing of jobs (1-2) support for divided files of each job by section definition (1-3) stack usage monitoring function (1-4) Abnormal interrupt operation monitor function (1-5) Functions such as standard map and standard work memory settings that do not create unique restrictions for each job improve the control strategy development environment and maximize the limited CPU power. The same time interval processing which is the basis of digital control theory can be achieved as much as possible.

The equal time interval processing is based on a periodic interrupt every 0.5 ms, and is 2, 4, 10, 50, 250.
Five types of equally interrupted jobs for every ms are prepared, and a high-priority class job (hereinafter simply referred to as classen job) that is immediately interrupted by crank angle signal input as processing synchronized with engine rotation. , A relatively low-urgency low-priority job that is interrupted by a crank angle signal input when there is no other job with a higher priority.

Each of these jobs includes a Krasen job>
In the order of 2 ms job> 4 ms job> 10 ms job> low priority class job> 50 ms job> 250 ms job, priority levels of 7 to 1 are assigned from the high side to the low side, as shown in FIG. The low-speed job is divided into the high-speed job and processed, and the multiplex waiting process of each job is performed.

Further, each program operating under the OS is arranged in order for each function-specific management area, that is, for each section area, and each section area is named by a section declaration for each function. The main section areas used on each strategy file side are: ○ Variable declaration area ○ Self-file name, automatic recording area during file creation ○ Setting data area ○ Class job area ○ 2ms job area ○ 4ms job area ○ 10ms job area ○ Low priority class job area ○ 50ms job area ○ 250ms job area ○ Reset initialization job area ○ Engine stall initialization job area ○ Background job area ○ Program body area, which is a file division for each function and program development It also enables structured description of programs.

Further, the above-mentioned OS has (2-1) A / D conversion processing (2-2) Calculation of various information related to crank position (2-3) Debug as an internal strategy closely related to the above management function. Simulation function (engine rotation and A / D conversion) (2-4) Ignition timer set (2-5) Fuel injection timer set and other functions are provided. Furthermore, various service routines related to these functions are provided. It is prepared in each job.

Conventionally, such a function has been achieved at each job level, but in this system,
If the fuel injection amount, ignition timing, etc. are set for each job on the user side based on the A / D conversion result processed by the OS side, crank position information, engine speed, etc. The instruction value is set by the OS in the fuel injection timer and the ignition timer.

Next, the function of job processing in the main computer 51 will be described with reference to the flowcharts of FIGS. Since the sub computer 52 is a computer dedicated to knock detection processing, its operation description is omitted.

First, the ignition switch 56 is turned on.
When the power is supplied to the system, a reset interrupt associated with the reset is activated, various initializations are performed, and a periodic interrupt timer for activating the periodic interrupt is activated every 0.5 ms.
Each signal input from 9 (BTDC 97 °, 65 °, 10 °
The classen interrupt that is activated every six engine revolutions per CA) is permitted, and then the background job is executed.

Then, on this background job, a periodic interrupt every 0.5 ms and 6 times per engine revolution.
A job of the 7th level is preferentially processed by the number of classen interrupts. In these two interrupts, after executing their own processing, they jump to a common address and execute job priority processing.

The reset interrupt may be caused by a factor that does not normally occur, such as when division by 0 is executed in an internal operation or when an infinite loop occurs.
Is activated.

First, the periodic interrupt every 0.5 ms shown in FIG. 2 will be described. In this periodic interrupt, step S1
At 00, set the OS work area, and at step S101,
When the watchdog timer is initialized, the process proceeds to step S102, and the P-RUN flag is set once every 20 times, that is, 10 times.
Invert every ms. The P-RUN flag is a flag for preventing the system from being automatically reset by a protection circuit (not shown), and is protected as long as the system operates normally and is inverted at regular time intervals (every 10 ms). The operation of the circuit is blocked.

Next, in step S103, the switch output is transferred. This switch output is the ON / OFF value of the bit written in the memory in each job. It is not directly output from the output port of the I / O interface 64 from each job, but the OS outputs the memory every 0.5 ms. Transfer the value to the output port.

Next, in step S104, the A
A / D conversion subroutine is executed to make various settings related to A / D conversion, and in step S105, a job flag creation subroutine is executed to set 2, 4, 10, 50, 250 ms.
Job flag JB_FL indicating each job interrupt request for each
After creating G, in step S106, A / D conversion is started.

In the A / D conversion, basically, the 8-channel input of the A / D converter 66 is processed every 0.5 ms in a predetermined conversion order, and all the inputs are converted in a cycle of 4 ms. However, one specific channel is synchronized at every crank angle of 90 ° (with time accuracy of 0.5 ms) for A / D conversion of suction pipe pressure that causes rotational pulsation, and interrupts the conversion order. The processing is performed in a dull shape, and the order of subsequent inputs is delayed by one.

Further, as shown in FIG. 15, the job flag JB_FLG is one in which each bit of the 1-byte variable is assigned as a flag corresponding to each job, and a plurality of job requests can be made simultaneously. There is. Bits 1 to 7 of this 1-byte variable correspond to priority levels 1 to 7, and are respectively 250 ms job, 50 ms job,
It is assigned to flags of low priority class job, 10 ms job, 4 ms job, 2 ms job, and class job. Then, when a predetermined bit is set, a job interruption request of a corresponding priority level is made. still,
Bit 0 is assigned to the flag of the background job and is not normally referred to.

Then, in step S105, the job flag JB_FLG is created by the job flag creation subroutine, and after A / D conversion is started in step S106, the process proceeds to step S107, and any job of the job flag JB_FLG is processed. Check whether the bit to be set is set.

As a result, when none of the bits of the job flag JB_FLG is set, there is no request from any job and the interrupt is ended.
If any bit of LG is set, the process proceeds to step S108, and there is no flag below the current level (a state in which a job of a predetermined priority level is being executed at the time when this periodic interrupt is executed). To find out.

If there is no flag below the current level in step S108, the process jumps to the job priority process shown in label WAR_JB in FIG. 4, and if there is a flag below the current level, in step S109 the level below the current level is reached. The overlap counter OLC of is increased by one.

The overlap counter OLC is a counter for storing a job request, 1 byte is allocated to each priority level, and the job flag JB_F is set.
It is incremented when a job is requested by LG and decremented when the job is completed. That is, by storing the job request by the counter, it is possible to deal with the multiple job request.

Next, from step S109 to step S1
Go to step 10 to check whether there is a flag higher than the current level. If there is no flag higher than the current level, exit the routine and end the interrupt. If there is a flag higher than the current level, the job priority process of label WAR_JB is executed. Jump to.

On the other hand, in contrast to the periodic interrupt every 0.5 ms, the interrupt by the classen in FIG.
Then, when the OS work area is set, step S201
Then, the crank position / half-rotation time calculation subroutine described below is executed, and the crank position variable for determining the current crank position and the half-engine elapsed time which is the sum of the latest three Classen intervals Calculate the rotation time.

The crank position variables are system variables prepared in the OS, and as shown in FIG.
Crank position for # 4 cylinder is 97 °, 65 °, 1
It is divided into 12 states by 0 ° CA and represents the current crank position.

That is, for each cylinder, the crank position information variable S_CC indicating the Krasen input order by the numerical value of 0, 1, 2
AS, # 1 cylinder is 0, # 3 cylinder is 1, # 2 cylinder is 2, #
Cylinder information variable S_ indicating the combustion order of cylinders with 4 cylinders as 3
RCAS and 3 of the total position variable S_ACAS that comprehensively represent the Krasen order and the cylinder order with numerical values of 0 to 11
The current crank position is represented by a variable, and when the crank position is normally determined with certainty, it is set to 0,
The estimated state where the determination result does not match and the anxiety remains 1,
An error level S_ECAS that sets the unknown state to 2 indicates the determination situation of the crank position. In FIG. 16, S_ indicating a system variable is omitted.

Next, from step S201 to step S2
When the process proceeds to 02, it is checked by reading the code stored in the accumulator A whether or not the crank position determination in the crank position / half-rotation time calculation subroutine has ended normally or cannot be determined (error code 1, normal Exit code 0).

Then, in step S202, when the value of the accumulator A is 1 and the crank position cannot be determined, the interrupt is ended, the value of the accumulator A is 0, and the crank position is determined normally. If so, the process proceeds to step S203, and the engine stall flag is cleared.

The engine stall flag is a flag indicating that the engine is in an engine stall state. When the classen interval is 0.5 sec or more (about 30 rpm or less), an engine stall processing routine prepared for a 50 ms job is provided. Is set by, and is cleared by this classen interrupt to release the stalled state.

Next, in step S204, the ignition timer setting subroutine is executed, and the ignition timer is set according to the ignition schedule created based on the instruction value of the ignition timing set on the user job side. This ignition schedule is for dwell start time, dwell on waiting time,
This is a structure variable whose members are the dwell off waiting time and the like. A creation routine is prepared during the 10 ms job, and the ignition sequence is determined according to this ignition schedule.

Next, at S205, a fuel injection timer set subroutine is executed, and the fuel injection amount instruction value (injection width for each cylinder) set on the user job side is set to
The fuel injection start timing is set in the fuel injection timer, and the process proceeds to step S206.

In step S206, it is determined whether or not the current job level at which this class is executed is the own job level. If the current status is the level of the class job itself, then in steps S207 and S208 the class job ,
Overlap counter OL for low priority class job
When C is incremented by 1 and the interruption is ended, and the current job level is not the level of the class job,
In step S209, it is checked whether the current job level is equal to or higher than the low priority class job level.

When the current job level is equal to or higher than the low-priority class job, the process proceeds from step S209 to step S210, and if the overlap counter OLC of the low-priority class job is incremented by 1, step S2
At 11, the job flag of the class job is set, and the process jumps to the job priority process of the label WAR_JB.

On the other hand, in step S209, when the current job level is not lower than the low priority class job, the process proceeds from step S209 to step S212 to set the job flag of the class job. The job flag is set, and the process jumps to the job priority process with the label WAR_JB.

In this job priority process, step S300
Then, if the job level JB_LEV, which is a 1-byte variable indicating the priority level of the job, is increased by one, the process proceeds to step S301, and it is checked whether or not the job flag corresponding to this priority level is set. If the job flag is not set, the process returns to step S300 to further increase the job level JB_LEV by one, and if the job flag is set, the process proceeds to step S302 to set the overlap counter OLC of the job for which the job flag is set. Initial value 0
Is set to 1 and the process proceeds to step S303.

In step S303, it is checked whether or not there is a higher job flag, and when there is a higher job,
Returning to step S300, the above processing is repeated. If there is no higher job, the process proceeds to step S304 to set the job executing flag JB_RUN, and then step S3
At 05, the highest-level job is executed by the job execution subroutine described later.

The job executing flag JB_RUN is
It is a flag that is set at the start of job execution and cleared at the end. By this flag, a job interrupted by a job with a higher priority can be identified during processing.

For example, as shown in FIG. 17, JB_LE
When an interrupt request for a 2ms job with JB_LEV = 6 is made during execution of a 10ms job with V = 4, the processing of the 10ms job is interrupted, and the higher priority 2ms job is set to JB_RUN = 1 and OLC = 1. Is executed. Then, during the processing of this 2 ms job, JB_
When an interrupt request for a 4 ms job with LEV = 5 occurs,
This 4 ms job is set to JB_RUN = 0 and OLC = 1 to accept an interrupt, but is not executed and is in a standby state.

After that, when the execution of the job by the job execution subroutine is completed, the process proceeds from step S305 to step S306, the overlap counter OLC is decremented by 1, and it is checked in step S307 whether the overlap counter OLC has become zero. . As a result, when the overlap counter OLC is not zero and there are multiple job interrupt requests at the same priority level, step S3
Returning to 05, the job is repeatedly executed, and when the overlap counter OLC becomes zero, the process proceeds from step S307 to step S308 to clear the job executing flag JB_RUN.

Next, in step S309, when the job level JB_LEV is lowered by 1 and the job level is moved to the next job level,
In step S310, it is checked whether this job level JB_LEV has become zero. Then, the job level JB_
When LEV is zero, this interrupt is ended, and when job level JB_LEV is not zero, step S3
Proceed to 11 and check whether the overlap counter OLC is zero.

When the overlap counter OLC is zero in step S311, there is no job request at this level. Therefore, the process returns from step S311 to step S309, the job level JB_LEV is further lowered by one, and the same processing is repeated. If the overlap counter OLC is not zero, the flow advances to step S312 to check if the job executing flag JB_RUN is set at this job level.

When the job executing flag JB_RUN is set in step S312, the job was being executed before the interruption, so the interruption is terminated and the process returns to the job before the interruption, and the job executing flag JB_RUN is set. If not, the process returns to step S304, the job of this level is executed, and the same processing is repeated.

That is, in FIG. 17, JB_LEV
= 6 ms 2ms job is completed, OLC = 0, JB_RU
When N = 0, the job level is lowered by 1 and JB_
4ms job with LEV = 5, JB_RUN = 0, OL
JB_RUN = 1 is set from the standby state of C = 1,
To be executed. Furthermore, when the 4ms job is completed, JB
Moving to _LEV = 4, the processing of the 10 ms job suspended by the 2 ms job and the 4 ms job is resumed from the state of JB_RUN = 1 (job is being executed).

In this way, the periodic interrupt every 0.5 ms,
A job flag J for notifying the priority level and execution timing of each job with the classen interrupt as the basic timing.
Since B_FLG is created, equal time interval processing and engine rotation synchronization processing can be realized as accurately as possible, and each job can be processed efficiently. Further, the job flag JB_F updated for each interrupt which is the basic timing
Since the overlap counter OLC stores the job multiplex request regardless of LG, even if the processing time of a certain job is prolonged and it is time to execute the same job again, the processing is abandoned midway. No, the process can be continued to the end as much as possible.

At this time, it is necessary to always know the crank position accurately, and the crank position calculation subroutine shown in FIG. 9 is executed for each classen interrupt to execute the crank position variables S_CCAS, S_RCAS, S_ACA.
S and S_ECAS are calculated. In the following description, S_ indicating a system variable will be omitted from the crank position variable.

In this crank position calculation subroutine,
First, in step S600, the lower 2 bytes of the class timer are stored in the lower 2 bytes of the soft timer. This classen timer is a hardware timer provided in the ECU 50, and in the present embodiment, a maximum of two 16-bit timers.
Counting is possible up to 55 ms, but a continuous area of 3 bytes is secured in the memory, 2 bytes of the Classen timer are transferred to the lower 2 bytes, and the 3rd byte is counted up by the interrupt generated by the overflow of the Classen timer. It is used as a soft timer.

That is, when an overflow occurs in the classen timer, the overflow interrupt shown in FIG. 12 occurs, and the third byte of the soft timer is set to 1 in step S900.
When the number is increased, it is determined in step S901 whether the third byte of the soft timer exceeds 255. And 255
If it does not exceed step S901, step S901 to step S9
When it jumps to 03 and exceeds 255, it proceeds from step S901 to step S902, stops the third byte of the soft timer at 255, and proceeds to step S903.

In step S903, it is determined whether the third byte of the soft timer is not 2, that is, the class interval is 0.
It is checked whether the engine is in the stalled state for more than 5 seconds (255 ms × 2). If the 3rd byte of the soft timer is not 2, the interrupt is terminated and the 3
When the byte is 2, the process proceeds from step S903 to step S904 to check whether the engine stall flag is set.

In the above step S904, the interrupt is ended when the engine stall flag is set, and when the engine stall flag is not set, the above-mentioned 50 is executed in step S905.
The stalling processing request flag for activating the stalling processing routine prepared for the ms job is set and the interruption is ended.

As a result, the classen interval can be up to 64 se.
It is possible to count up to c (255 ms × 256), and it is possible to easily cope with extremely long Krasen intervals such as cranking without using a special hardware timer of 16 bits or more.

On the other hand, in the crank position calculation subroutine, when the process proceeds from step S600 to step S601, it is checked whether the classen interval is equal to or shorter than the set time. This set time is
The time as a classen interval corresponding to the maximum engine speed is, for example, 0.3 ms, and when the classen interval is less than or equal to the set time in the above step S601, it is determined as a counting error of the classen timer due to mixing of noise or the like in step S602.
Error code 1 is stored in accumulator A, and in step S601, when the classen interval is longer than the set time, it is determined that the classen timer count is normal, and the step
Proceed to S603.

At step S603, CCAS.R to be described later is performed.
The CAS determination subroutine is executed to determine the crank position, and in step S604, it is determined whether or not the error level ECAS is 2, that is, whether or not the cylinder is not determined, such as during cranking. Examine, ECAS
= 2, the process branches to step S605, the error code 1 is stored in the accumulator A, and the routine exits.

On the other hand, in the above step S604, ECAS ≠ 2
In case of, the process proceeds to step S606, and the third byte of the soft timer is set to 0. Then, the process proceeds to step S607, whether or not the crank position information variable CCAS is 1, that is,
Current crank position is BTDC 65 ° CA-10 ° CA
During the period (see FIG. 16), CCAS = 1
In case of, it jumps from step S607 to step S609, and in case of CCAS ≠ 1, it advances from step S607 to step S608 and increments the A / D conversion request by 1,
Proceed to step S609.

This A / D conversion request is a flag-like variable for instructing crank synchronization A / D conversion for each 90 ° crank angle, and takes a value of 0 or 1, and when the value is 1, crank synchronization is performed. Instruct A / D conversion. That is, as described above, of the 8-channel A / D conversion, the 1-channel A / D conversion is performed at every crank angle of 90 °.
When CCAS becomes 0 (BTDC 97 °), CC
When AS becomes 2 (BTDC 10 °), the crank-synchronized A / D conversion request is set, and the A / D conversion for every 90 ° crank angle is interrupted for the A / D conversion order every 0.5 ms. It does.

Then, in step S609, the total position variable ACAS is calculated by multiplying the cylinder information variable RCAS by 3 and adding the crank position information variable CCAS (ACAS = RCAS × 3 + CCAS), and step S610
Then, the soft timer is limited by 2 bytes, and if the classen timer overflows, the lower 2 bytes are F
The processing proceeds to step S611 as FFF (255 ms).

In step S611, the total position variable ACAS
Array TCAS [A with subscripts = 0, 1, 2, ..., 11
CAS] (element of array) to store the classen interval data, and in step S612, crank position information variable CCAS =
Array MTCSX [CCAS] with subscripts 0, 1, 2
Store Classen interval data in (array element).

As shown in FIG. 18A, the array TCAS is a 12-word classen interval table in which classen interval data for two engine revolutions corresponding to ACAS = 0, 1, 2, ... Yes, array MTCSX
As shown in FIG. 18B, CCAS = 0,1,2
3 pieces of Classen interval data corresponding to
It is a word classen interval table.

That is, by referring to the array TCAS, it is possible to know the change in the Krasen interval (change in rotational speed) at each crank position of each cylinder, and to determine the presence or absence of misfire in each cylinder, the combustion state, and the like. The operation status of all cylinders can be grasped. Also, the array MTC
By referring to SX, the latest Classen interval can always be obtained, and the current operating condition can be quickly grasped.

Next, in step S613, the value of the error level ECAS is checked again. Here, since it has already been confirmed in step S604 that ECAS ≠ 2, it is checked whether or not the error level ECAS is 1, that is, whether or not the determination of the crank position is an estimation state in which anxiety remains. .

When ECAS ≠ 1 (that is, ECAS = 0) in step S613 and the crank position is determined with certainty, the process proceeds from step S613 to step S614, and the sum of the latest three classen interval data ( (Sum of array MTCSX), 3 bytes half rotation time MT
Calculate as CS18 (MTCS18 = ΣMTCS
X). That is, the half rotation time MTCS18 is calculated each time the crank position information variable CCAS is updated for each classen interrupt and the data in the array MTCSX is updated,
The latest data can always be obtained by taking the moving sum of the Krasen intervals for each position of BTDC 97 °, 65 °, 10 °.

On the other hand, in the above step S613, ECAS = 1
When the crank position is in an estimated state in which the determination of the crank position remains uncertain, the half rotation time MTCS1 is calculated from the array MTCSX.
8 is not calculated, but the half rotation time estimation subroutine is executed in step S615 to estimate the half rotation time MTCS18.

The estimation of the half rotation time MTCS 18 will be described. First, in step S700 of FIG. 10, whether or not the crank position information variable CCAS is 1, that is, whether or not the current crank position is between BTDC 65 ° and 10 °. If CCAS = 1, then in step S701, BTD
From the angle 32 ° between C97 ° and 65 °, the previous Krasen interval × 180/32 is estimated as the half rotation time MTCS18 and the process returns.

On the other hand, in the above step S700, CCAS ≠ 1
If it is, the routine proceeds from step S700 to step S702, and whether or not the crank position information variable CCAS is 2, that is, the current crank position is from BTDC10 ° to ATDC.
Whether or not it is between 83 ° (BTDC97 ° of the next cylinder) is checked, and when CCAS ≠ 2 (when CCAS = 0),
Progressing to step S703, BTDC10 ° to ATDC83
The angle between 93 ° and the previous Krasen distance x 180/9
3 is estimated as the half rotation time MTCS 18 and the process returns.

In step S702, CCAS = 2
In the case of, the process branches from the above step S702 to step S704, and from the angle 55 ° between BTDC 65 ° to 10 °, the previous classen interval × 180/55 is set as the half rotation time MTCS18.
And return.

In the crank position calculation subroutine, after the half rotation time MTCS18 is calculated in step S614 or after the half rotation time MTCS18 is estimated by the subroutine of step S615 described above, the process proceeds to step S616 and 3 bytes. When the half rotation time MTCS18 of the above is limited to 2 bytes and stored in a predetermined variable MTCSK, this variable MTCSK is doubled and stored in the variable MTCSK4 in step S617, and the normal end code 0 is stored in the accumulator A in step S618. Store and exit the routine.

Next, the CCAS / RCA shown in FIG.
The S determination subroutine will be described. In this subroutine, first, in step S800, the CamSen counter is limited to 0-4. The number of cam pulses from the cam angle sensor 41 counted by the cam sensor counter is 0 to 3 in the normal state as shown in FIG. 24, but is 4 or more abnormal count values due to the influence of noise or the like. Therefore, the camsen counter is limited to 0 to 4 and an abnormal state is represented by 4.

Next, in step S801, a combination of 5 × 4 × 2 (the number of cam sens counters 0 to 4 is 5) is obtained from (the count value of) the cam sen counter, the cylinder information variable RCAS, and the crank position information variable CCAS. Type, cylinder information variable RCAS
Of the cylinder / crank position state CCHMA in which the state data for four types of 0 to 3 and two types of the crank position information variable CCAS of 0, 1 and 2 are stored.
Read P.

This cylinder / crank position state map CCH
In the MAP, as shown in FIGS. 19 (a) and 19 (b), when the crank position information variable CCAS is 0 or 1,
When the crank position information variable CCAS, which is the change point of the cylinder information variable RCAS, is 2, it is determined whether normal or abnormal for all possible states of each combination of the Camsen counter and the cylinder information variable RCAS. The state data indicating whether to be good or to be estimated is stored, so that the current state can be evaluated and the next state to be taken can be known.

That is, the program can be greatly simplified, the memory capacity can be saved, the processing speed can be improved, and the specification can be flexibly changed as compared with the normal condition judgment processing. Can be dealt with.

The above-mentioned status data is 2-bit data, and the value of bit 0 indicates whether it is definite or estimated, and the value of bit 1 indicates whether it is normal or abnormal. The value of bit 0 is
When the value is 0, the determination is made, and when the value is 1, the estimation is shown, and as can be seen from FIG. The value of bit 1 is normal when 0, abnormal when 1, and normal only when the camsen counter is 3 or less and matches the combination shown in FIGS. 16 and 24, and otherwise. It is in an abnormal state.

For example, as shown in FIGS. 16 and 24, CCAS = 0 or 1, that is, a combination in which the CAMDC counter is 0 and the cylinder information variable RCAS is 0 for BTDC 97 ° to 10 ° of a certain cylinder. In addition, since it is a state in which the crank position can be estimated normally, the state data of 01 (normal estimation) in binary is stored in the corresponding region of the cylinder / crank position state map CCHMAP.
Furthermore, when the cam sen counter is 1 and the cylinder information variable RCAS is
Since the combination in which is 0 is obviously abnormal and is a state that can only be estimated, state data of 11 (abnormality estimation) in binary is stored in the corresponding region of the cylinder / crank position state map CCHMAP.

Further, CCAS = 2, that is, a combination in which the CAMDC counter is 3 and the cylinder information variable RCAS is 0 with respect to BTDC10 ° to ATDC83 ° of a certain cylinder, the crank position sandwiching the TDC of the # 1 cylinder is used. Cylinder / crank position status map CCHM because it can be confirmed normally
Binary number 00 (normally confirmed) status data is stored in the corresponding area of the AP, and further, the Kamsen counter is set to 2
Since the combination in which the cylinder information variable RCAS is 0 is obviously abnormal, it is in a state in which there is no choice but to confirm if there are two or more Camsen inputs. Therefore, in the corresponding region of the cylinder / crank position state map CCHMAP, a binary number 10 (abnormality confirmed)
The status data of is stored.

When the status data is read from the cylinder / crank position status map CCHMAP in step S801, the process proceeds to step S802, and it is determined whether or not the error level ECAS is 2, that is, the current status is not cylinder-determined. Check whether it is in an unknown state, ECAS = 2
If it is, it is checked whether or not bit 0 of the state data read from the cylinder / crank position state map CCHMAP in step S803 is 0, that is, whether it is the confirmed state. If it is the confirmed state, the process proceeds to step S804, and the state is not the confirmed state. When it is in the estimated state, it exits the routine and waits until it becomes the confirmed state.

On the other hand, when ECAS ≠ 2 in step S802, the process proceeds to step S804 to check whether the state is the estimated state or not, and depending on the confirmed state or the estimated state, the process proceeds to step S805 and subsequent steps or step S812 and subsequent steps. If the process proceeds to step S804 in the confirmed state at step S803, the process proceeds to step S805 and subsequent steps.

First, the processing after step S805 will be described. When the processing proceeds to step S805,
Since it is in the confirmed state that the cylinder discrimination is made regardless of abnormality,
As can be seen from the time chart of FIG. 24, the crank position information variable CCAS is set to 0 because the present classen interrupt is a BTDC 97 ° interrupt after three or two cam pulses are input.

Next, in step S806, it is checked whether the Camcen counter is 3 or not, and the Camcen counter is 3c.
If it is not, that is, when the CamSen counter is 2, it is after ignition of the # 2 cylinder, so the cylinder information variable RCAS is set to 3 in Step S807 and the process proceeds to Step S809. Since it is after ignition, the cylinder information variable RCAS is set to 1 in step S808, and the flow proceeds to step S809.

In step S809, the status data is read again from the cylinder / crank position status map CCHMAP using the updated crank position information variable CCAS, cylinder information variable RCAS, and Camsen counter as parameters, and bit 1 of this status data is 1 , That is, whether or not it is in an abnormal state.

As a result, when it is determined in step S809 that the bit 1 of the state data is 1 and the state is abnormal, the crank position information variable CCAS and the cylinder information variable RC
Assuming that the AS update result is an uneasy estimate
In step S810, the error level ECAS is set to 1, and the routine exits. When bit 1 of the status data is 0, indicating a normal state, the error level ECAS is set to 0 in step S811, and the routine exits.

On the other hand, in the processing after step S812, the current crank position information variable CCAS (crank position information variable CCAS calculated by the previous Krasen interrupt) is 2 in step S812, that is, the change point of the cylinder information variable RCAS. If CCAS = 2, the process proceeds from step S812 to step S813, and the cylinder information variable R
CAS is incremented by 1, the crank position information variable CCAS = 0 is set in step S814, and the flow proceeds to step S817.

On the other hand, in the step S812, CCAS ≠ 2
If it is, the process proceeds from step S812 to step S815 to check whether the Camcen counter is not 0. If the Camcen counter is not 0, the above step S813 is executed.
When the cam sen counter is 0,
In S816, the crank position information variable CCAS is incremented by 1, and the process proceeds to step S817.

In step S817, the status data is read again from the cylinder / crank position status map CCHMAP using the updated crank position information variable CCAS, cylinder information variable RCAS, and Camsen counter as parameters to determine whether or not there is an abnormal status. Check, bit 1 of status data is 0
In the normal state, the routine is exited as it is (the current error level ECAS = 0 remains). If the bit 1 of the status data is 1 and the status is abnormal in step S817, the process proceeds to step S818, and the error level ECAS is set as the estimation result of the crank position information variable CCAS and the cylinder information variable RCAS is an uneasy estimation. Set to 1 and exit the routine.

The A / D conversion request in step S608 of the above crank position calculation subroutine is A in FIG.
Referenced in the A / D conversion subroutine, equal time interval A / D
The conversion and the crank synchronization A / D conversion are executed at a predetermined timing. Hereinafter, a description will be given according to the flowchart of FIG.

In this A / D conversion subroutine, it is checked in step S1000 if it is the first A / D conversion process. If it is the first process, step S1001
Then, the conversion order table ADC is sent to the A / D converter 66.
The A / D conversion in the input channel indicated by the head data ADC_N [0] of _N is set, and step S1002
Then, the pointer ADC_I of the conversion order table ADC_N
(Initial value is 0) Increases 1 and exits the routine.

The conversion order table ADC_N shown in FIG.
As shown in 0, it is a table in which the A / D conversion order is stored for the 8th channel input to the 0th to 7th channels of the A / D converter 66, and the corresponding input channel is stored according to the data in the table indicated by the pointer ADC_I A / D conversion is performed. In this embodiment, basically 6,
A / D conversion is performed in the order of 7, 1, 4, 0, 2, 3, 5 and, for example, the cooling water temperature, the voltage, etc. are relatively changed, with the throttle opening, intake air amount, etc. having the fastest change as the first. The slowest one is set later, and the last 5th input channel is set to the crank sync input (however, as mentioned above, the last 5th input channel is ordered by the crank sync timing. change).

On the other hand, when it is not the first time processing in step S1000, the processing from step S1000 to step S10 is performed.
Proceed to 03, execute the read and store processing subroutine to the system shift buffer SSHB, which will be described later, read the previous A / D converted data from the corresponding channel of the A / D converter 66, and shift the read data to the system shift. Store in buffer SSHB.

The system shift buffer SSHB is
As shown in FIG. 22, the head offset addresses 0, +8, +1 in which the respective A / D conversion results of 8 channels are stored
It consists of memories of Nos. 6, +24, +32, +34, +36, and +38, and a 1-word memory at the start offset address -2 where the A / D conversion result of crank synchronization at every 4 ms is stored. One A / D conversion result executed each time is stored in one word (2 bytes).

4 from the start offset address 0
It is a multi-stage shift memory, and A / D every 90 ° CA.
The conversion result is stored and the latest 4 data (1 rotation) can be referred to from the job. The head offset addresses +32, +34, +36, and +38 are each 1
This is a word memory, and when the smoothing function is selected, a weighted average value of the A / D conversion results is stored to enable noise removal and accuracy improvement. The data is available for slow jobs.

Further, each head offset address + 8, +
From addresses 16 and 24, each is a 4-word memory,
It is designed to be used in 4ms jobs. In each of these memories, the latest A / D conversion result is counted from the beginning,
The value of the overlap counter OLC of the ms job is stored in the subsequent word, the data is read from the first word when the 4 ms job is executed, and the data of each subsequent word is sequentially shifted to the word in the first direction as the job ends. FIFO that is read from the previously stored data.
It is a buffer.

Thereafter, steps S1003 to S1004
In step S1005, the loop counter ADC_C (initial value is 8) for keeping a series of A / D conversion cycles every 4 ms is decremented by 1, and the loop counter ADC_C is set to 0 in step S1005.
If ADC_C ≠ 0, the process jumps to step S1007. When ADC_C = 0, that is, when a series of A / D conversions of 4 ms period is completed, in step S1006, pointer ADC_I and loop counter ADC_C are determined. Are respectively set to 0 and 8 which are initial values, and the process proceeds to step S1007.

At step S1007, Classen synchronization A / D
Check if there is a conversion request. This Classen synchronous A / D conversion request is a flag-like variable for instructing the crank synchronous A / D conversion for each 90 ° crank angle, and takes a value of 0 or 1 to calculate the crank position in the Classen interrupt. In the subroutine, when the crank position information variable S_CCAS is S_CCAS ≠ 1, it is set to the value 1 to instruct the crank synchronous A / D conversion.

That is, as described above, the A / D conversion of one channel out of the A / D conversion of eight channels is performed at every crank angle of 90 °, but when S_CCAS becomes 0 (BTDC97 °), When S_CCAS becomes 2 (BTDC 10 °), the crank-synchronized A / D conversion request is set to 1, and the A / D conversion is performed at every 90 ° crank angle for the A / D conversion order at every 0.5 ms. Make it interrupt.

If it is determined in step S1007 that there is no Krasen synchronization A / D conversion request, the flow advances from step S1007 to step S1008 to move the pointer ADC_
The corresponding channel corresponding to the conversion order table ADC_N value indicated by I is set, and the pointer A is set in step S1009.
Increase DC_I by 1 and exit the routine. On the other hand, if there is a classen synchronous A / D conversion request in step S1007, the process branches from step S1007 to step S1010, and the classen synchronous A / D conversion request is decremented by 1, and in step S1011, A / D conversion is performed. The crank synchronization input channel, which is the fifth channel of the device 66, is set and the routine exits.

That is, when a Krasen synchronization A / D conversion request is made, crank synchronization conversion is performed without increasing the pointer ADC_I, and the loop counter AD
Since C_C keeps the cycle of 8 channels and delays the subsequent A / D conversion order by 1, the crank-synchronized A / D conversion does not impair the equal time interval property, and the necessary data can be properly converted. Can be obtained at the timing.

In this case, the engine speed is 3750r.
At pm or higher, the last input of A / D conversion is completely stopped, and at 7500 rpm or higher, the second input from the last is stopped, but the order of A / D conversion is throttle opening, intake air amount. As the cooling water temperature and voltage are changed relatively slowly, the cooling water temperature and voltage are changed later, and the last A / D conversion order is set to the crank synchronization input. Absent.

Next, FIG. 1 shows the read and SSHB store processing subroutine in step S1003.
A description will be given according to the flowchart of No. 3. First, the step
In S1100, it is checked whether or not the dream mode variable DRM_AD that instructs the transition to the dream mode is zero.

The dream mode is a simulation mode for executing and debugging software while completely separated from the engine hardware.
As shown in FIG. 23, the dream mode variable DRM_AD for instructing the transition of the A / D conversion to the dream mode is provided with a 1-byte variable DRM_AD + n corresponding to the 8-channel input of the A / D converter 66. ing.

The dream mode includes an A / D conversion simulation mode and a Krasen / Kamsen input simulation mode. Transition to the dream mode of Kamsen / Krasen is checked in a background job.

Then, in step S1100, DRM_
When AD ≠ 0, a value other than zero is written in the dream mode variable DRM_AD, and the transition to the dream mode is instructed, the process proceeds from step S1100 to step S1101, and the dream mode variable DRM_AD is entered.
The value of the pseudo A / D conversion that is four times the value of is loaded into the accumulator A, and the process proceeds to step S1103.

On the other hand, in step S1100, DRM_A
When D = 0, the above steps S1100 to S11
Proceed to 02 to read the conversion result from the channel that was previously A / D converted and load it into accumulator A. In step S1103, the channel that was previously A / D converted is the Classen synchronous A / D conversion channel If it is a channel for Classen synchronous A / D conversion, the process proceeds to step S1114 and thereafter, and if it is not a channel for Classen synchronous A / D conversion (A / D conversion channel at fixed time intervals). ), The process proceeds to step S1104 and subsequent steps.

The processing after step S1104 is the same time A /
This is a process of storing the D conversion result at +8 or more addresses of the system shift buffer SSHB, and at step S1104, A
System shift buffer SSHB for storing each conversion result corresponding to channels 0 to 8 of the / D converter 66
21 in which the address of is stored is referred to, it is checked whether or not the store address of the A / D conversion result is 32 or more by referring to the SSHB store address table ADC_M.

In step S1104, when the store address of the A / D conversion result is not 32 or more, but the FIFO buffer of store address +8, +16, +24 used in the 4 mS job, the steps S1104 to S1105.
Proceed to step 4 ms job overlap counter O LC
Is limited to 3, the accumulator A is added to the address obtained by doubling the overlap counter OLC and adding the store address in step S1106, that is, the address of the FIFO buffer shifted in units of 2 bytes according to the job execution status. Stores the A / D conversion result loaded in, and exits the routine.

On the other hand, in step S1104, when the store address of the A / D conversion result is 32 or more, the function of branching from step S1104 to step S1107 and memorizing the A / D conversion result by weighted averaging Check whether there is a moderation cancel flag indicating that it is not used.

If there is a smoothing process cancel flag, the flow advances from step S1107 to step S1108 to store the A / D conversion result as it is in the corresponding store address and exit the routine, and there is no smoothing process cancel flag. From step S1107 above to step S1
Go to 109 and multiply the A / D conversion result by 16, then step S1110.
Then, it is checked whether or not it is the second round of smoothing processing.

In the case of the second round of smoothing processing,
The procedure advances from step S1110 to step S1111 to perform a 1/16 weighted average smoothing process on the current A / D conversion result, and in step S1112, the result is stored in the corresponding store address and the routine exits. When the process is the first process, not the second and subsequent annealing processes, the process proceeds from step S1110 to step S1113, and the A / D conversion result loaded in the accumulator A is set as the initial value in the corresponding store address. Store and exit the routine.

On the other hand, the previous A / D conversion channel is the Krasen synchronization A / D conversion channel, and
If the process proceeds from step S1103 to step S1114 and thereafter,
First, in step S1114, it is determined whether or not the pointer ADC_I is 8, that is, whether it is the Classen synchronous A / D conversion interrupted in the order of the isochronous A / D conversion, or the Classen synchronous A / D conversion set in advance at the end. Find out what.

If ADC_I ≠ 8 and the class-synchronous A / D conversion interrupts the preset conversion order, the steps S1114 to S11 are executed.
Proceeding to 15, the contents of the system shift buffer SSHB from addresses +0 to +6 are sequentially shifted to the subsequent words, and in step S1116, the system shift buffer SS
A / loaded in accumulator A at address 0 of HB
Store the D conversion result and exit the routine. As a result, 4 from the address 0 of the system shift buffer SSHB
Data for one rotation every 90 ° CA is stored in the word shift memory (see FIG. 22).

In step S1114, ADC_I
= 8, and the Classen synchronization A set at the end in advance
In the case of A / D conversion, the process proceeds from step S1114 to step S1117, and the A / D loaded in the accumulator A is loaded at address -2 of the system shift buffer SSHB.
The conversion result is stored as the Classen synchronization A / D conversion result in the preset A / D conversion order, and the routine exits.

The A / D conversion result stored in the system shift buffer SSHB as described above is used in each job. Next, the job execution subroutine will be described with reference to the flowcharts of FIGS.

First, in step S500, the job flag JB
By referring to _FLG, it is checked whether the job to be executed is not a class job. If it is not a class job,
The processing branches to label ALJ10, and if it is a class job, the process proceeds to step S501 to check whether or not cylinder discrimination is provided.

When the cylinder is not discriminated, the routine is not executed and the job is not executed. When the cylinder is discriminated, the steps from the step S501
In step S502, the value of the overlap counter OLC is referenced to check whether or not the multiplex wait state is set.

In step S502, when the multiplex waiting state is not set, the process proceeds to step S503, and the system variable S_ACAS (crank total position variable) calculated for each classen interrupt is set as the user variable ACAS, while in the multiplex waiting state, The process branches to step S504 and the user variable A
The new user variable ACAS is obtained by taking the remainder obtained by increasing CAS by 1 and dividing by 12, and this user variable ACAS
, 0, 1, 2, ..., 11, 0, 1 ,.

That is, the classen job and the low-priority classen job may be delayed by being disturbed by the job itself or a job with a high priority, but the classen interrupt is executed exactly in synchronization with the crank angle sensor signal, and the system variable S
_ACAS is updated regardless of job delay.

Therefore, the system variable S_AC is set in the job.
Knowing the crank position by referring to AS, and trying to perform work according to this crank position, but if you are delayed because of being disturbed by another job, know the crank position that corresponds to your work Can not be. Therefore, in the class job and the low-priority class job, the system variable S_ACAS for the OS is taken in as the user variable ACAS when not in the multiplex waiting state, and this user variable ACAS is updated each time the job is executed, and in the case of multiple request. Also, the appropriate processing corresponding to the crank position is performed.

Thereafter, the process proceeds from step S503 or step S504 to step S505 to set the work area of the job. In step S506, the level 0 interrupt is permitted. In step S507, the classen job section is entered. Then, the processing linked to this class job section is executed, and in step S508, the interrupt is prohibited and the routine exits.

Next, in step S500, when the job to be executed is not the class job, the label AL
In step S510 of J10, it is checked whether or not the job is a 2 ms job. When the job is a 2 ms job, the work area of the job is set in step S511. In step S512, the level 0 interrupt is permitted, and in step S513, the 2 ms job Go to section. Then, the job main body (a routine based on the control strategy on the user side or a service routine prepared on the OS side) linked to this section is executed, and in step S514, interrupt is prohibited and the routine exits.

On the other hand, if the job to be executed is not a 2 ms job in step S510, the process branches from step S510 to step S520 to check whether or not the job to be executed is a 4 ms job. If it is not a 4 ms job, the process branches to label ALJ30. If it is a 4 ms job, the work area of the job is set in step S521, and the process proceeds to step S522.

In step S522, the interrupt of level zero is permitted, and then in step S523, the switch input is read, and in step S524, the section of the 4 ms job is executed and the linked job main body is executed.
After that, when the section of the 4 ms job is exited, the interrupt is prohibited in step S525, the process proceeds to step S526,
The system shift buffer SSHB is shifted to exit the routine.

This 4 ms job receives A / D conversion data via the system shift buffer SSHB.
Although it is a D conversion use job, A / D conversion is accurately performed in a 4 ms cycle by a periodic interrupt every 0.5 ms, whereas a 4 ms job may be delayed by being interrupted by a high priority job.

Therefore, when executing the 4 ms job in step S524, the FIFO buffers +8 to +16 are used.
From the system shift buffer SSHB of addresses ~, +24 to, the address corresponding to the value of the overlap counter OLC, that is, the A / D conversion used in the next 4 ms job among the A / D conversion results stored in the interrupt generation order. After the 4 ms job is finished, the data in the FIFO buffer is sequentially shifted toward the beginning so that the result comes to the beginning at the step S526.

As a result, even when the 4 ms job is in the multiple interrupt state, the proper A / D conversion result can be received via the system shift buffer SSHB at the execution stage, and the processing result of the equal time interval processing can be obtained. Accurate control can be realized without causing contradiction.

On the other hand, when the job to be executed is not the 4 ms job in step S520 and the processing branches to the label ALJ30, the number of jobs to be executed is 10 in step S530.
It is checked whether the job is ms job or not, and if it is 10 ms job, the work area of the job is set in step S531,
If the level 0 interrupt is enabled in S532, step S5
At 33, the section moves to the 10 ms job section, the job main body is executed, and at step S534, interruption is prohibited and the routine exits.

In the 10 ms job section, a service routine for calculating the engine speed from the half rotation time, a service routine for creating the above-mentioned ignition schedule, etc. are prepared on the OS side.

If it is determined in step S530 that the job to be executed is not a 10 ms job, then step S5 is executed.
The process branches from 30 to step S540 to check whether the job to be executed is a low priority class job. If the job is not the low priority class job, the process branches from step S540 to the label ALJ50. If the job to be executed is the low priority class job, the process proceeds from step S540 to step S541, and the current state is the multiplex waiting state. Check if there is.

When the current state is not the multiplex wait state, the process proceeds from step S541 to step S542, the system variable S_ACAS (crank total position variable) is set as the user variable ACAS, and the process proceeds to step S544. After branching from step S541 to step S543 and incrementing the user variable ACAS by 1 to obtain the remainder, the process proceeds to step S544.

In step S544, the work area of the job is set, and in step S545, when the level 0 interrupt is permitted, in step S546, the section moves to the low priority class job, the job body is executed, and then step S547.
Disable the interrupt and exit the routine.

Further, in the label ALJ50, the step
In S550, it is checked whether or not the job to be executed is a 50 ms job. If the job is a 50 ms job, the process proceeds to step S551 to set the work area of the job, and the process proceeds to step S552.

If the level 0 interrupt is permitted in step S552, the process moves to the 50 ms job section in step S553, and the stalling processing routine prepared on the OS side,
The ignition timing retard routine for each cylinder, the fuel injection start timing setting routine, etc. are executed, and the routine based on the control strategy on the user side is executed. After the job is completed, the interrupt is prohibited in step S554, and the routine is exited.

On the other hand, if the job to be executed in step S550 is not a 50 ms job, then step S5
After branching from step 50 to step S560 and setting the work area of the job, in step S561 the level 0 interrupt is permitted, the process proceeds to step S562, the section area of the 250 ms job is entered, the job body is executed, and then step S5
Disable interrupt at 63 and exit the routine.

[0174]

As described above, according to the present invention, the conversion order of a plurality of input channels in the analog / digital converter is converted into an equal time interval analog / digital conversion in which the conversion is performed at regular intervals within a set time. The channel corresponding to crank-synchronized analog / digital conversion that performs conversion at a predetermined crank position of the engine is set in advance so that it starts at the corresponding channel, and corresponds to analog / digital conversion at equal time intervals within the set time. If the timing of crank-synchronized analog / digital conversion is reached before the conversion on all channels is completed, the crank-synchronized analog / digital conversion is performed on the corresponding channel, and the analog / digital conversion is performed at equal time intervals thereafter. 1 for the conversion order of the channel corresponding to In order not to change the number of analog / digital conversion executions within a set time as a delay, the crank synchronization of non-constant cycle is performed while maintaining the equal time interval property of analog / digital conversion that should be executed in a constant cycle. The analog / digital conversion can be executed, necessary data can be obtained at an appropriate timing, and the controllability can be improved.

[Brief description of drawings]

FIG. 1 is a flowchart of an A / D conversion subroutine.

FIG. 2 is a flowchart of periodic interrupt processing every 0.5 ms.

FIG. 3 is a flowchart of classen interrupt processing.

FIG. 4 is a flowchart of job priority processing.

FIG. 5 is a partial flowchart 1 of a job execution subroutine.

FIG. 6 is a partial flowchart 2 of a job execution subroutine.

FIG. 7 is a partial flowchart 3 of a job execution subroutine.

FIG. 8 is a partial flowchart 4 of a job execution subroutine.

FIG. 9 is a flowchart of a crank position calculation subroutine.

FIG. 10 is a flowchart of a half rotation time estimation subroutine.

FIG. 11 is a flowchart of a CCAS / RCAS discrimination subroutine.

FIG. 12: Flowchart of Classen timer overflow interrupt processing

FIG. 13 is a flowchart of a read and store process subroutine to SSHB.

FIG. 14 is an explanatory diagram showing a job execution state.

FIG. 15 is an explanatory diagram of a job flag.

FIG. 16 is an explanatory diagram of crank position variables.

FIG. 17 is an explanatory diagram showing changes in a job execution flag and an overlap counter.

FIG. 18 is an explanatory diagram of a classen interval table.

FIG. 19 is an explanatory diagram of a cylinder / crank position state map.

FIG. 20 is an explanatory diagram of a conversion order table.

FIG. 21 is an explanatory diagram of an SSHB store address table.

FIG. 22 is an explanatory diagram of a system shift buffer.

FIG. 23 is an explanatory diagram of dream mode variables.

FIG. 24 is a time chart showing a crank position and an engine stroke.

FIG. 25 is a schematic configuration diagram of an engine system.

FIG. 26 is a front view of a crank rotor and a crank angle sensor.

FIG. 27 is a front view of a cam rotor and a cam angle sensor.

FIG. 28 is a circuit configuration diagram of an electronic control system.

[Explanation of symbols]

 50 ECU 66 analog / digital converter ADC_N conversion order table

Claims (1)

[Claims] 1. An analog / digital conversion method in which channels of an analog / digital converter having a plurality of input channels are sequentially driven, and analog / digital conversion is performed a set number of times at each set time, the conversion of each channel. The order starts from the channel corresponding to the equal time interval analog / digital conversion which performs conversion at regular intervals within the above set time, and the last channel corresponding to the crank synchronous analog / digital conversion which performs conversion at a predetermined crank position of the engine. If the execution timing of the crank-synchronized analog / digital conversion comes before the conversion on all channels corresponding to the equal time interval analog / digital conversion is completed within the set time, , The above-mentioned crank sync analog / digital conversion on the corresponding channel Line, and an analog / digital conversion method which is characterized in that one delay and the converted order set in advance the conversion sequence of channels corresponding to the subsequent the isochronous analog / digital converter.