JPH06245486A - Back-type dc-dc converter circuit - Google Patents
Back-type dc-dc converter circuitInfo
- Publication number
- JPH06245486A JPH06245486A JP5304593A JP5304593A JPH06245486A JP H06245486 A JPH06245486 A JP H06245486A JP 5304593 A JP5304593 A JP 5304593A JP 5304593 A JP5304593 A JP 5304593A JP H06245486 A JPH06245486 A JP H06245486A
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- Prior art keywords
- current
- voltage
- switch element
- capacitor
- diode
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する分野】本発明は、バック型ＤＣ−ＤＣコ
ンバ−タ回路のスイッチング損失やサ−ジ電圧及びノイ
ズ低減に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of switching loss, surge voltage and noise of a buck type DC-DC converter circuit.
【０００２】[0002]
【従来の技術】図１は従来のバック型ＤＣ−ＤＣコンバ
−タ回路、図２は図１のバック型ＤＣ−ＤＣコンバ−タ
回路の代表的動作波形を示す。図１においてＱ1は主ス
イッチ素子でＦＥＴを例示している。Ｄ1及びＣossは、
前記主スイッチ素子Ｑ1に寄生する第１のダイオ−ド及
びコンデンサで、Ｖｉは直流電源、Ｌ1はチョ−クコイ
ル、Ｄ2はフライホイルダイオ−ド、Ｃ2は平滑用の第２
のコンデンサ、ＲＬは負荷、Ｖ0は出力電圧、すなわち
前記 （２） 第２のコンデンサＣ2の両端の電圧、Ｉ0は出力電流を表
している。2. Description of the Prior Art FIG. 1 shows a typical operation waveform of a conventional buck type DC-DC converter circuit, and FIG. 2 shows a typical operation waveform of the buck type DC-DC converter circuit. In FIG. 1, Q1 is a main switching element, which is an FET. D1 and Coss are
A first diode and a capacitor parasitic on the main switching element Q1, Vi is a DC power supply, L1 is a choke coil, D2 is a flywheel diode, and C2 is a second smoothing coil.
, RL is a load, V0 is an output voltage, that is, (2) the voltage across the second capacitor C2, and I0 is an output current.
【０００３】図２の動作波形において（１）は前記主ス
イッチ素子Ｑ１の駆動信号Ｑ１ＶGS、（２）は前記チョ
−クコイルＬ1に流れる電流ＩＬ1及び出力電流平均値Ｉ
0、（３）、（４）は各々前記主スイッチ素子Ｑ1のドレ
イン電流ＩDS、ドレイン・ソ−ス間電圧ＶDS、及びＤ1
の逆電圧ＶＲ、（５）は前記主スイッチ素子Ｑ1のドレ
イン電流ＩDSとドレイン・ソ−ス間電圧ＶDS（３）、
（４）が重なり合う期間の損失ＰLOSSである。ＴON、Ｔ
OFFは前記主スイッチ素子Ｑ1の導通、しゃ断時間を表し
Ｔは周期を表している。従来この種の回路では、前記出
力電圧Ｖ0は一般に次式で表す事が出来る。尚（４）の
点線波形は、Ｄ2の逆電圧Ｄ2ＶRである。In the operation waveform of FIG. 2, (1) is a drive signal Q1VGS of the main switching element Q1, and (2) is a current IL1 flowing through the choke coil L1 and an output current average value I.
0, (3) and (4) are the drain current IDS of the main switching element Q1, the drain-source voltage VDS, and D1 respectively.
The reverse voltage VR of (5) is the drain current IDS of the main switching element Q1 and the drain-source voltage VDS (3),
(4) is the loss PLOSS during the overlapping period. TON, T
OFF represents the conduction / interruption time of the main switch element Q1, and T represents the cycle. In the conventional circuit of this type, the output voltage V0 can be generally expressed by the following equation. The dotted line waveform of (4) is the reverse voltage D2VR of D2.
【０００４】Ｖ0＝ＴON／Ｔ・ＶiV0 = TON / T · Vi
【０００５】従って出力電圧Ｖ0を安定化させるために
は周期Ｔが一定であるＰＷＭ（パルス巾変調）制御方式
の場合、前記主スイッチ素子Ｑ1の導通時間ＴONをコン
トロ−ルして行っている。このため主スイッチ素子Ｑ1
の導通、しゃ断時に図２の（５）で示した様なスイッチ
ング損失が発生する。特に高周波で大容量コンバ−タを
動作させようとした時の損失は大きなものになり効率の
低下をまねく。Therefore, in order to stabilize the output voltage V0, in the case of the PWM (pulse width modulation) control method in which the period T is constant, the conduction time TON of the main switch element Q1 is controlled. Therefore, the main switch element Q1
When conducting and shutting off, the switching loss as shown by (5) in FIG. 2 occurs. In particular, when trying to operate a large capacity converter at high frequency, the loss becomes large and the efficiency is lowered.
【０００６】又図２の（３）、（４）の様に主スイッチ
素子Ｑ1の電流ＩDS、電圧Ｑ1ＶDS、フライホイ−ルダイオ
−ドＤ2の電圧Ｄ1ＶRが配線等の寄生インダクタンスに
依り、主スイッチ素子Ｑ1のＯＦＦの時及びフライホイ
−ルダイオ−ドＤ2のリカバリ−に依り、大きなサ−ジ
電圧やノイズが発生する。このため対策として、図３の
様に主回路部を並列に接続し電流の分散化を計って主ス
イッチ素子当りに流れる電流を減らして、損失及びサ−
ジ電圧の低減化を計ったりした。しかし小型化、コスト
の面で抜本的解決はならない問題がある。 （３）Further, as shown in (3) and (4) of FIG. 2, the current IDS of the main switching element Q1, the voltage Q1VDS, and the voltage D1VR of the flywheel diode D2 depend on the parasitic inductance of the wiring, etc. A large surge voltage and noise are generated depending on the OFF state and the recovery of the flywheel diode D2. For this reason, as a countermeasure, as shown in FIG. 3, main circuits are connected in parallel to disperse the current to reduce the current flowing per main switching element to reduce loss and increase
I also tried to reduce the voltage. However, there is a problem in that a drastic solution cannot be achieved in terms of downsizing and cost. (3)
【０００７】大容量コンバ−タにおける従来回路での問
題点を解決し、効率化、サ−ジ電圧の低減、低ノイズ化
を実現させるために本発明は成された。又従来の準共振
型コンバ−タにみられる主スイッチ素子の電圧、電流ス
トレスを軽減出来、更に制御上の難しさ等も解決出来、
コストアップ等の要因も少ない。The present invention has been made in order to solve the problems in the conventional circuit in the large capacity converter, and to realize the efficiency, the reduction of the surge voltage and the noise reduction. In addition, the voltage and current stress of the main switch element found in the conventional quasi-resonant converter can be reduced, and the difficulty in control can be solved.
There are few factors such as cost increase.
【０００８】[0008]
【実施例】図４は本発明の実施例であるバック型ＤＣ−
ＤＣコンバ−タの基本回路図、図５は図４のバック型Ｄ
Ｃ−ＤＣコンバ−タ回路の代表的な動作波形を示す。図
４に示す如く直流電源Ｖｉの＋側に主スイッチ素子Ｑ1
例えばＦＥＴのドレインを接続し主スイッチ素子Ｑ1の
ドレインソ−ス間に並列に第１のコンデンサＣ1と逆並
列に第１のダイオ−ドＤ1を接続し前記主スイッチ素子
Ｑ1のソ−ス側から直列にチョ−クコイルＬ1の一端とフ
ライホイ−ルダイオ−ドＤ2のカソ−ドが接続される。
前記フライホイ−ルダイオ−ドＤ2のアノ−ド側は前記
直流電源Ｖｉの−側に接続される。前記チョ−クコイル
のもう一方の側は平滑用の第２のコンデンサＣ2と負荷
抵抗ＲLが並列に接続され、前記平滑コンデンサＣ2と負
荷抵抗ＲLのもう一方の側は、並列に直流電源Ｖｉの−
側に接続される。FIG. 4 is a back type DC-type which is an embodiment of the present invention.
The basic circuit diagram of the DC converter, FIG. 5 is the back type D of FIG.
A typical operation waveform of the C-DC converter circuit is shown. As shown in FIG. 4, the main switch element Q1 is provided on the + side of the DC power source Vi.
For example, the drain of the FET is connected, the first capacitor C1 is connected in parallel between the drain sources of the main switching device Q1, and the first diode D1 is connected in antiparallel to the source side of the main switching device Q1. One end of the choke coil L1 is connected to the cathode of the flywheel diode D2.
The anode side of the flywheel diode D2 is connected to the-side of the DC power source Vi. A second smoothing capacitor C2 and a load resistor RL are connected in parallel on the other side of the choke coil, and the other side of the smoothing capacitor C2 and the load resistor RL are connected in parallel to the DC power supply Vi.
Connected to the side.
【０００９】又前記主スイッチ素子Ｑ1のドレイン・ソ
−ス間には、第２のチョ−クコイルＬ2とトランスＴ1、
補助スイッチ素子Ｑ2から成る直列回路が、並列に接続
される。更に前記トランスＴ1の２次側には、図４に示
した如くトランスＴ1の巻方向に順じて第３のダイオ−
ドＤ3のアノ−ドが接続され、前記トランスＴ1のもう一
方の側は直流電源Ｖｉの（−）側接続される。A second choke coil L2 and a transformer T1 are provided between the drain and source of the main switch element Q1.
A series circuit composed of the auxiliary switch element Q2 is connected in parallel. Further, the secondary side of the transformer T1 is provided with a third diode in the winding direction of the transformer T1 as shown in FIG.
The node D3 is connected, and the other side of the transformer T1 is connected to the (-) side of the DC power supply Vi.
【００１０】又、前記第３のダイオ−ドＤ3のカソ−ド
は直流電源Ｖｉの＋側に接続される。更に前記主スイッ
チ素子Ｑ1と前記補助スイッチＱ2にはＯＮ、ＯＦＦさせ
るための駆動回路が接続されているものとする。尚前記
トランスＴ1は１ （４） 次巻数Ｎｐ、２次巻数Ｎｓで構成され巻数比ｎ（＝ＮＰ
／ＮＳ）になっているものとする。The cathode of the third diode D3 is connected to the + side of the DC power supply Vi. Further, it is assumed that a drive circuit for turning on and off is connected to the main switch element Q1 and the auxiliary switch Q2. The transformer T1 is composed of 1 (4) secondary winding number Np and secondary winding number Ns, and the winding ratio n (= NP
/ NS).
【００１１】主スイッチ素子Ｑ1と補助スイッチＱ2のゲ
−トには図５（１）及び（２）のＱ1ＶGS、Ｑ2ＶGSの信
号が入力される。図５は本発明の実施動作回路図４の各
部の動作波形を示しており（１）は主スイッチ素子Ｑ1
のゲ−ト入力電圧Ｑ1ＶGS、（２）は補助スイッチ素子
Ｑ2のゲ−ト入力電圧Ｑ2ＶGS、（３）は主スイッチ素子
Ｑ1のドレイン電流Ｑ1Ｉｄ1、ドレイン電圧Ｑ1ＶDS、及
びフライホイ−ルダイオ−ドＤ2の電圧Ｄ2ＶR、（４）
は、第１コンデンサＣ1の充放電々流ＩＣ1と、第１のダ
イオ−ドＤ1の電流ＩF1、（５）は前記フライホイ−ル
ダイオ−ドＤ2の電流ＩF2と補助スイッチ素子Ｑ2のドレ
イン電流Ｉｄ2、Ｉ0は負荷電流を表している。（６）は
第２のチョ−クコイルＬ2に発生する電圧ＶＬ、期間ｔ1
〜ｔ7は本発明を説明する上で重要な代表的な１サイク
ルの時間を表している。The signals of Q1VGS and Q2VGS shown in FIGS. 5A and 5B are input to the gates of the main switch element Q1 and the auxiliary switch Q2. FIG. 5 shows an operation waveform of each part of the operation circuit of the present invention shown in FIG. 4. (1) shows the main switching element Q1.
Gate input voltage Q1VGS, (2) is the gate input voltage Q2VGS of the auxiliary switching device Q2, (3) is the drain current Q1Id1 of the main switching device Q1, the drain voltage Q1VDS, and the flywheel diode D2 voltage. D2VR, (4)
Is the charge / discharge current IC1 of the first capacitor C1 and the current IF1 of the first diode D1, and (5) is the current IF2 of the flywheel diode D2 and the drain currents Id2, I0 of the auxiliary switch element Q2. Represents the load current. (6) is the voltage VL generated in the second choke coil L2, period t1
.About.t7 represents a typical one cycle time which is important for explaining the present invention.
【００１２】以下に本発明のバック型ＤＣ−ＤＣコンバ
−タ回路の詳細動作を図４、図５を用いて説明する。説
明にあたっては簡単にするため負荷電流Ｉ0は定電流源
として扱い主スイッチ素子Ｑ1、補助スイッチ素子Ｑ2、
ダイオ−ドＤ1〜Ｄ3の電圧降下及び配線に依る電圧降下
は無いものとする。時間ｔ7〜ｔ1の期間は、主スイッチ
Ｑ1がタ−ンオン状態で直流電源Ｖｉのエネルギ−が第
１のチョ−クコイルに蓄積されると共に負荷ＲLに伝達
されている。従って前記主スイッチ素子Ｑ1には図５の
（３）のＱ1Ｉd1が流れている。The detailed operation of the buck type DC-DC converter circuit of the present invention will be described below with reference to FIGS. To simplify the explanation, the load current I0 is treated as a constant current source, and the main switch element Q1, the auxiliary switch element Q2,
It is assumed that there is no voltage drop in the diodes D1 to D3 and no voltage drop due to the wiring. During the period from time t7 to t1, the main switch Q1 is in the turn-on state, the energy of the DC power supply Vi is accumulated in the first choke coil and is transmitted to the load RL. Therefore, Q1Id1 of (3) in FIG. 5 flows through the main switch element Q1.
【００１３】時間ｔ1〜ｔ2の期間は、時刻ｔ1で主スイ
ッチＱ1がタ−ンオフすると今まで前記主スイッチ素子
Ｑ1に流れていた電流Ｑ1Ｉｄ1（＝Ｉ0）は第１のコンデ
ンサＣ1に転流される。このため前記第１のコンデンサ
Ｃ1の電圧、すなわち主スイッチ素子Ｑ1の電圧Ｑ1ＶDS
はゆるやかに立上がるため、ゼロ電圧スイッチング（Ｚ
ＶＳ）動作を行う。従ってスイッチング損失は極めて少
ないも （５） のとなる。During the period from time t1 to t2, when the main switch Q1 is turned off at time t1, the current Q1Id1 (= I0) flowing in the main switch element Q1 until now is commutated to the first capacitor C1. Therefore, the voltage of the first capacitor C1, that is, the voltage Q1VDS of the main switching element Q1.
Since it rises slowly, zero voltage switching (Z
VS) operation is performed. Therefore, the switching loss is extremely small, which is (5).
【００１４】（時間ｔ2〜ｔ3）時刻ｔ2で前記第１のコ
ンデンサＣ1の電圧が直流電源Ｖiに達すると、フライホ
イ−ルダイオ−ドＤ2がタ−ンオンし、第１のチョ−ク
コイルＬ1に蓄積されていたエネルギ−をフライホイ−
ルダイオ−ドＤ2を通して回生する。(Times t2 to t3) At time t2, when the voltage of the first capacitor C1 reaches the DC power source Vi, the flywheel diode D2 turns on and is stored in the first choke coil L1. Fly energy
Regenerate through Rediode D2.
【００１５】（時間ｔ3〜ｔ4）時刻ｔ3で補助スイッチ
素子Ｑ2がタ−ンオンする。フライホイ−ルダイオ−ド
Ｄ2に流れていた電流ＩF2は、前記補助スイッチ素子Ｑ2
に分流し時刻ｔ4で負荷電流Ｉ0に達する。又、この時前
記補助スイッチ素子Ｑ2に流れる電流Ｑ2Ｉｄ2の立上り
時間は、第２のチョ−クコイルＬ2とトランスＴ1の１次
側に発生する電圧によって決まる。式は、補助スイッ
チＱ2の電流Ｑ2Ｉｄ2の立上り時間を表したものであ
る。 △ｔ4＝（ｔ4−ｔ3）＝Ｌ1・Ｉ0／ＶL・・・・・ 但しＶLは第２のチョ−クコイルＬに発生する電圧で ＶL＝Ｖi−ｎＶi ∴ｎはＴ1の巻数比Ｎｐ／Ｎｓ で表すことができる。従って補助スイッチＱ2はゼロ電
流スイッチ（ＺＣＳ）動作を行うため、補助スイッチＱ
2のスイッチング損失は極めて少ないものとなる。又、
前記トランスＴ1の２次側には第３のダイオ−ドＤ3を通
して補助スイッチＱ2の電流Ｑ2Ｉｄ2の前記トランスＴ1
の巻数比倍の電流ｎ・Ｑ2Ｉｄ2倍が流れる。(Time t3 to t4) At time t3, the auxiliary switch element Q2 is turned on. The current IF2 flowing in the flywheel diode D2 is the auxiliary switch element Q2.
The load current I0 is reached at the shunting time t4. At this time, the rising time of the current Q2Id2 flowing through the auxiliary switch element Q2 is determined by the voltage generated on the primary side of the second choke coil L2 and the transformer T1. The equation represents the rise time of the current Q2Id2 of the auxiliary switch Q2. Δt4 = (t4−t3) = L1 · I0 / VL ... where VL is the voltage generated in the second choke coil L. VL = Vi−nVi∴n is the turn ratio Np / Ns of T1. Can be represented. Therefore, since the auxiliary switch Q2 operates as a zero current switch (ZCS), the auxiliary switch Q2
The switching loss of 2 is extremely small. or,
The transformer T1 of the current Q2Id2 of the auxiliary switch Q2 passes through the third diode D3 to the secondary side of the transformer T1.
A current n.multidot.Q2Id2 times that of the number of turns ratio flows.
【００１６】時間（ｔ4〜ｔ5） 時刻ｔ4で補助スイッチＱ2の電流Ｑ2Ｉｄ2が負荷電流Ｉ
0に達すると主スイッチ素子Ｑ1と並列に接続されている
第１のコンデンサＣ1の電圧（直流電源Ｖｉに充電され
ている。）が放電を開始する。この時前記第１のコンデ
ンサＣ1の電圧、すなわちＱ1ＶDSはゼロボルトになる。
従って、前記第１のコン （６） デンサＣ1の電圧がゼロボルトになるまでの時間と、
式より求められる。この時の補助スイッチ素子Ｑ2の電
流Ｑ2Ｉｄ2（ｔ5）はそれぞれ △ｔ5＝ｔ5−ｔ4＝１／ω・ＣＯＳ-・（−Ｖ1）／Ｖｉ−Ｖ1・・・ 但しω＝１／√・Ｌ1Ｃ1、Ｖ1＝Ｖｉ−ｎＶｉ Ｉｄ2(ｔ5)＝Ｉ0＋(Ｖｉ−ｎＶｉ)／Ｚ0・sinω△ｔ5・・・ 但しＺ0＝√・Ｌ1／Ｃ1 又前記第１のコンデンサＣ1がゼロボルトになるための
条件は、Ｖｉ≧２・ｎ・Ｖｉであるからｎ≦１／２でな
ければならない。更にフライホイ−ルダイオ−ドＤ2の
電圧は、前記フライホイ−ルダイオ−ドＤ2に流れてい
た電流ＩＦ2が、前記時刻ｔ4でゼロになってからゆるや
かに印加されるため、リカバリ−発生が少ないものとな
り、それによりサ−ジ、ノイズの発生は極めて少なくな
る。Time (t4 to t5) At time t4, the current Q2Id2 of the auxiliary switch Q2 becomes the load current I.
When it reaches 0, the voltage of the first capacitor C1 (which is charged in the DC power supply Vi) connected in parallel with the main switch element Q1 starts discharging. At this time, the voltage of the first capacitor C1, that is, Q1VDS becomes zero volt.
Therefore, the time until the voltage of the first capacitor (6) capacitor C1 becomes zero volt,
Calculated from the formula. The current Q2Id2 (t5) of the auxiliary switch element Q2 at this time is Δt5 = t5−t4 = 1 / ω · COS− · (−V1) / Vi−V1 ... where ω = 1 / √ · L1C1 and V1 = Vi−nVi Id2 (t5) = I0 + (Vi−nVi) / Z0 · sin ωΔt5 ... where Z0 = √ · L1 / C1 and the condition for the first capacitor C1 to be zero volt is Vi ≧ Since 2 · n · Vi, n ≦ 1/2 must be satisfied. Further, since the voltage of the flywheel diode D2 is slowly applied after the current IF2 flowing in the flywheel diode D2 becomes zero at the time t4, the recovery is less likely to occur. As a result, the generation of surge and noise is extremely reduced.
【００１７】時間（ｔ5〜ｔ6） 時刻ｔ5で第１のコンデンサＣ1の電圧すなわち主スイッ
チＱの電圧Ｑ1ＶDSがゼロボルトになると、補助スイッ
チＱ2の電流Ｑ2Ｉｄ2が第２のチョ−クコイルＬ2の作用
により第１のダイオ−ドＤ1を通して流れ続ける。この
期間△ｔ6は式により求めることができる。 △ｔ6＝(ｔ6−ｔ5)＝Ｌ1・(Ｑ2Ｉd2(ts)−Ｉ0)／ｎＶｉ・・・・ 又この期間に前記主スイッチ素子Ｑ1をタ−ンオンする
ことにより、ゼロ電圧スイッチング（ＺＶＳ）動作が可
能となる。Time (t5 to t6) At time t5, when the voltage of the first capacitor C1, that is, the voltage Q1VDS of the main switch Q becomes zero volts, the current Q2Id2 of the auxiliary switch Q2 becomes the first by the action of the second choke coil L2. Continue to flow through diode D1. This period Δt6 can be obtained by an equation. .DELTA.t6 = (t6-t5) = L1. (Q2Id2 (ts) -I0) / nVi ... Also, by turning on the main switching element Q1 during this period, zero voltage switching (ZVS) operation is performed. It will be possible.
【００１８】時間（ｔ6〜ｔ7） 時刻ｔ6で補助スイッチ素子Ｑ2に流れていた電流Ｑ2Ｉ
ｄ2は負荷電流Ｉ0に達するため、主スイッチ素子Ｑ1に
分流を始める。この期間は、式より求めることができ
る。 △ｔ7＝（ｔ7−ｔ6）＝Ｌ1・Ｉ0／ｎＶｉ・・・・ 従って前記補助スイッチＱ2のタ−ンオフは、前記補助
スイッチＱ2をゼロ電 （７） 流スイッチ（ＺＣＳ）動作を行わせるためには、時間ｔ
7以降に設定する必要がある。つまり、補助スイッチの
タ−ンオン時間△ｔQ2は△ｔ4＋△ｔ5＋△ｔ6＋△ｔ7以
上にする必要がある。Time (t6 to t7) At time t6, the current Q2I flowing through the auxiliary switch element Q2
Since d2 reaches the load current I0, shunting starts in the main switch element Q1. This period can be calculated by an equation. Δt7 = (t7−t6) = L1 · I0 / nVi ... Therefore, the turning off of the auxiliary switch Q2 causes the auxiliary switch Q2 to perform zero current (7) current switch (ZCS) operation. Is the time t
Must be set to 7 or later. That is, the turn-on time ΔtQ2 of the auxiliary switch needs to be Δt4 + Δt5 + Δt6 + Δt7 or more.
【００１９】図６、図７、図８は本発明の他の応用例を
示す。FIG. 6, FIG. 7 and FIG. 8 show other application examples of the present invention.
【００２０】[0020]
【発明の効果】本発明に依りバック型ＤＣ−ＤＣコンバ
−タ回路において、スイッチング時の共振作用に依り主
スイッチ素子のスイッチング損失を低減すると共に主ス
イッチ素子及びフライホイ−ルダイオ−ドのサ−ジ電
圧、ノイズの低減に効果があり、コンバ−タの低ノイズ
化、高効率化、小型化が実現出来、産業上の効果大であ
る。In the buck type DC-DC converter circuit according to the present invention, the switching loss of the main switching element is reduced by the resonance action at the time of switching, and the surge of the main switching element and the flywheel diode is reduced. It is effective in reducing voltage and noise, and can realize low noise, high efficiency and miniaturization of the converter, which is a great industrial effect.
【図１】従来のバック型ＤＣ−ＤＣコンバ−タ回路FIG. 1 is a conventional buck type DC-DC converter circuit.
【図２】従来のバック型ＤＣ−ＤＣコンバ−タ動作波形FIG. 2 is a conventional back-type DC-DC converter operation waveform
【図３】従来の大容量コンバ−タにおけるバック型ＤＣ
−ＤＣコンバ−タの対策回路FIG. 3 is a back type DC in a conventional large capacity converter.
-DC converter countermeasure circuit
【図４】本発明のバック型ＤＣ−ＤＣコンバ−タ回路FIG. 4 is a buck type DC-DC converter circuit of the present invention.
【図５】本発明のバック型ＤＣ−ＤＣコンバ−タ動作波
形FIG. 5 is a back-type DC-DC converter operation waveform of the present invention.
【図６】本発明の他の実施例回路図、その１FIG. 6 is a circuit diagram of another embodiment of the present invention, part 1
【図７】本発明の他の実施例回路図、その２FIG. 7 is a circuit diagram of another embodiment of the present invention, part 2
【図８】 （８） 本発明の他の実施例回路図、その３(8) Circuit diagram of another embodiment of the present invention, part 3
Ｖi・・・・直流電源 Ｑ1・・・・主スイッチ素子 Ｑ2・・・・第２のスイッチ素子 ＣOSS・・・主スイッチ素子の寄生コンデンサ Ｌ1・・・・第１のチョ−クコイル Ｌ2・・・・第２のチョ−クコイル Ｃ1・・・・第１のコンデンサ ＣＬ・・・ 平滑用コンデンサ Ｄ1・・・・第１のダイオ−ド Ｄ2・・・・フライホイ−ルダイオ−ド Ｄ3・・・・第２のダイオ−ド Ｔ1・・・・トランス ＲＬ・・・ 負荷 Vi ... DC power supply Q1 ... Main switch element Q2 ... Second switch element COSS ... Main switch element parasitic capacitor L1 ... First choke coil L2 ...・ Second choke coil C1 ・ ・ ・ First capacitor CL ・ ・ ・ Smoothing capacitor D1 ・ ・ ・ ・ First diode D2 ・ ・ ・ ・ ・ ・ Flywheel diode D3 ・ ・ ・Two diodes T1 ... Transformer RL ... Load
Claims (1)
素子及び第１のチョ−クコイルを通して負荷に電力を供
給する回路と、前記主スイッチ素子がＯＦＦの時、前記
第１のチョ−クコイルのエネルギ−を前記負荷に回生す
るフライホイ−ルダイオ−ドと、前記第１のチョ−クコ
イル出力を平滑する第２のコンデンサから成るバック型
ＤＣ−ＤＣコンバ−タに於いて、前記主スイッチ素子と
並列に前記主スイッチ素子の寄生コンデンサを含む第１
のコンデンサ及び逆並列の第１のダイオ−ドを接続し、
かつ前記主スイッチ素子に並列に第２のチョ−クコイル
とトランス及び補助スイッチ素子から成る直列回路を接
続し、さらに前記トランスの２次側の一端を第２のダイ
オ−ドのアノ−ド側に、他端を前記電源の（−）側に接
続し、前記第２のダイオ−ドのカソ−ド側を前記電源の
（＋）側に接続した事を特徴とするバック型ＤＣ−ＤＣ
コンバ−タ回路。1. A circuit for supplying power to a load through a main switch element and a first choke coil connected in series to a DC power supply, and a circuit for supplying power to the load when the main switch element is OFF. In a back-type DC-DC converter comprising a flywheel diode for regenerating energy to the load and a second capacitor for smoothing the output of the first choke coil, a parallel switch is provided in parallel with the main switch element. First, including a parasitic capacitor of the main switching element in
Connect the capacitor and the first diode in anti-parallel,
A series circuit composed of a second choke coil, a transformer and an auxiliary switch element is connected in parallel to the main switch element, and one end of the secondary side of the transformer is connected to the anode side of the second diode. , The other end is connected to the (-) side of the power source, and the cathode side of the second diode is connected to the (+) side of the power source.
Converter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5053045A JP2997608B2 (en) | 1993-02-18 | 1993-02-18 | Buck type DC-DC converter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5053045A JP2997608B2 (en) | 1993-02-18 | 1993-02-18 | Buck type DC-DC converter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06245486A true JPH06245486A (en) | 1994-09-02 |
| JP2997608B2 JP2997608B2 (en) | 2000-01-11 |
Family
ID=12931914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5053045A Expired - Lifetime JP2997608B2 (en) | 1993-02-18 | 1993-02-18 | Buck type DC-DC converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2997608B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2011001500A1 (en) * | 2009-06-30 | 2012-12-10 | 富士通株式会社 | DC-DC converter, module, power supply device and electronic device |
| US20140321172A1 (en) * | 2013-04-24 | 2014-10-30 | Daniel Princinsky | Systems and methods for a dc phaseback choke |
-
1993
- 1993-02-18 JP JP5053045A patent/JP2997608B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2011001500A1 (en) * | 2009-06-30 | 2012-12-10 | 富士通株式会社 | DC-DC converter, module, power supply device and electronic device |
| US20140321172A1 (en) * | 2013-04-24 | 2014-10-30 | Daniel Princinsky | Systems and methods for a dc phaseback choke |
| US9875841B2 (en) * | 2013-04-24 | 2018-01-23 | Applied Energy Llc | Systems and methods for a DC phaseback choke |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2997608B2 (en) | 2000-01-11 |
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