JPH06245108A - Television receiver - Google Patents

Abstract

PURPOSE:To allow an equalizer and a Y/C separator circuit to use a clock synchronization timing generating circuit in common. CONSTITUTION:An AV switch 51 selectively provides either an output video signal of a channel selection demodulator 2 or an external video signal. The output of the AV switch 51 is given to an equalization circuit 7 via an A/D converter 53 and also to a GC switch 55. The GC switch 55 selects an output of the AV switch 51 just after application of power and selects an output of the AV switch 51 subjected to waveform equalization by the equalization circuit 7. A Y/C separator circuit 15 separates an output of the GC switch 55 into a luminance signal and a chrominance signal, and a clock synchronization timing generating circuit 23 generates a clock and a timing signal and gives them to an equalizer 52 and the Y/C separator circuit 15. Since the equalizer 52 is arranged at a post-stage of the AV switch 51, even when the clock is fed to the equalizer 52 and the Y/C separator circuit 15, the effect of spurious radiation is less.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver, and more particularly to a television receiver suitable for digital construction.

[0002]

2. Description of the Related Art In recent years, television receivers compatible with the EDTV system have become widespread. In the EDTV system, a GCR (ghost cancellation reference) signal is inserted as a reference signal for removing a ghost on the broadcasting station side, and a motion adaptive three-dimensional Y / C separation circuit or the like is adopted on the receiving side to improve image quality. We are trying to improve.

FIG. 5 is a block diagram showing a conventional television receiver having such an equalizing function. FIG. 6 is a flow chart for explaining the operation. The basic configuration of the device in FIG. 5 is described in Reference 1 (Kamemoto et al.
Clear Vision Receiver with Built-in TSC Converter "Toshiba Review, 1991, Vol.46, No.11, pp.907-910), Reference 2
(Iga et al., "Ghost Clean TV Tuner", Toshiba Review, 1989, Vol.44, No.11, pp.898-901), and Document 3 (Patent Publication, Japanese Patent Publication No. 2-18790).
Etc.

The RF signal induced in the antenna 1 is given to the channel selection demodulator 2. Tuning microcomputer (hereinafter,
The tuning microcomputer 3) controls the tuning demodulator 2,
Demodulate a given channel. The demodulated video signal is supplied to the clock generation circuit 5 of the equalizer 4 and has a frequency of 4 fsc (fsc is a color subcarrier frequency = 3.579545).
The clock CK1 of MHz) is reproduced. The frequency 4fsc of the clock CK1 is a value that satisfies the Nyquist theorem for the band 4.2 MHz of the television video signal. The demodulated video signal operates on clock CK1
The signal is converted into a digital signal by the / D converter 6 and given to the equalizing circuit 7 and the waveform memory 8.

FIG. 7 is a block diagram showing a specific structure of the equalization circuit 7.

The output of the A / D converter 6 is the delay devices 31 and (l
+ M + 1) taps are applied to the transversal filter 32. The transversal filter 32 uses the clock CK1
, A group of latches 33 for delaying the input signal in units of cycle T, a group of multipliers 34 for multiplying the input signal and the delay signal from each latch of the latch group 33 by a tap coefficient, and tap coefficients (c-1 to c0).
To cm) for storing tap coefficients and an adder 36 for adding the outputs of the multipliers of the multiplier group 34.

As will be described later, the tap coefficient memory 35 is provided with a tap coefficient corresponding to the distortion of the input signal from the CPU 10. In this way, the transversal filter 32 equalizes the waveform of the input signal and outputs a ghost canceling signal for removing a ghost having a delay time of -IT to mT seconds to the adder 37. The input signal is input to the adder 37 after being delayed by the delay unit 31 for 1T seconds, and the adder 37 subtracts the ghost cancellation signal from the input signal,
The video signal from which the ghost has been removed is output to the adder 38.

The output of the adder 38 is a delay device having a delay time of mT.
It is given to the transversal filter 40 via 39.
The configuration of the transversal filter 40 is similar to that of the transversal filter 32. Transversal filter 40
The tap coefficient memory 43 stores the tap coefficients cm + 1 to cn. The tap coefficients cm + 1 to cn correspond to ghosts having a delay time of (m + 1) T to nT seconds, and the transversal filter 40 has a ghost cancellation signal for canceling a ghost having a delay time of (m + 1) T to nT seconds. Is output to the adder 38. The adder 38 removes the ghost cancellation signal from the output of the adder 37 and outputs the ghost removal signal to the waveform memory 8 and the D / A converter 9. In this way, the equalization circuit 7 can remove a ghost having a delay time of -IT to nT seconds.

In the above description, the ghost is taken as an example of the waveform distortion, but the frequency characteristic of the tuning demodulator 2 is disturbed or the frequency characteristic is disturbed by the reflection between the antenna and the tuning demodulator 2. Also becomes waveform distortion and can be removed by the equalization circuit 7.

The transversal filter 32 is non-cyclically connected in order to remove the front ghost, but the transversal filter 40 is cyclically connected so that the output of the delay device 39 is waveform-equalized and returned to the adder 38. ing.

The tap coefficient is modified by the CPU 10 of the arithmetic control circuit 19. The waveform memory 8 takes in the GCR signal included in the input / output of the equalization circuit 7. Further, the ROM 9 stores the same reference signal as the GCR signal inserted in the input television video signal. CPU 10 is waveform memory 8
And the data read from the ROM 9 for working R
The tap coefficient is corrected so that the output waveform distortion from the equalization circuit 7 is set to 0 by performing a predetermined calculation using AM11. The GC included in the input / output of the equalization circuit 7
The extraction timing of the R signal is controlled by the synchronization timing circuit 12. The demodulated video signal is also given to the synchronization timing circuit 12 via the synchronization switch 13, and the synchronization timing circuit 12 creates a timing signal based on the clock CK1 and outputs it to the CPU 10 and the waveform memory 8.

The tap coefficient calculation algorithm is described in detail in Document 2 and the like, and its explanation is omitted.

The ghost elimination signal of the equalization circuit 7 is converted into an analog signal by the D / A converter 9, and the AV switch
It is input to the Y / C separation circuit 15 via 14. An external video signal is also input to the AV switch 14 via the terminal 20.
The AV switch 14 is switched and controlled by the channel selection microcomputer 3 and outputs one of two inputs. The output of the AV switch 14 is given to the clock generation circuit 17 and the synchronization timing circuit 18 of the clock / synchronization / timing generation means 16. The synchronization timing circuit 18 extracts a synchronization signal from the output of the AV switch 14, and outputs the timing signal to the clock generation circuit 17 and Y /
Output to the C separation circuit 15. The clock generation circuit 17 uses the output of the AV switch 14 and the timing signal to generate a clock
K2 is generated and output to the Y / C separation circuit 15. The Y / C separation circuit 15 is supplied with the clock CK2 and the timing signal, and separates the input video signal into a luminance signal and a color signal and outputs them.

Next, the operation of the circuit of FIG. 5 will be described with reference to the flowchart of FIG.

Now, when the power is turned on in step S1 of FIG. 6, the channel selection microcomputer 3 causes the channel selection demodulator 2 to demodulate the last selected channel when the power is turned off. Further, the tuning microcomputer 3 controls the synchronization switch 13 in step S2 to give the output of the tuning demodulator 2 to the synchronization timing circuit 12. As a result, the synchronization timing circuit 12 generates a timing signal. At this point, the sync signal portion and the burst portion of the video signal are affected by waveform distortion such as ghost. In step S3, the channel selection microcomputer 3 switches the AV switch 4 so as to select the previously viewed video signal.

When an external video signal is selected, that is, an external video signal in a band of a non-broadcasting wave or a broadcasting wave or more which does not include a GCR signal such as a VTR (video tape recorder) or a laser disk is selected. If you do,
The tuning microcomputer 3 does not operate the equalizer 4 and shifts the processing from step S4 to step S5 and waits for the subsequent operation.

On the contrary, when it is detected in step S4 that the broadcast wave is selected, the tuning microcomputer 3 controls the CPU 10 to operate the equalizer 4. This allows the CPU
10 sequentially finds the tap coefficient by using, for example, the successive correction method disclosed in Document 2 (step S6
). The tap coefficient calculation result of the CPU 10 is transferred to the tap coefficient memories 35 and 43 of the equalization circuit 7 in step S7, and the equalization circuit 7 performs waveform equalization by the tap coefficient. This tap coefficient calculation and tap coefficient transfer are performed a predetermined number of times, and the process proceeds from step S8 to step S9.

In step S9, the CPU 10 causes the synchronous switch 13 to select the output of the D / A converter 9. As a result, the synchronization timing circuit 12 can generate a timing signal by using a synchronization signal and a burst in which waveform distortion such as a ghost is reduced and the disturbance is small. Therefore,
After this, more stable tap coefficient calculation (step S10)
And, the tap coefficient transfer (step S11) becomes possible.

By the way, as described above, the AV switch
Reference numeral 14 is for switching between a broadcast wave and an external video signal, and since the GCR signal is included only in the broadcast wave, the equalizer 4 for removing the ghost from the broadcast wave is an AV device.
It is arranged in front of the switch 14. In this way, the analog video signal from the equalizer 4 or the analog external video signal is input to the AV switch 14. In recent years, television receivers have been digitized, and the Y / C separation circuit 15 in the subsequent stage of the AV switch 14 is composed of a digital circuit. That is, the front stage of the AV switch 14 is composed of an analog circuit and the rear stage is composed of a digital circuit.
In this case, in order to prevent the influence of the relatively large unnecessary radiation generated from the digital circuit, the device in the preceding stage of the AV switch 14, that is, the channel selection demodulator to which the relatively small analog signal is input, is mounted. 2. Equalizer 4 placed in a shield case and AV for switching analog video signals
The board forming the switches 14 and the like and the board forming the Y / C separation circuit 15 placed in the shield case are separate boards, or the front stage and the rear stage of the AV switch 14 are sufficiently separated from each other. Arrange.

That is, considering the influence of unwanted radiation, the signals from one clock generation circuit and the synchronization timing circuit cannot be supplied to both the equalizer 4 and the Y / C separation circuit 15. As described in 5, there is a drawback that these circuits must be provided separately.

[0021]

As described above, in the above-described conventional television receiver, in order to prevent the influence of unnecessary radiation, the equalizer and the Y / C separation circuit are used to form a circuit. There is a problem that the circuit scale becomes large because it cannot be shared.

The present invention has been made in view of the above problems, and allows the equalization device and the Y / C separation circuit to share the circuit, thereby reducing the circuit scale and the cost. It is intended to provide a television receiver.

[Constitution of Invention]

According to a first aspect of the present invention, there is provided a television receiver which selects a demodulation means for selecting and demodulating a received video signal, and a video signal from the demodulation means. First selection means for selectively outputting one of the other video signals, A / D conversion means for digitizing the output of the first selection means, transversal filter with variable tap coefficient, And a calculation control means for obtaining a tap coefficient for removing a waveform distortion component included in the output video signal of the A / D conversion means from the reference signal in the storage means. Equalization means for waveform-equalizing and outputting the output video signal of the A / D conversion means, D / A conversion means for returning the output of the equalization means to an analog signal, and output video signal of the first selection means. And the above D
Second selecting means for selectively outputting one of the output video signals of the A / A converting means, and clock / timing generating means for generating a clock signal and a timing signal from the output video signal of the second selecting means, The television receiver according to claim 2 of the present invention comprises Y / C separation means for separating a luminance signal and a chrominance signal from the output video signal of the second selection means. Channel demodulating means for selecting and demodulating a signal, first selecting means for selectively outputting one of the video signal from this channel demodulating means and another video signal, and the first selecting means. And an equalizing means for equalizing the waveform of the output video signal from the first selecting means and an output video signal of the first selecting means in the initial state, and selecting and outputting the output video signal of the equalizing means after the initial state has passed. Second selection means and this second Y / C separation means for separating a luminance signal and a color signal from the output video signal of the selection means, and a clock / timing generation means for generating a clock signal and a timing signal from the output video signal of the second selection means. According to claim 3 of the present invention, a television receiver selects a channel of a received video signal and demodulates it, and a video signal from this channel demodulation means and another video signal. First selecting means for selectively outputting one of
A / D conversion means for digitizing the output of the first selection means, a transversal filter with a variable tap coefficient, a memory means for taking in a reference signal in a video signal, and a reference signal in the memory means An equalization unit that includes a calculation control unit that obtains a tap coefficient for removing a waveform distortion component included in the output video signal of the A / D conversion unit, and equalizes and outputs the output video signal of the A / D conversion unit. A second selection means for selectively outputting one of the output video signal of the first selection means and the output video signal of the equalization means, and a clock signal from the output video signal of the second selection means. And a clock / timing generating means for generating a timing signal, and a Y / C separating means for separating a luminance signal and a chrominance signal from the output video signal of the second selecting means.

[0024]

In the present invention, the equalizing means is arranged after the first selecting means. The second selecting means selectively outputs one of the output video signal of the first selecting means and the output video signal of the equalizing means, and the Y / C separating means outputs the video signal from the output of the second selecting means. Separated from the luminance signal. The clock / timing generating means supplies the generated clock signal and timing signal to the equalizing means and the Y / C separating means. Since the equalizing means is arranged after the first selecting means, even if the clock / timing generating means supplies a clock to both the equalizing means and the Y / C separating means, the influence of unnecessary radiation is small. .

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention. In FIG. 1, the same components as those in FIG. 5 are designated by the same reference numerals.

An RF (high frequency television) signal is induced in the antenna 1. This RF signal is input to the channel selection demodulator 2. The tuning demodulator 2 is controlled by the tuning microcomputer 3 to tune and demodulate the RF signal of a predetermined channel and output a demodulated video signal. In the present embodiment, the demodulated video signal is applied to the equalizer 52 via the AV switch 51 which constitutes the first selecting means. An external video signal is also input to the AV switch 51, and the AV switch 51 is controlled by the channel selection microcomputer 3 so that one of two inputs is equalized by the equalizer 52.
Output to.

A clock CK2, which will be described later, is applied to the A / D converter 53 of the equalizer 52, and the demodulated output is converted into a digital signal by using this clock CK2 and applied to the equalizer circuit 7 and the waveform memory 8. The equalization circuit 7 has the same configuration as that of FIG. The waveform memory 8 is controlled by the arithmetic control circuit 56 to take in the GCR signal included in the input / output of the equalization circuit 7. The arithmetic control circuit 56 has the same configuration as the arithmetic control circuit 19 of FIG. 5, and has a CPU, a ROM, and a working RAM. The arithmetic control circuit 56 performs a tap coefficient correction calculation using the GCR signal taken into the waveform memory 8 to correct the tap coefficient of the tap coefficient memory of the equalization circuit 7. The equalization circuit 7 equalizes the waveform based on the tap coefficient, removes the waveform distortion component of the video signal from the AV switch 51, and outputs it to the D / A converter 54.

The D / A converter 54 is supplied with the clock CK2, uses the clock CK2 to convert the ghost-free video signal into an analog signal, and outputs the analog signal to the GC switch 55 as the second selecting means. In this embodiment,
The demodulated output from the AV switch 51 is also given to the GC switch 55. The GC switch 55 is controlled by the arithmetic control circuit 56 to selectively output one of the two inputs.

The output of the equalizer 52 is input to the Y / C separation circuit 15 and also the clock / synchronization / timing generation circuit.
Also entered in 23. The clock / synchronization / timing generation circuit 23 has the same configuration as that of FIG. 5, and is composed of the clock generation circuit 21 and the synchronization timing circuit 22. The synchronization timing circuit 22 creates a timing signal from the input video signal to generate the Y / C separation circuit 15 and the clock generation circuit 21.
Output to. Further, the synchronous timing circuit 22 outputs the timing signal to the arithmetic control circuit 56.
The clock generation circuit 21 generates a clock CK2 based on the video signal and the timing signal, and the Y / C separation circuit 15,
It outputs to the D / A converter 53 and the A / D converter 54. Y / C
The separation circuit 15 separates the ghost-removed video signal into a luminance signal and a chrominance signal by using the clock CK2 and the timing signal, and outputs them.

The equalizer 52 at the latter stage of the AV switch 51
And the Y / C separation circuit 15 are arranged on the same substrate or at positions close to each other.

Next, the operation of the embodiment thus constructed will be described with reference to the flowchart of FIG. In FIG. 2, the same steps as those in FIG. 6 are designated by the same reference numerals.

When the power is turned on in step S1 of FIG. 2, the tuning microcomputer 3 controls the tuning demodulator 2 to
Demodulate the last selected channel. Step S1
Immediately after the end, the arithmetic control circuit 56 causes the GC switch 55 to select the input of the equalizer 52 by an instruction to the tuning microcomputer 3 (step S21). As a result, the output of the AV switch 51 passes through the equalizer 52 and is supplied to the Y / C separation circuit 15 and the clock / synchronization / timing generation circuit 23.

Clock / sync / timing generator 23
Immediately after the power is turned on, an external input video signal such as a non-broadcast wave or a video signal of a broadcast wave that is disturbed by waveform distortion such as ghost is input, and the synchronization signal part and the burst part of this video signal are input. Clock C used in the entire device
Generate K2 and timing signals. The frequency of the clock CK2 generated by the clock generation circuit 21 is 4 fsc.

Next, in step S3, the channel selection microcomputer 3 controls the switching of the AV switch 51 to select the last selected video signal when no special operation is performed. When the external video signal from the VTR or the laser disk is selected by the AV switch 51, since it is a non-broadcast wave in which the GCR is not inserted, the process proceeds from step S4 to step S5, and the tuning microcomputer 3 is selected. Does not operate the equalizer 52 and waits for the subsequent operation.

On the contrary, when the broadcast wave is selected, the tuning microcomputer 3 operates the equalizer 52. AV switch 51
The video signal of the broadcast wave from is converted into a digital signal by the A / D converter 53 and given to the equalization circuit 7. The equalization circuit 7 performs waveform equalization based on the tap coefficient to perform D / A
Output to the converter 54. The D / A converter 54 converts the output of the equalization circuit 7 into an analog signal and gives it to the GC switch 55.

The tap coefficient of the equalization circuit 7 is calculated by the arithmetic control circuit.
56 is sequentially obtained from the input / output of the equalization circuit 7 and the reference signal taken into the waveform memory 8 by the sequential correction method (step S6). In this case, the arithmetic control circuit 56 controls the waveform memory 8 and the equalization circuit 7 using the synchronization signal and the timing signal from the clock / synchronization / timing generation circuit 23. That is, at this time point, the sync signal and the timing signal obtained from the video signal which is not waveform-equalized are used for the calculation of the tap coefficient. The obtained tap coefficient is transferred to the tap coefficient memory in the equalization circuit 7 (step S7).

In the next step S8, it is determined whether or not the number of tap coefficient calculations reaches a predetermined number. When the tap coefficient calculation is repeated a predetermined number of times, the process proceeds to step S22 and the waveform-equalized video signal is output. That is,
The GC switch 55 is controlled by the arithmetic control circuit 56, and the D / A
Select the output of converter 54. As a result, the composite video signal from which the waveform distortion such as ghost is removed is applied to the Y / C separation circuit 15 and the clock / synchronization / timing generation circuit 23.

The Y / C separation circuit 15 obtains a luminance signal and a color difference signal from which waveform distortion such as ghost is removed.
The clock / synchronization / timing generation circuit 23 generates a clock CK2 having a small jitter and a stable synchronization timing signal by using a synchronization signal and a burst signal which are stable by removing a waveform distortion such as a ghost.

By the way, from the GC switch 55 to the equalizer 52
When the input of is output, the composite video signal input to the clock / synchronization / timing generation circuit 23 includes a waveform distortion component such as a ghost, but the GC switch 55
Is switched to the output of the D / A converter 54, the composite video signal after the waveform distortion component such as ghost is removed is input to the clock / synchronization / timing circuit 23. Since the clock / synchronization / timing generation circuit 23 reproduces the reproduction clock based on the color burst,
The phase of the reproduced clock may change at the switching timing of the GC switch 55.

Therefore, in the present embodiment, after the GC switch 55 is switched to output the ghost-removed video signal from the equalizer 52, step S
At 23, the operation wait state is set. As a result, the arithmetic control circuit 56 does not perform the tap coefficient correction calculation, and the equalization circuit 7 performs waveform equalization using the tap coefficient obtained in steps S6 to S8 as it is.

By the way, the GCR signal of the 8-field sequence, which is the reference signal, is defined by the cycle position of the color burst (Reference 4 (Kawauchi, "Standardization of Method and Deliberation Status", Journal of Television Society, 1989, Vol.43, No.
5, pp.435-439))). Therefore, if the GC switch 55 is switched in step S22 after obtaining the tap coefficient, the clock phase changes and the sample value of the reference signal changes.
However, since the frequency of the clock CK2 satisfies the Nyquist theorem, the video signal before and after the switching of the GC switch 55 does not change even if the clock phase changes.
Further, when the GC switch 55 is switched in step S22, the tap coefficient of the equalizing circuit 7 is already determined. Therefore, even if the clock phase changes, the output analog video signal of the D / A converter 54 will not be a ghost. The waveform distortion remains unchanged and remains unchanged.

As described above, in this embodiment, the GC switch 55 is used to provide a through route for allowing the input of the equalizer 52 to pass therethrough. Immediately after the power is turned on, a synchronizing signal is generated based on the video signal passing through the through route. Further, after the timing signal is generated and the output of the equalizer 52 is used after the tap coefficient is determined, the equalizer 52 can be arranged at the subsequent stage of the AV switch 51. As a result, the equalizer 52 and the Y / C
The separation circuit 15 and the separation circuit 15 can be provided on the same substrate or at positions close to each other, and the clock generation circuit and the synchronization timing circuit can be shared.

As described in Document 2, the performance of the clock / synchronization / timing generation circuit 23 has been improved in recent years, and even a ghost of D / U 6 dB can be removed without any problem. When a stronger ghost arrives, the phase jitter of the reproduction clock and the reproduction synchronization signal becomes large, which may make it impossible to remove the ghost. In this case, a known 8-field sequence GCR signal detection method is used. It is only necessary to cause the GC switch 55 to select the through route by using, and it is possible to prevent the image for which ghost removal has failed from being output.

Further, since the video signal before and after the switching of the GC switch 55 in step S22 does not change even if the clock phase changes, the tap coefficient calculation is performed with a minute correction amount to bring the continuous operation state into a gentle operation. It can also be adapted to various ghost changes. In addition, GC switch 55
As a matter of course, it is desirable to avoid switching during the capture of the 8-field sequence GCR.

Furthermore, instead of the iterative correction method, reference 5 (Nishikawa et al., "A Study on Suppression of Unwanted Tap Coefficients in Ghost Cancellers", Technical Report of the Television Society, ITEJ T
echnical Report Vol.16, No.27, pp.13-18, VIR'92-18, C
E'92-19, Mar. 1992), the GC switch 55 may be switched in step S22 after the tap coefficient is obtained using the collective arithmetic method. In this case, the waveform memory 8 need only fetch the input video signal of the equalization circuit 7.

FIG. 3 is a block diagram showing another embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the equalizer 52 and the Y / C separation circuit 15 are used.
And instead of the clock / synchronization / timing generation circuit 23,
This embodiment differs from the embodiment of FIG. 1 in that an equalizer 61 without the D / A converter, a digital Y / C separation circuit 62, and a clock / synchronization / timing generation circuit 63 are provided.

The output of the AV switch 51 is given to the A / D converter 53, and the output of the A / D converter 53 is given to the equalization circuit 7, the waveform memory 8 and the GC switch 60. The output of the equalization circuit 7 is output via the GC switch 60. That is, GC
The switch 60 receives a digital video signal that has not been waveform-equalized or a digital video signal that has been waveform-equalized by the equalization circuit 7.

The digital video signal from the GC switch 60 is given to the Y / C separation circuit 62, and the Y / C separation circuit 62 separates the video signal into a luminance signal and a chrominance signal and outputs it. The clock / sync / timing generator 63 is a clock generator
64 and the synchronization timing circuit 65,
A clock CK2 and a synchronization timing signal are generated from the input digital video signal.

In the embodiment constructed as described above,
A digital video signal is output from the GC switch 60 of the equalizer 61, and the Y / C separation circuit 62 and the clock / synchronization / timing generation circuit 63 perform digital video signal processing.
Other operations are the same as in FIG.

Note that this configuration is compatible with a digital television receiver.

FIG. 4 is a block diagram showing another embodiment of the present invention. 4, the same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

This embodiment differs from the embodiment of FIG. 3 in that an equalizer 71 and a clock / synchronization / timing generation circuit 72 are employed. The clock / synchronization / timing generation circuit 72 is composed of a clock generation circuit 75 and a synchronization timing circuit 76, and generates a clock CK4 having a frequency of 8 fsc and a synchronization timing signal. As disclosed in Document 4, when a clock having a frequency of 8 fsc is adopted, it is convenient for performing sequential scanning line conversion.

The equalizer 71 gives the output of the A / D converter 53 to the equalizer circuit 7 and the waveform memory 8 through the thinning circuit 73,
The output of the equalization circuit 7 is passed through the interpolation circuit 74 to the GC switch 60.
Is given to. The A / D converter 53 uses the clock CK4 to convert the output of the AV switch 51 into a digital signal.
The thinning circuit 73 thins the output of the A / D converter 53 to halve the frequency rate and supplies it to the equalizing circuit 7 and the waveform memory 8. The interpolation circuit 74 interpolates the output of the equalization circuit 7 to restore the frequency rate to the original and outputs it to the GC switch 60.

In the embodiment constructed as described above,
The clock / synchronization / timing generation circuit 72 creates a clock CK4 having a frequency of 8 fsc. Since the characteristics of the GCR signal are set by using one clock difference with a frequency of 4fsc, using the clock CK4 with a frequency of 8fsc in the equalization circuit 7 has no advantage because the equalization delay time range is halved. Not at all. For this reason, A / D
The output of the converter 53 is decimated by the decimating circuit 73 to reduce the frequency rate to 1/2, and the result is given to the equalizing circuit 7 and the waveform memory 8. As a result, it is not necessary to change the equalization circuit 7, the waveform memory 8 and the operation control circuit 56, and the tap coefficient operation may be the same as the conventional one. Also, the equalization delay time range is not halved. The output of the equalization circuit 7 is returned to the original frequency rate by the interpolation circuit 74 and output to the GC switch 60.

As described above, the present embodiment has an advantage that it is suitable for performing sequential scanning line conversion in addition to the effect similar to that of the embodiment of FIG.

The present invention is not limited to the above embodiments, and a non-recursive transversal filter may be used as the equalization circuit 7, and the actual I
An input weighted type often used in the C circuit may be used. Further, the tap coefficient calculation method is not limited, and other than the successive correction type or the training type, for example,
A method of equalization in the frequency domain, a method of collectively obtaining by matrix calculation, or a high-speed removal algorithm such as the RLS method may be adopted.

In general, since the timing signal required by the Y / C separation circuit or the scanning line conversion circuit is different from the timing signal required by the equalizer, the basic horizontal and vertical timing signals etc. Of course, only the timing signal generating circuit to be generated may be shared, and the timing signals required in the equalizer may be generated using these basic timing signals.

[0059]

As described above, according to the present invention, the circuit can be shared by the equalizer and the Y / C separation circuit, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional television receiver.

FIG. 6 is a flowchart for explaining the operation of the conventional example.

FIG. 7 is a circuit diagram showing a specific configuration of an equalization circuit.

[Explanation of symbols]

2 ... Tuning demodulator, 3 ... Tuning microcomputer, 15 ... Y / C separation circuit, 23 ... Clock / synchronization / timing generation circuit, 51 ... A
V switch, 52 ... Equalizer

Claims (4)

[Claims] 1. A channel selection demodulation means for selecting and demodulating a received video signal, and a first selection means for selectively outputting one of a video signal from this channel selection demodulation means and another video signal. An A / D conversion means for digitizing the output of the first selecting means, a transversal filter with a variable tap coefficient, a storage means for taking in a reference signal in a video signal, and a reference signal in the storage means. From the A / D converting means to a tap coefficient for removing a waveform distortion component included in the output video signal, the output video signal of the A / D converting means is waveform-equalized and output. Equalizing means, D / A converting means for returning the output of the equalizing means to an analog signal, and one of the output video signal of the first selecting means and the output video signal of the D / A converting means. Second selecting means for outputting, and Clock / timing generation means for generating a clock signal and a timing signal from the output video signal of the second selection means, and a Y / C separation means for separating a luminance signal and a color signal from the output video signal of the second selection means. A television receiver characterized by comprising: 2. A channel selection demodulation means for selecting and demodulating a received video signal, and a first selection means for selectively outputting one of a video signal from this channel selection demodulation means and another video signal. And an equalizing means for equalizing the waveform of the output video signal from the first selecting means, and an output of the equalizing means when the output video signal of the first selecting means is selected in the initial state and the initial state has passed. Second selecting means for selecting and outputting a video signal, Y / C separating means for separating a luminance signal and a chrominance signal from the output video signal of the second selecting means, and an output of the second selecting means A television receiver comprising: a clock / timing generating means for generating a clock signal and a timing signal from a video signal. 3. A channel selection demodulation means for selecting and demodulating a received video signal, and a first selection means for selectively outputting one of the video signal from this channel selection demodulation means and another video signal. An A / D conversion means for digitizing the output of the first selecting means, a transversal filter with a variable tap coefficient, a storage means for taking in a reference signal in a video signal, and a reference signal in the storage means. From the A / D converting means to a tap coefficient for removing a waveform distortion component included in the output video signal, the output video signal of the A / D converting means is waveform-equalized and output. An equalizing means, a second selecting means for selectively outputting one of an output video signal of the first selecting means and an output video signal of the equalizing means, and an output video signal of the second selecting means. Clock and timing signals And clock timing generating means for generating a television receiver, characterized by comprising a Y / C separation means for separating the luminance signal and the color signal from the output video signal of said second selecting means. 4. A thinning-out means for thinning out an output video signal of the A / D converting means when a frequency of a clock signal generated by the clock timing generating means and an operating clock frequency of the equalizing means are different from each other. 4. The television receiver according to claim 1, further comprising: an interpolating unit that interpolates an output video signal of the equalizing unit.