JPH0623985B2 - Logic diagram automatic generation method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical diagram automatic generation, and more particularly to a logical partitioning method suitable for a logical diagram automatic generation of a large-scale logical device such as an ultra-large computer.

[Background of the Invention]

With the recent increase in the scale of logic devices and the increase in VLSI, automatic generation of logic diagrams has become an essential function.

Automatic logic diagram generation usually divides the entire logic into divided logics by logical division, determines the arrangement of each logical symbol in the divided logic by automatic arrangement for each divided logic, and determines the wiring between the logical symbols by automatic wiring. Has been realized in a way.

The conventional logic division method is, for example, "Automatic generation system of logic circuit diagram", Sugimoto et al., NEC technique, No.133,1.
980, “Logical circuit diagram input / output system”, Kuruyama et al., Information Processing, Design Automation Study Group materials 17-2, 1983, etc., but these logical division methods are prescribed logical diagram 1 page size. The easiness of seeing the strict logic diagram was not taken into consideration simply by logically dividing it into divisional logic that fits inside. For this reason, the logic diagram is difficult to see and is complicated due to the logical division, and there is a problem in handling efficiency.

[Object of the Invention]

An object of the present invention is to provide a logical partitioning method that is easy to see and handle a logical diagram, and to provide an excellent method for automatically generating a logical diagram based on this method.

[Outline of Invention]

In order to achieve the above object, the present invention pays attention to two points, that is, the minimum number of cutting nets and the maximum degree of guarantee of logical progress, as an index of visibility of a logic diagram. , The vertical logical division step and the division logic serial number management step are used to perform logical division, thereby satisfying the above two indexes.

Example of Invention

First, the concept of logical partitioning processing according to the present invention will be described with reference to FIG. The entire logic 100 is horizontally logically divided and logically divided so that the length of each generated divisional logic 101 in the Y direction is equal to or less than the maximum length in the Y direction of the logic diagram. After this processing, vertical logical division is performed for each division logic 101,
Logical division is performed so that the length of each generated division logic 102 in the X direction is equal to or less than the maximum length in the X direction of the logic diagram.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a flow chart showing the entire logical division processing according to the present invention. The logical division processing procedure will be sequentially described below based on the processing flow of FIG.

Step 200: (1) Level setting: Fan-in tracing is performed starting from the logical symbol on the most output side of the overall logic to determine the level of each logical symbol. (2) Level correction: Level correction is performed so that normal logic symbols and connection logic symbols do not coexist on the same level. Specifically, the level of the connection logical symbol is set to a value obtained by subtracting 1 from the level of the minimum value among the levels of the normal logical symbol at the fan-in destination, and the normal level having the same level as the newly set value is set. The level is corrected by a method of setting the level of the logical symbol to a value obtained by subtracting 1. (3) Initial setting of variables: p = p + 1, q when the number of generated division logics is p and the variable for controlling the progress of division processing is q
= P, and the divided logical belonging number G _i of each logical symbol of the overall logic is set to G _i = p. Here, the initial value of p is specified from the outside. By this designation, it becomes possible to continuously perform the division processing of a plurality of whole logics.

Step 201: When the lengths in the X and Y directions of the divided logic composed of logical symbols satisfying G _i = q are L _x and L _y , these are calculated based on the following equations.

Here, the N _l is the number of levels of the divided logical, L _xl, L _yl each X direction of the l-level logical symbol group, the length of the Y-direction, L _xli, L _yli each of the l level The lengths of the logical symbol S _{i in} the X direction and the Y direction are represented by L _ylt , and the total length of the l-th level logical symbol S _{i in} the Y direction is represented.
Further, ↓ x ↓ represents a value obtained by rounding down the decimal part of x, and ↑ x ↑ represents a value obtained by rounding up the decimal part of x. Incidentally, the normal logic symbol is L _xli, L _yli 1, the line connecting the symbols are _{L xli = 0, L yli =} 1, (4) expression of a second right side,
Item 3 represents the correction of the length for wiring. Figure 3 shows
An example of divisional logic is shown in which the first level is the connection logic symbol 301 and the second and third levels are the normal logic symbols 300. When the size of the division logic of this example is calculated using the equations (1) to (5), L _x = 6 and L _y = 7.

Step 202: The maximum lengths in the X and Y directions of the logic diagram are L respectively.
_xm, when the L _ym, to step 204, if _L y> _{L ym,}
Otherwise, proceed to step 203 respectively.

Step 203: Step 206 if L _x > L _xm
Otherwise, go to step 208.

Step 204: (1) Determination of starting point symbol: If the number of first-level logical symbols is 2 or more, all of them are set as starting point parent symbols. Otherwise, fan-in tracing is performed from the first-level logical symbol, a logical symbol having a fan-in number of 2 or more is found, and the logical symbol of the fan-in destination is set as the originator symbol. (2) Calculation of separation degree: The following processing is performed for each starting point symbol. If the starting symbol is the starting child symbol,
Temporarily disconnect the net that connects the logical symbols of the level. Next, perform fan-in tracing from the starting symbol, find the disconnection nets (untraced fan-out nets of each logical symbol traced during the fan-in trace), and temporarily disconnect these disconnecting nets for logical division. , The separation degree ρ _i is calculated based on the following equation.

Here, N _j represents the number of division logics generated by logical division, X _k represents the number of logic symbols in each division logic, and X _m represents the maximum value of X _k . (3) Logical division: When the pre-designated allowable degree of separation is ρ _m , the starting point symbol that minimizes ρ _j (if there are multiple starting point symbols that satisfy this condition, the number of cutting nets c among them is c _(j is the smallest), and if ρ _j ρ _m , all the relevant disconnecting nets are actually disconnected and logical division is performed. However, ρ _j
If> ρ _m , logical division is not performed.

An example of horizontal logical division will be described below assuming that ρ _m = 2.
FIG. 4 shows an example of the starting parent symbol, and FIG. 5 shows the separation degree calculation result of this example. In this example, the starting parent symbol 302 has _three logical symbols S ₁ , S ₂ , and S ₃ . Juan-in trace is performed from S ₁ as a starting point, and the traced logical symbol 303 and disconnection net 304 are found.
These are temporarily cut. At this time, c _j = 2, N _j = 3,
X _k (k = 1,2,3) = 14,2,3, X _m = 14 and therefore ρ _j = 32.9. Similarly, S
It is possible to calculate ρ _j when starting from ₂ and S ₃ . In this example, ρ _j when S ₃ is the starting point is 1.
Since 4 is smaller than ρ _{m, the} cutting net when S ₃ is the starting point is actually cut and logical division is performed. Sixth
The figure shows an example of the starter symbol, and FIG. 7 shows the separation degree calculation result of this example. In this example, the originator symbol 305 has _three logical symbols S ₁ , S ₂ , and S ₃ . First temporarily disconnect the fan-out the net 306 of the S _1, performs Fuan'in trace starting from the S _1, find the the cutting the net 304 logical symbol 303 was Tadotsu (not present in the case of S _1), these Temporarily cut. At this time, c _j = 1, N _j = 2, X _k (k = 1, 2) = 9,
7, X _m = 9 and therefore ρ _j = 1.3. Similarly, it is possible to calculate ρ _j when starting from S ₂ and S ₃ . In this example, ρ _j when S ₁ is the starting point is 1.3 and smaller than ρ _m , so the disconnecting net when S ₁ is the starting point is actually cut and logical division is performed. Further, FIG. 8 shows an example of the starter symbol. In this example, there are nine logical symbols S ₁ , ... S _{9 as} the originator symbols 305. In this example, the same result is obtained regardless of which originator symbol is used as the origin, and c _j =
1, N _j = 2, X _k (k = 1,2) = 1,9, X _m = 9
And therefore ρ _j = 9. Since this is larger than ρ _m , no logical partitioning can be done.

Step 205: If horizontal logical division has been carried out, proceed to Step 207, otherwise proceed to Step 206.

Step 206: (1) Calculation of equivalent length each level: logic symbols of the l level is calculated on the basis of equivalent length L _Exlg the case of the normal logic symbols, the equivalent length L _Exlw the case of the line connecting symbols in the following equation .

here, Indicates a value obtained by sequentially selecting b from a _i having the maximum value and adding them. N _exl represents the converted level number of the 1st-level normal logical symbols, and X _wl represents the number of the 1st-level connected logical symbols. (2) Calculation of the converted length of the divided logic: Calculation of the converted length of the divided logic: The converted length L _ex of the divided logic is calculated based on the following formula.

Here, either L _cxlg or L _cxlw is valid for the l-th level, and N _cxl is valid only for the level of the normal logical symbol. The value of the valid one is 0. (3) Calculation of the number of divisions: The separation logical number m is calculated based on the following equation.

(4) Calculation of total fan-out: The total fan-out total of the l-th level logical symbol d _l is calculated based on the following equation.

Here, f _li represents the fan-out number of the l-th level logical symbol. (5) Intra-level logical partitioning: m levels that satisfy the following two partitioning constraint conditions are selected in order from d _l having the smallest value, and the logical partitioning is performed by actually cutting all of those fan-out nets. (a) When the (l-1) th level is the level of the connection logic symbol, d ₁ cannot be cut.
(ii) Each division logic generated by m fanout net cuts must fit within one page of the logic diagram.
(6) Logical division within the level: The logical diagram does not fit on one page,
Partitioning logic in which logical partitioning between levels is impossible is performed by intra-level logical partitioning. First, a level for logical division within a level is obtained. This can be obtained by the minimum value of N _c that satisfies the following equation.

Next, the conversion length r ₁ in which the logical symbol can be arranged within the N _c-th level is calculated based on the following equation.

Next, the converted length in which the logical symbol can be arranged within the N _c-th level is obtained. This can be obtained by the maximum value of r ₂ that satisfies the following equation.

Here, MaxL _xlj is the maximum value of the length in the X direction of the normal logical symbols in each group when the normal logical symbols at the N _c-th level are grouped in units that can be arranged in the Y direction on the logical diagram page 1. Represents Further, x _w is the (N _{c c)} which becomes the fan-out destination of the normal logic symbol selected by the setting of r _2.
-1) Represents the number of level connection logical symbols. At this time, when the (N _c -1) th level is a normal logical symbol, the fan-out net of the selected normal logical symbol and the fan-in nets of the remaining normal logical symbols are all cut off for logical division. Further, when the (N _c -1) th level is the level of the connection logical symbol, for each fanout net of the selected normal logic symbol, the fanout destination is the connection logical symbol and more than half of the connection logical symbol. If the fan-in source is included in the selected normal logic symbol, all the fan-out nets of the connected logic symbol are disconnected. Otherwise, disconnect the fanout net. At the same time, performs a logical division disconnects all Fuan'in-the net remaining normal logic symbols of the N _c levels.

_{L xm = 9, L ym =} 5, L xli = L yli = 1 assuming below describing the vertical logical partition example. FIG. 9 shows an example of logical division between levels. In this example, L _cx = 15, m = 1
Next, in ascending order of _{d l,} the second level _(d l = 2),
The logical division will be attempted in the order of the third level (d ₁ = 3) and the fourth level (d ₁ = 4). At this time, the disconnection of the fanout net of each of the second and third levels is m.
Since = 1 is not satisfied, a logical division will be performed at the disconnection line 307 in order to disconnect the fourth level fan-out net. FIG. 10 shows an example of intra-level logical division when connection logical symbols are not involved. In this example, L _cx = 15 and m = 1, and it is impossible to perform the inter-level logical division satisfying m = 1, so the intra-level logical division is performed. At this time, N _c = 3, r ₁ = 4, r ₂
= 2, and the logical division is performed at the cutting line 308.

Further, FIG. 11 shows an example of the intra-level logical division when the connected logical symbols are related. In this example, L _cx =
16, m = 1, and in-level logical division is similarly performed. At this time, N _c = 3, r ₁ = 4, r ₂ = 1 and the logical division is performed at the cutting line 309.

Step 207: Update G _i of the logical symbol S ₁ satisfying G _i > q based on the following equation.

G _i = G _i + N _d -1 (17) Here, N _d represents the number of generated divisional logics. Next, N _d pieces of divided updating G _i of each logic symbol S _i in the logic, the logic symbols of the left divided in logic (q + N d _-1) in the range up to cutting the net or cutting line from q _{G i} of S _i is performed so as to be smaller than those of the _{G i} to the right. Also, p is updated based on the following equation.

p = p + N _d -1 (18) Step 208: q = q + 1. If qp, the process proceeds to step 209, and if q> p, all the logical division processing ends.

Step 209: Take out the division logic composed of logic symbols satisfying G _i = q.

The logical partitioning process can be easily realized on one computer. Alternatively, it is also possible to allocate one computer to each of the processing steps of horizontal logical division and vertical logical division and the remaining processing steps.

According to this embodiment, in particular, the number of disconnection nets is minimized and the degree of guarantee of logical progress is maximized, and the divided logical diagrams are easy to see and easy to handle. Logical division is possible.

〔The invention's effect〕

As described above in detail, according to the present invention, the visibility of the logic diagram can be improved from the two viewpoints of the minimum number of disconnection nets and the guarantee of the progress of the logic. Effective in improving work efficiency.

[Brief description of drawings]

FIG. 1 is a general explanatory view of the logical partitioning process, FIG. 2 is a flow chart of the logical partitioning process according to the present invention, and FIG. 3 is an explanatory diagram showing an example of calculating the size of the partitioning logic, 4, 6, 8 FIG. 5 is an explanatory view showing an example of horizontal logical division according to the present invention.
FIG. 9 is an explanatory diagram showing an example of calculating the degree of separation according to the present invention,
10 and 11 are explanatory views showing an example of vertical logical division according to the present invention. 100 ... Whole logic, 101, 102 ... Division logic, 200
... 209 ... Logical division processing step, 300 ... Normal logical symbol, 301 ... Connection logical symbol, 302 ... Origin parent symbol, 303 ... Logical symbol traced by fan-in trace from origin symbol, 304 ... Disconnection net, 30
5 ... Originator symbol, 306 ... Originator symbol fanout net, 307-309 ... Cutting line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yasushi Ozawa, 6-81 Onoue-cho, Naka-ku, Yokohama-shi, Kanagawa Hitachi Software Engineering Co., Ltd. (72) Inventor Takashige Kubo 1099, Ozen-ji, Aso-ku, Kawasaki-shi, Kanagawa Ceremony company Hitachi Systems Development Laboratory

Claims (2)

[Claims] 1. A logic diagram generation method for generating a corresponding logic diagram from a network in which logic symbols are connected to each other, by tracing the network from an output side of a signal toward an input side thereof, Detecting fan-out nets connected to symbols that do not include a trace route on the network as disconnection nets, and using the number of the disconnection nets as an index for each signal propagation route A first step of dividing the network, a second step of dividing the network according to the number of logical stages of the logical symbols counted in the order of signal propagation using the number of the disconnected nets as an index, and a predetermined logical diagram size. Sub that fits
And a step of repeating the first or second division step until a network is obtained. 2. The method according to claim 1, further comprising the step of assigning a serial number according to an order in which a signal propagates to each of the sub-networks generated by the first or second division step. A method for automatically generating a logical diagram described in the section.