JPH06236319A - Method and apparatus for execution, by computer, of procedure of different word size - Google Patents

Abstract

PURPOSE: To provide a method and device for allowing a 64-bit device to operate a 32-bit software. CONSTITUTION: This method and device is constituted of the process of placing display indicating the word size of a procedure in at least one of the number of the registers of a processor, the process of supplying a save area including at least one part of the save area of the procedure of the smallest word size in the same address for a memory for the register filing of each word size, the process of indicating the word size of the procedure at the part of the save area with the same address and place display held by at least one of the register of the processor, and the process of re-investigating display at the part of the save area with the same address each time of generating saving operation for deciding the word size of a procedure to be restored.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to computer systems, and more particularly from 32 bits to 64 bits.
A method and apparatus for extending a computer architecture to bits.

[0002]

BACKGROUND OF THE INVENTION Computers have improved in speed and power, but there is still a demand for more addressable memory. The size of the address directly controls the size of the addressed memory. Each additional bit of the address doubles the addressable memory. A system using a 64-bit address can supply twice as many addresses as a system using a 32-bit address can supply. Therefore, researchers are now developing computer systems based on 64-bit architectures. On the other hand, there are also very powerful computers that use 32-bit addresses. There are many very useful pieces of software for such systems. Many companies invest more in software than they invest in hardware. These 32-bit systems may be able to handle more problems if there is a simple way to easily address more addresses. The only valid way to get more memory is with more (64
The idea of designing a system with (bit) addresses would abandon all of the effort put into 32-bit systems and software, which would be ridiculous and economical. It is a disaster. Therefore, new computer systems based on new memory sizes are prioritized by the requirement to be able to use old programs for new architectures. The first question in designing such a system is how to change the memory address size to allow older programs to be used on the new architecture.

There are two different strategies to solve this problem and allow the new system to work with both old and new programs. One way is to have two different architectures on the same machine that handle programs based on different memory sizes and have one of them chosen. In this case, the machine will implement two different sets of instructions. One problem with this solution is that two independent architectures are permanently needed for each new machine. That is, manufacturers must continue to make systems with both 32-bit and 64-bit architectures as long as 32-bit programs are used. There is another problem. That is, because old and new procedures operate at different locations in the system, they cannot be easily communicated. Digital Equipment Company
mpany, DEC) adopted this method when the computer was changed from the PDP11 series to the VAX series. DEC prepared a new VAX computer with microcode that could operate with both PDP11 and VAX instruction sets, and installed a mode switch on the machine to select between the two instruction sets.

The second solution is to design a new system where the same hardware can process both old and new programs using the same circuitry. This is the more preferred solution. However, the prior art attempts to address this problem have failed to achieve the purpose of eliminating special hardware destined for different architectures. For example, Intel followed this method in the design and improvement of its 80x86 line of computers. Intel continued the memory handling hardware mechanism of programs based on the old architecture, adding additional memory handling hardware for programs based on the new architecture. The instructions applicable to the old program are a subset of the total set of instructions available to the new machine. This solution allows you to use both old and new software on the same processor,
There is no easy way to use the old and new processes at the same time. This method requires the inclusion of additional memory processing hardware with more advanced steps that can disrupt more advanced architectures. For example, modern Intel processes cannot handle larger address spaces without the memory mapping hardware provided by older machines.

Thus, there are at least two solutions to the problem. However, each method cannot solve the problem in such a way that the new system can easily run old and new programs using the new address space.
Both required a huge amount of new hardware, and the old software had to be rewritten to match the new hardware.

One difficult problem associated with providing such a system is that older systems have register files that store the contents of their registers in memory during certain operations and their contents. The cause is the method of restoring. The new system, which has twice the memory address size of the old system, must use a different space to store the information than the old system, so the system handles the information correctly for programs of both sizes. I have to find some way to do it.

[0007]

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for a computer system in which a program having a 32-bit word size and a new program having a 64-bit word size exist and operate. It is to be. Another object of the present invention is to have an existing 32-bit program without increasing hardware, with both a program having a 32-bit word size and a new program having a 64-bit word size. It is an object of the present invention to provide a method and apparatus by which a computer system can store from and restore from a register file without requiring a software transformation. Still another object of the present invention is 32
It is an object of the present invention to provide a method and apparatus for bringing a computer system into a saved and restored state in response to the presence of traps for both programs having a bit word size and new programs having a 64-bit word size.

[0008]

SUMMARY OF THE INVENTION The above and other objects are for placing an indication in the at least one of the number of registers of a processor indicating the word size of a procedure, and for each word size register file. In memory, word
The process of supplying a save area containing at least one part of the save area of the procedure with the smallest size at the same address, and the word size of the procedure in the part of the save area having the same address whenever a save operation occurs. The process of placing the display held in at least one of the processor's registers, and the save area having the same address each time the save operation occurs to determine the word size in the restoration procedure. And a method of causing a computer to perform different word size procedures on a processor having a register designed to perform the largest word size procedure with.

The above and other objects and features of the invention will be better understood by the embodiments described in detail with reference to the following drawings.

[0010]

【Example】

Caveats and Terminology In the detailed description which follows, there are terminology for algorithms and symbols that describe the operation of computer memory data bits. The display and description of these algorithms is a means commonly used by those skilled in the data processing arts to convey the substance of their work to others. An algorithm is here or generally considered to be a consistent sequence of processes leading to a desired result.
The process requires physical manipulations of physical quantities. The physical quantity need not necessarily be stored, transmitted, combined, compared, or otherwise manipulated to take the form of an electrical or magnetic signal. Such signals may be bits, values, elements, because they are commonly used.
It has proven convenient to refer to it as a symbol, letter, period, number, etc. However, it should be noted that those terms and their synonyms correspond to the appropriate physical quantity and that they are merely labels applied to that quantity. Further performed operations may be expressed in terms related to operations performed by an operator, such as addition and comparison. In many cases, such operator intervention is not necessary or preferred for the operations described to form the invention. An operation is a machine action. Useful machines for practicing the invention are common digital computers and the like. One should keep in mind the distinction between the method of operating a computer and the method of computation itself.
The present invention relates to an apparatus and method for operating a computer to process electrical or other (eg mechanical, chemical) physical signals in order to generate these physical signals.

The problem of changing from a system that handles 32-bit addresses to a system that handles 64-bit addresses seems simple by simply changing the size of the registers. However, it is actually complicated because the hardware and software already exist. 3 reasons for this complexity
2-bit SPARC architecture and its 32-bit
It may be understood with reference to FIG. 1 which illustrates a register file using a 64-bit architecture designed to replace the architecture. SPAR
The machine using C is Sun Microsystems, Inc. of Mountain View, California.
c.) designed, manufactured and sold. Shown on the left are 16 individual registers that can store 32 bits of binary information represented as zeros and ones. The bit positions for each register are shown above the 32-bit register file. In the SPARC format, it is customary that the 7th register from the bottom be the stack pointer, and the stack pointer contains the stack address in which a part of the register file is stored in memory at the time of the interrupt.

The 64-bit register file shown on the right is similarly arranged. Binary information 6
It has 16 individual registers that can hold 4 bits. The bit positions for that register are shown above the 64-bit file. The words stored in the 64-bit registers are matched with respect to the significant words used in the 32-bit SPARC architecture.

Those skilled in the art will generally appreciate that the data contained in a 32-bit register does not affect the result in a 64-bit
It will be appreciated that it can be placed in a register and used. This occurs because many architectures generally use a two's complement architecture that overflows to the left. And the 32 bits used for an instruction in a 32-bit architecture are certainly placed in the register space provided in the 64-bit architecture.

However, when executing software in many architectures, switching from one procedure to another or from one program to another is often done. Whenever the processor does not have enough registers to process a new procedure, at least some of the contents of the register must be saved so that the space it occupies is used by the new procedure. Whenever a program runs and the system has to stop a particular procedure and move to another procedure, the state of the current procedure (information held in the associated register file and used by that procedure) is It needs to be evacuated for use in returning to the procedure. The register must be restored for the new procedure, the new procedure is executed, the state from the old procedure is retrieved and placed in the register, and the old procedure is restarted. This is true of many architectures, regardless of what format they are run in.

Unlike many architectures, SPARC
The architecture is based on an integer processor with many registers.
You have a register file that contains windows. Each register window contains 16 registers, 8 of which are called LOCAL registers and the remaining 8 are called IN registers. There is always at least two register windows when implementing the SPARC architecture. The IN register of one register window functions as the OUT register of the immediately preceding window, as the register windows are considered to form a large ring. When a program changes from one procedure to the next, it switches from one window to the next window without saving the memory of the remaining procedure registers and restoring the procedure registers from memory. , The processor performs many steps. This speeds up the operation of the processor.

However, SPARC processors have a limited number of register windows. When the limit is reached, the register in the next window of the ring saves the memory. To do this, the SPARC architecture has a window pointer. If the register file is outside the register window and the window pointer indicates that a new window is requested, an overflow trap occurs,
Instructs the contents of the next register window to be saved to memory. When the saved procedure is executed again, the contents of the register are restored from the memory.
Similarly, when a procedure that has been saved is restored to a register window, the register window contains the procedure that was saved before the restored procedure was placed in the window's register. To accomplish this, a window pointer is used and an underflow trap is generated. So the general architecture and SPARC
In both architectures, it is time to save the register file to memory and restore it.

A 32-bit SPAR to save the state of the procedure in response to an overflow or underflow.
The C architecture machine takes 32 bits from each of the integer processor's current register windows and stores (in a stack) information in a 32-bit save space in memory. Let the hardware and program do this. The system uses the address stored in the stack pointer register and places the information stored at the address in memory starting at the stack pointer address of the register in the register file. The hardware and software are combined to create a specific 32-bit save space for storing register states for trap occurrences. This is a common method based on 32-bit architecture operation.

The 32-bit save space of such a SPARC machine is shown in FIG. As shown, the save space is 16 32 bytes starting from the stack pointer address.
Contains a bit word. It should be noted that there is additional space above the register file, storage area of the save space for other purposes. It should also be noted that the address held in the stack pointer register of the register file shown in FIG. 1 is stored in the seventh word space of the save space of the memory. When the procedure restarts, the data in the save area will be returned to the register file for use by the processor.

Because it operates on a 32-bit procedure, the architecture of the new system must follow the conventions used in its code. That is, the new system must be able to save the 32-bit information in the 32-bit save area as the old architecture did from the old procedure held in the register file. You must retrieve that information and replace it properly in the register file.

The memory save space provided for the 32-bit procedure is not designed to handle 64-bit words. So the system needs to store a long word somewhere. Some arrangements can be shown for placing the 64-bit registers used in the new architecture. For example, it is possible to divide a 64-bit word into halves, and place the half including the high-order bits on the half of the low-order bits of the word space that is adjacent to the save space starting with the stack pointer. However, when searching for data stored by the system, the 32-bit format and
It may be in a different position in the 4-bit format. If the system expects 32-bit data to retrieve the data and it is 64-bit data (and vice versa), the system cannot operate properly.

Even with the arrangement providing enough space to store a 64-bit word, the system must determine whether the information is 64-bit information or 32-bit information in order to operate properly. It is clear that it must be. And even if the information is stored correctly, the system must know how to restore it when needed.

This causes a number of problems. At first,
How does the system know if the information in the register file is 32-bit information or 64-bit information?
Second, what the bits mean, even if the system knows that the information is in the proper format. For example,
If the procedure is a 32-bit procedure then the upper bits held in the register are meaningless, but if it is a 64-bit procedure it is the necessary information. Machine is 6 in the register
Restoring 4 bits and using meaningless bits in a 32-bit procedure makes the procedure extremely difficult.

This problem is difficult if the registers and storage are fixed in hardware. However, if the registers and save space are written in software, the problem becomes more serious. For example, a specific system (SPARC
The conventions used to define behavior (such as architecture) regulate the storage for programs and procedures running on that particular system. Each procedure thus assembles the register stack. It builds a stack pointer that points to a register / save area. The positions of the register save area and stack pointer do not change, and old programs do not run. Since the old procedure has a defined layout, all old procedures running on a 32-bit machine must be modified to function properly and they must know what to do with that information.
Correctly adjusting (translating) old programs is completely impossible. Therefore, when converting to a system that includes a 64-bit architecture, the software of the new system must be created so that both old and new programs can run without modification.

The present invention provides a method for storing and restoring both 32-bit and 64-bit information without substantially increasing the hardware and without requiring modification of existing 32-bit software. Solve a problem. The present invention utilizes a procedure level indication to indicate whether the procedure is a 32 bit procedure or a 64 bit procedure. To accomplish this, a stack pointer is used to store the display. This is known as the position for display. This is because the system has to use the stack pointer to find the address of the save space. On a trap requesting a register file save, the display examines to determine if the state is stored in 32-bit save space or 64-bit save space. In this way, the save space for the old procedure uses the same area of memory as is used by the software of the old system. Additional space is provided to store 64-bit procedure registers.

FIG. 1 shows how the above can be realized in a system using the SPARC architecture. As shown, the 64-bit register contains the value of the 32-bit register in the low order bits. Since each 32-bit procedure used in the SPARC architecture is contained in the stack pointer register, the stack pointer indicating the address of the memory at which this procedure is recorded is stored. The Stack Pointer Register always contains this stack address. Bit 63 of the stack pointer to indicate whether the particular procedure word held in the register is a 32 or 64 bit word.
(Most significant bit) is used. A zero is placed in this bit position if the procedure is a 32-bit procedure, and a 1 is placed in a 64-bit procedure. In the SPARC architecture, a trap handler procedure (ie, hardware) is included when an overflow trap indicates that the register of the procedure being executed is stored. Whether done in hardware or software, the trap handler looks at this bit in the stack pointer and acts on it to store the register according to the particular procedure type.

The use of this bit is more important than the use of other bits. The stack pointer contains the address where the save area is found. Since this address is manipulated mathematically in addressing, the use of the most significant bit causes the stack pointer address to add or subtract without affecting the type of procedure held in bit 63. Since bit 63 is the most significant bit, it does not affect the low level addition or subtraction performed by addressing with the stack pointer.

Since the SPARC architecture and most other architectures utilize two's complement arithmetic, the low order bits of the operation result are independent of the high order bits of the operands. This is done with the address of the stack pointer, whether the address is a 32-bit code or a 64-bit code.

The arrangement described above allows the system to know the format of the data used by the procedure when a store operation is required. In response to this indication, information is placed in the registers for the 32-bit procedure of the save space shown in FIG. However, as mentioned above, this space is not organized for register information in 64-bit procedures. Therefore, the 64-bit function or procedure defines a new save area. This save area is shown in FIG. This space starts at the same stack pointer address and pre-occupies the same register space, such as a 32-bit area. However, the information stored in this space is the lower 32 bits of the stack pointer address, leaving the other register storage locations empty. Starting at the first position above the 32-bit save area, a completely new 64-bit save area is defined. In the embodiment of the invention used in SPARC, the data from each register is stored in two 32-bit words that are adjacent to each other with the lower bits below the upper bits. The entire 32-bit word space, ie each 32 bits, can store a register file for a 64-bit procedure. It should be noted that the stack pointer is stored in this 64-bit save area again in a non-deformed form. The reason for this will become clear in the description.

The indication is 32 to indicate whether the stored procedure is a 64-bit procedure or a 32-bit procedure at decompression.
It is moved to the lower 32 bits so that only the bit save area is searched. That bit tells the machine that only the lower 32 bits of the state in the 32-bit procedure is used when restored or that the 64 bits of the state in the 64-bit procedure is used when restored.

As mentioned above, the indication placed in the stack pointer register o6 is sufficient to inform the system whether the procedure performed in the register file is a 32-bit procedure or a 64-bit procedure. . However, the state stored in the save area must be restored in order to reuse it. There may be several ways to determine if the system is 32 bit or 64 bit when searching the save area. One of the requirements of the new design is that the 32-bit save area format is not changed, so retrieving the information in bit 63 of the stack pointer for a 32-bit procedure makes this bit It will not inform you because it is not in the save area of the 32-bit procedure.

There are several ways to determine the type of procedure from the lower 32 bits of the stack pointer. Fortunately for SPARC architectures, the stack pointer address values are aligned on 4-byte boundaries, as are other architectures. The stack pointer register holds an address containing zero as the least significant bit. Use this bit to record the format indication stored in the upper bits of the Stack Pointer Register, allowing the indication to be displayed when the register state is stored in both 32-bit and 64-bit areas of memory. It can be transferred to the 32-bit save area. Therefore, when the state of the register file is stored, the state of the bit at the 63 bit position is moved to the least significant bit. In this way, only the stack pointer in the 32-bit save area needs to be searched.

The underflow trap is used to restore the save area of memory. The overflow trap is simply a stack trap to determine if the 32-bit or 64-bit procedure is stored in the save area.
Only search the least significant bit of the pointer. This tells the system what kind of procedure is currently being used. In this embodiment, zero is used to represent the 32-bit procedure. If the 32 bit procedure already used has not changed and a zero is normally found in the least significant bit, this remains in the save area with the 32 bit procedure unchanged. In contrast, the least significant bit 1 is used to indicate a 64-bit procedure. 64
Once the low-order 32-bit copy of the bit stack pointer (actually only the least significant bit is needed) is stored in the normal location for the 32-bit stack pointer, once the 64-bit procedure is detected by the trap. The 64-bit procedure then responds to the same underflow trap without modification to the procedure, apart from the response to restore from a different storage location.

Since the stack pointer information must be used by the procedure, if the procedure is 64 bits, the system will register the stack pointer of the upper region of the first condition where the least significant bit position is one. Leave it intact so that you don't lose time when files are restored. Even if the least significant bit of the stack pointer of the 32-bit save area supplies the same information while the register file is stored in the save area, as shown in FIG. 3, it is a 64-bit procedure. Bit position 6 to indicate
1 of 3 remains.

One of the problems of using the same 64-bit registers for both 32-bit and 64-bit procedures is that a register file performing a 32-bit procedure will have the upper bits unrelated to the procedure. It may be included. Unfortunately in some cases these bits affect the outcome of the procedure being performed. For example, if a register contains an address used in a load or store operation for a 32-bit procedure and its high order bits are used, they will generate the wrong address. Therefore these bits must be masked in some way. In this embodiment, a mask register is used to store information about the particular bit of the address to be used. When data is loaded and stored using the address held in the register file, its mask register forces the state of the upper bits and prevents the information from being invalidated. Such a mask
For details of the register, refer to "MASK REGISTER FOR COMPUTER PROCES
SOR) '' filed on the same date and assigned to the applicant by Powell et al.
No.

FIG. 4 is an iterative representation of the steps used to carry out the method of the present invention. While the invention has been described in terms set forth in the examples, it will be apparent to those skilled in the art that various changes can be made without departing from the spirit and scope of the invention. Therefore, the present invention should be limited only by the terms of the appended claims.

[Brief description of drawings]

1 is a register file used in a 64-bit architecture designed to replace the register file used in a 32-bit SPARC architecture and a 32-bit architecture.

FIG. 2 is a diagram showing an area of memory used to save a register file in a 32-bit architecture.

FIG. 3 is a diagram showing an area of memory used for saving a register file in a 64-bit architecture.

FIG. 4 illustrates the process used to carry out this method.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Robert Kumelik United States 94086 California, Sunnyvale Chula Vista Terrace 1024 (72) Inventor Shin Con United States 94039 California, Mountain View Pioobox 391379 No house number (72) Inventor David Ditzel United States 94022 Los Altos Hills Page Mill Road, California 4010 (72) Inventor Edmond Kelly United States 95136 San Jose Rio Grande Drive 5277 California

Claims (2)

[Claims] 1. A process of placing an indication indicating a word size of a procedure in at least one of the number of registers of a processor, and in memory for each word size register file, the smallest word size of A process of supplying a save area including at least one part of the save area of the procedure at the same address, and instructing the word size of the procedure in the part of the save area having the same address whenever the save operation occurs Of placing the display held in at least one of the registers, and re-examining the display in the portion of the save area that has the same address each time a save operation occurs to determine the word size in the restored procedure. And a processor with registers designed to execute in the largest word size procedure with How to get a computer to perform a custom size procedure. 2. A means for placing an indication indicating the word size of the procedure in at least one of the number of registers in the processor, and the smallest word size in memory for each word size register file. A means for supplying a save area including at least one part of the save area of the procedure at the same address, and a processor for indicating the word size of the procedure in the part of the save area having the same address whenever the save operation occurs Means for placing the display held in at least one of the registers, and means for re-examining the display in the portion of the save area that has the same address each time a save operation occurs to determine the word size in the procedure to be restored. And a processor with registers designed to execute in the largest word size procedure with A device that causes a computer to perform a custom size procedure.