JPH06233281A - System for transmitting video encoding signal - Google Patents

Abstract

PURPOSE:To reduce transmission delay time without deteriorating transmission quality in a video encoding system where a video frame is encoded, transmitted and decoded at a reception side. CONSTITUTION:In the video transmission system cosisting of a video encoder, a transmission line 12 and a video decoder, time which is obtained by dividing one video frame time by the proportion of the sum of the storing capacitance of a sending transmission buffer memory 106 and transmission encoding quantity corresponding to one video frame time in the transmission line 12 to transmission encoding quantity per one video frame time in the video encoder is adopted as the upper limit value of one frame decoding time in the video decoder.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video coded signal transmission system for compressing and reducing the code amount of a code relating to video information when transmitting the video information.

[0002]

2. Description of the Related Art A video coding technique has a transmission code amount much smaller than the code amount when the video information is directly encoded by the PCM (pulse code modulation) technique in order to remove the redundancy of information contained in the video as much as possible. Enables efficient video communication by compressing to. Here, in order to eliminate the redundancy of the information to be transmitted, the spatial correlation and the temporal correlation of the video are used. FIG. 3 shows a typical example thereof and is a block diagram showing a configuration of a video transmission system using inter-frame correlation and spatial correlation.

In this figure, 1 is a differentiator, 2 is a DCT
(Discrete Cosine Transform) Unit, 3 Quantizer, 4 Variable Length Encoder, 5 Inverse Quantizer, 6 Inverse DCT Unit, 7 Adder, 8 Frame Memory, 9 Motion Estimator, Reference numeral 10 is a transmission buffer memory, 11 is a transmission interface, and these constitute a video encoding device.

Further, 13 is a transmission interface, 14 is a transmission buffer memory, 15 is a variable length decoder, 16 is an inverse quantizer, 17 is an inverse DCT section, 18 is an adder, and 19 is a frame memory. A video decoding device that receives and decodes transmission information from the video encoding device via the transmission path 12 is configured.

In the above configuration, the sequentially generated video frames are input to the differentiator 1 of the video encoding device as the transmission side device, and the frame information stored in the frame memory 8 is subtracted. Here, the frame memory 8 stores information corresponding to the frame that is one frame before the transmission process is completed. Therefore, the difference between the currently input frame and the frame that was previously transmitted from the differentiator 1 is changed. The inter-frame difference information corresponding to is obtained. This interframe difference information is subjected to discrete cosine transform by the DCT unit 2,
It is quantized by the quantizer 3. The information quantized by the quantizer 3 is converted into a variable-length code by the variable-length encoder 4 and output from the transmission buffer memory 10 to the transmission line 12 via the transmission interface 11.

The output information of the quantizer 3 is returned to the state before quantization by the inverse quantizer 5, and then the inverse DCT unit 6
Is returned to the inter-frame difference information. The adder 7 adds the frame information stored in the frame 8 and the inter-frame difference information obtained from the inverse DCT unit 6. The output information of the adder 7 is stored in the frame memory 8 as a frame for which the transmission processing has been completed this time. The motion evaluator 9 detects a motion vector of a video based on the frame stored in the frame memory 8 and the video frame arriving at the differentiator 1.
The motion vector thus obtained is used for motion compensation of frame information to be transmitted, and is transmitted to the receiving side device.

[0007]

The redundancy contained in the image to be transmitted differs depending on each frame, and the code amount forming one frame also differs from frame to frame. When such a frame is transmitted through the constant rate transmission line 12, a means for absorbing the variation in the code amount between frames is required. The transmission buffer memory 10 in FIG. 3 is provided in the video encoding device in order to absorb such a variation in code amount between frames on the transmission side. Further, since the sequentially generated video frames have different code amounts, the transmission time for transmitting all the codes in the frame is different for each video frame, and it is necessary to smooth this. Therefore, the transmission buffer memory 14 for reception is provided in the video decoding device as in the transmission side.

In the video coding device, the transmission buffer memories 10 and 14 overflow,
The code generation amount is controlled so as not to underflow. Here, if the buffer sizes of the transmission buffers 10 and 14 are sufficiently large, the generated code is transmitted and decoded without loss, while the code remains in the reception transmission buffer 14. Therefore, the delay time from encoding to completion of decoding becomes long. For this reason, in applications such as immediate conversation such as videophones and video conferences, it is not possible to set a transmission buffer memory of sufficient length, and the quality of video encoding / decoding must be reduced. There was a problem that there is. Further, depending on the control method of the transmission buffer memory 10, when the generated code amount becomes large, the video frame to be input next may be discarded.

The present invention is a video coding system for coding a video frame, transmitting the video frame, and decoding the video frame at the receiving side, which makes it possible to reduce the transmission delay time without deteriorating the transmission quality. The purpose is to provide.

[0010]

A video coded signal transmission system according to the present invention is a video composed of a video coding apparatus, a transmission line and a video decoding apparatus for compressing and reducing the code amount of digitized video information for transmission. In the transmission system, the sum of the transmission buffer memory amount of the video encoding device and the transmission code amount corresponding to one video frame time on the transmission path and 1
It is characterized in that a time obtained by dividing one video frame time by the ratio of the transmission code amount per video frame time is set as an upper limit value of one frame decoding time in the video decoding device.

[0011]

According to the above invention, the video information can be transmitted in a short transmission time without causing overflow and underflow of the code to be transmitted on the transmitting side and the receiving side.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a video transmission system to which a video coded signal transmission device according to an embodiment of the present invention is applied. In FIG. 1, 102 is a phase locked clock generator, 103 is an encoder operating clock, and 104 is an interframe prediction DC.
T coding unit, 105 is a variable length coding unit, and 106 is a transmission transmission buffer memory having a storage capacity of a value obtained by multiplying one video frame time (time length of one video frame) by the transmission speed of the transmission line 12. Yes, these constitute a video encoding device as a transmission side device.

Further, 107 is a phase-locked clock generator, 108 is a decoder operation clock, and 109 is a storage capacity which is a value obtained by multiplying the transmission rate by 3 video frame times (time length of 3 video frames). Transmission buffer memory, 110 variable length decoding unit, 111 inter-frame prediction D
The CT decoding unit 112 is a display frame memory having a storage capacity of 3 video frames. Reference numeral 12 is a fixed-speed transmission line similar to that in FIG.

In the video encoding device, the signal output from the transmission transmission buffer 106 to the transmission line 12 is used as an input of the phase lock generator 102 to generate an operation clock 103 synchronized with the clock of the transmission line. Using this clock, in the inter-frame prediction DCT encoding unit 104, the difference between each frame of the video and the frame processed immediately before each frame is obtained, and the difference is subjected to the discrete cosine transform. Further, each coefficient obtained by the discrete cosine transform is quantized. Each quantized coefficient is variable-length coded in the variable-length coding unit 105 by Huffman coding the number of zero-valued coefficients and the signal value of the non-zero coefficient. The variable length code obtained as a result is stored in the transmission transmission buffer memory 106, and FIFO (first in first out)
It is sent to the transmission line 12 under control. Here, the inter-frame prediction D is calculated according to the accumulated amount in the transmission transmission buffer memory 106.
The quantization characteristic of the CT coding unit is controlled. That is, when the storage amount approaches the capacity of the transmission transmission buffer memory 106, the generated code amount is reduced by increasing the probability that the quantization characteristic becomes a zero coefficient value, and the quantization is performed when the storage amount approaches 0. The amount of generated code is increased by making the characteristics finer. Here, the transmission buffer 106 in the video encoding device has a storage capacity corresponding to one video frame time, and therefore the maximum value of the generated code amount is the number of transmission bits corresponding to two video frame times. There is.

In the video decoding apparatus, the phase-locked clock generator 107 generates the operation clock 108 which is synchronized with the signal transmitted through the transmission line 12 and which has a frequency twice the clock of the video encoding apparatus. To do. Then, the decoding is started at the time when the codes for two frames are accumulated in the reception transmission buffer memory 109. Variable length decoding unit 11
At 0, in accordance with a request from the inter-frame prediction DCT decoding unit 111, the codes accumulated in the reception transmission buffer memory 109 are sequentially read out and are returned to the equal-length code in which the code length per code is constant. These equal-length codes are input to the inter-frame predictive DCT decoder 111, subjected to dequantization / inverse DCT at a speed twice as fast as the operation speed of the video encoding device, decoded into a video signal, and displayed in a display frame memory. It is stored in 112. Then, the display is started at the time when the video for two frames is accumulated in the display frame memory 112. The display frame memory 112 requests the variable length decoding unit 110 to read from the reception transmission buffer memory 106 when the frame memory area for one frame or more is empty.

Here, since the memory amount of the transmission transmission buffer memory 106 is 1/2 of the allowable generated code amount, the transmission transmission buffer memory amount is set for the next video frame when the maximum code amount occurs. It becomes the upper limit of the generated code amount.
As shown in FIG. 2, when a video frame i + 1 that generates a code amount corresponding to 0.5 video frame time continues after a video frame i that generates a code amount over 2 video frame times, the frame is stored in the transmission transmission buffer memory 106. i + 1, the idle time of frame i + 2 is deleted,
Only 3 video frame times are required to transmit 3 video frames. On the other hand, if the video decoding device operates at the same speed as the video encoding device, it takes 4 video frame times because it takes time to receive the code of the first video frame. Is 1 / k (where k = (maximum transmission time per video frame) / (1
Video frame time), and 2) in the above example, only 3 video frame times are required for decoding. In most frames, the generated code amount is less than or equal to one video frame time in terms of transmission rate. Therefore, a video frame that requires twice the transmission time cannot be immediately followed by a video frame that alleviates it. Also, if the video decoding device has some buffer memory function, the product band of decoding can be relaxed and resolved within a certain time. Therefore, if the video decoding apparatus is provided with a reception transmission buffer memory having a capacity of 3 video frames and decoding is started from the time when the code of 2 video frames is received, the code to be decoded on the decoding side will be lost. There is no need to repeat the same image. In addition, the delay time required for transmission is suppressed to 2 video frame times, and input video frames are not discarded in order to prevent overflow of the transmission / transmission buffer memory.

[0017]

As described above, since the transmission / transmission buffer memory overflow does not occur and the code to be decoded is not received in the video decoding device, the buffer underflow does not occur. The input video frame can be encoded, transmitted, and decoded, and the required transmission / reception buffer memory amount is small, so that the transmission delay time can be shortened.
As the generated code amount of each frame, at least the storage capacity of the encoder transmission buffer memory is secured,
The video quality can be guaranteed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video transmission system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing a configuration of a general video transmission system using inter-frame prediction.

[Explanation of symbols]

 12 transmission path 102 phase-locked clock generator 103 coding device operating clock 104 interframe prediction DCT coding unit 105 variable-length coding unit 106 transmission transmission buffer memory 107 phase-locked clock generator 108 decoding device operating clock generator 109 reception transmission Buffer memory 110 Variable length decoding unit 111 Inter-frame prediction DCT decoding unit 112 Display frame memory

Claims (1)

[Claims] 1. A video transmission system comprising a video encoding device, a transmission path, and a video decoding device for compressing and reducing the code amount of digitized video information for transmission, and a transmission buffer memory amount of the video encoding device and The time obtained by dividing one video frame time by the ratio of the sum of the transmission code amount corresponding to one video frame time in the transmission path and the transmission code amount per one video frame time is the one frame decoding time in the video decoding device. A video coded signal transmission method characterized by an upper limit value.