JPH06231098A - Control system for multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce both hardware and software amounts by monitoring the registers of a system storage device by each cluster at the time of power supplying, and connecting the cluster with the system storage device when the registers are turned on. CONSTITUTION:A front end processor(FEP) 20 and back end processors(BEP) 21 and 22 are connected with a system storage unit(SSU) 25, and a system storage coupled multiprocessor system(SCMP) is constituted. Also, service processors(SVP) 26-28 are respectively connected with the FEP 20 and the BEP 21 and 22, and the SSU 25 is equipped with a constitution control register(CFR) 30 and a connect mechanism register(CFX) 31. An automatic remote controller unit(ARC) 29 performs the power supply control of the FEP 20 and the BEP 21 and 22. At that time, the power supply of the SSU 25 is thrown in, the registers are turned on, and then the power supply of the cluster is thrown in so that the cluster can be connected with the SSU 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system control system, and more particularly to a system storage coupled multiprocessor system control system.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 8, a system storage coupled multi-processor having a front end processor (FEP) 10 and back end processors (BEP) 11 and 12 as a cluster connected to a system storage unit (SSU) 15 respectively. There is a processor system (SCMP). In the conventional SCMP, the local area network (LAN) 19 connects the FEP 10 and the service processors (SVP) 16, 17, 18 attached to the BEPs 11, 12 as a cluster, respectively. FEP1
0, BEP 11 and 12 may be different kinds of computers, power sources are independent of each other, and FEP 10 to SS
Power is supplied to U15.

[0003]

Conventionally, when the power of the SCMP is turned on, communication is performed between the SVPs 16 to 18 via the LAN 19 and the powers of the FEP 10 and the BEPs 11 and 12 are turned on in synchronization with the SVPs 16 to 18. I am raising.

When the SVPs 16 to 18 are connected by the LAN in this way, the hardware becomes large in scale, and
Heterogeneous computers FEP10, BEP11,1
2 is connected to the LAN 19 via the SVPs 16 to 18, the software becomes large-scale and the time required for communication becomes long.

The present invention has been made in view of the above points,
SEP of FEP and multiple BEPs connected to SSU
An object of the present invention is to provide a control method for a multiprocessor system that does not require communication between Ps and can reduce the amount of hardware and software for communication between SVPs.

[0006]

A control method for a multiprocessor system according to the present invention is a control method for a multiprocessor system in which a plurality of clusters, which are computer systems, share a system storage device, and registers are provided in the system storage device. After turning on the power of the system storage device, the register is turned on, and each cluster monitors the register of the system storage device at the time of turning on its power source and connects to the system storage device when the register is turned on.

Further, the cluster which is powered on generates an interrupt to the system storage device. Further, a bit indicating whether the storage data is valid or invalid is provided in the system storage device, and each cluster determines the storage data of the system storage device by referring to the bit.

Further, a flag is set in the system storage device when a serious failure occurs, and access to the system storage device is prohibited by setting the flag.

[0009]

According to the present invention, after the register is turned on by turning on the power of the system storage device, the power-on cluster is connected to the system storage device. Therefore, the system can be operated without communication between service processors (SVP). Each cluster in can be powered on.

Further, since the power-on cluster interrupts the system storage device, the overhead of the processor managing the system storage device is reduced.

Further, since the storage data is judged in each cluster from the bit indicating whether the data of the system storage device is valid or invalid, useless access of the system storage device is suppressed, and when a serious failure of the system storage device occurs. Access is banned and failure is prevented from spreading.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of SCMP according to the present invention. In the figure, FEP20 and BEP21, 22
Each of them is connected to the SSU 25 to form SCMP. SEP2 for FEP20 and BEP21,22 respectively
6 to 28 are attached respectively, and SVP 26 to 28 are L
Not connected by AN.

In the SSU 25, a configuration control register (CF
R) 30 and a connection mechanism register (CFX) 31 are provided.

The automatic remote controller unit (ARC) 29 includes FEP20 and BEP21,22.
The power supply is controlled and the power supply warning report is supplied to them.

FIG. 2 shows a block diagram of one embodiment of SCMP. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. S
Access to the memory unit 40 in the SU 25 is controlled by the memory control unit 41. SCMP in the memory control unit 41
A configuration control register (CFR) 30 for storing connection configuration information of the clusters in the above, and connection information of a cluster actually used among the clusters defined by the CFR 30 for high-speed switching such as hot standby. The connection control register (CFX) 31 and the cluster ready register (C which indicates that the cluster can be connected)
RR) 32.

The mover 42 controlled by the memory controller 41 is a FEP 20 and a BEP 21, 22.
Data to and from the interrupt control circuit (GS
The IGP) sends and receives interrupt requests and parameters to and from the FEPs 20, BEPs 21 and 22 to perform interrupt control.
In addition, the SCI interface 44 is FEP20, BEP
Connected to the SCI (Service Processor Control Interface) of each of 21, 22 and FEP 20, BEP
The contents of the registers in the memory control unit 41 are transferred at the time of remote scanning from each of 21 and 22.

The malfunction detection circuit 45 is a BEP
When an abnormal signal is supplied from each of 21 and 22, another BE
Notify P of which BEP is in an abnormal state.

Access to the memory unit (MSU) 50 of the BEP 21 is controlled by a memory control unit (MCU) 51. The MCU 51 has a scalar unit (SU) 52 which is a processor for performing a scalar operation and a vector unit (VU) 5 which is a processor for performing a vector operation.
3 is connected.

The MOVER 54 and GSIGP 55 controlled by the MCU 51 are connected to the MOVER 42 and GSIGP 43 of the SSU 25, respectively, to perform data transfer and interrupt. The SCI 56 is connected to the SCI interface 44 of the SSU 25 and also connected to the SVP 27, and transmits / receives control information to / from the SVP 27.
The system power supply controller (SPC) 57 controls the power supply of the BEP 21 and the SVP 27 according to the control of the ARC 29 connected via the terminal 58.

The configurations of FEP 20 and BEP 22 are the same as the above B.
Similar to EP21.

FIG. 3 is a block diagram of an essential part of the SCMP of the present invention, FIG. 4 is a flowchart of the power-on process executed by the SVP 26 of the FEP 20, and FIG. 5 is a power-on process executed by the SVP 27, 28 of the BEP 21, 22. A flow chart is shown.

In FIG. 4, in step S2, SVP2
6 performs power-on reset of FEP 20 and SSU 25. Next, in step S4, the configuration information stored in the SVP 26 is changed from the SCI of the FEP 20 to the SC of the SSU 25.
It is transferred to the I interface 44 and the above configuration information is CFR.
30 and CFX31 respectively.

The contents of the CFR 30 are fixed without being rewritten thereafter, and the contents of the CFX 31 are F.
It is rewritten by the software of EP20, and high-speed switching such as hot standby becomes possible.
It is not necessary to rewrite the contents of the CFR 30 using the LAN between the VPs 26 to 28, and the control is simplified. After this, clock tuning is executed in step S6, and step S8
Then, the CRR 32 is turned on, the SSU power ready (SPR) signal is turned on in step S9, and the process is ended.

Here, as shown in FIG. 6, the clock is generated by the clock phase generator 61 with the clock coming from the terminal 60 as a reference, and various clocks having phases corresponding to the phase setting value of the phase register 64 are generated. At 62, it is distributed to the terminals 63 _{1 to} 63 n and supplied to each part of the apparatus. Clock tuning is performed by loading the phase setting value in the phase register 64.

In FIG. 5, in step S10, SVP2
7 performs a power-on reset of BEP21. Next, in step S12, clock tuning is performed, and in step S14, the unit ready register (U
RR) 70 is turned on. After this, SCI of BEP21
Scan out the contents of CRR 32 from 56 through SCI interface 44 of SSU 25, and step S1
At 6, it is determined whether the CRR 32 is on. If CRR is on, S in the MCU 51 of BEP21 in step S18
The SU connection flag (SCF) 71 is turned on, and step S
At 20, the SSU is interrupted and the process ends. If CRR is off, the process is terminated without turning on the SCF 71.

Here, the CFR 30 and CFX 3 in the SSU 25 shown in FIG. 3 are executed by executing the processing of FIG.
1, the configuration information is set, and the AND circuit 72 generates a signal that is turned on only for the clasp (BEP) whose connection is designated by the configuration information, and then the MOVER 42, G
The signals are supplied to the SIGP 43 and the malfunction detection circuit 45, respectively, and also supplied to the BEPs 21 and 22. Also CR
R32 and SPR are turned on.

Next, when the processing of FIG. 5 is executed, BEP2
The URR 70 and SCF 71 in 1 are turned on. Since the SSU power ready signal coming from the terminal 73 is turned on and stored in the flip-flop 74, the output of the AND circuit 75 is turned on and supplied to the AND circuits 76 and 77.
The AND circuit 76 also turns on the positive side output because the URR 70 output is turned on. Both the positive and negative outputs of the AND circuit 76 are supplied to the AND circuit 78 of the SSU 25, and the ON outputs of the AND circuit 78 are MOVER 42, GSIGP 43,
It is supplied to the multiple function detection circuit 45, and these circuits are brought into an operating state by both ON outputs of the AND circuits 72 and 78.

When the AND circuit 72 output of the SSU 25, the AND circuit 75 output of the BEP 21, and the URR 70 are turned on, the AND circuit 77 turns on the MOVER 54 and GSI.
The GP 55 is put into operation. As a result, BEP21's MOVER54 and GSIGP55 and SSU25's MOV
Data transfer and interruption are possible between the ER 42 and GSIGP 43.

Thereafter, in step S20, the MSU5
The firmware in 0 is activated and the MCU 51 sets GSIG
An interrupt request is issued from P55 to GSIGP43 of SSU25. This interrupt is busy between GSIGP 55 and 43, and when the condition code CC = 2, waits for a predetermined time (for example, 1 msec).
When it becomes 0, it is retried, and when CC = 2 by bus parity machine check or the like, it is retried twice. This B
By interrupting the SSU 25 from the EP 21, the SSU 25 is notified that the BEP 21 is activated, and further, the GSIGP 43 of the SSU 25 notifies the FEP 20. This reduces the FEP 20 overhead without the FEP 20 having to repeatedly poll the SSU 25 to see if the BEPs 21, 22 have been powered on.

By the way, when an abnormal signal is output from the BEP 21 due to a malfunction of the BEP 21 or the like, the malfunction detection circuit 45 of the SSU 45 causes another BE from the terminal 80.
Notify P22 that BEP 21 has been disconnected.

In this way, L is set between the SVPs 26-28.
The SCMP can be powered on without performing communication using the AN.

After the SSU 25 is tuned to the clock, the cluster ready register (CRR) 22
Is turned on, and in BEP21, after clock tuning, it is determined whether or not CRR22 is turned on, and MOVER54, G
In order to make the SIGP 55 operable, noise such as clock tuning is generated between the MOVES 42 and 54 and the GSIG.
Since the data is not transferred between P43 and P55, malfunction can be prevented.

Here, the memory section 40 of the SSU 25 is provided with a data invalid (DI) bit 46 and a system damage (SD) bit 47. The DI bit 46 is set to 1 by the memory control unit 41 at the time of power-on reset of the SSU 25, and also set to 1 at the momentary power failure of the SSU 25, indicating that the data in the SSU 25 is not guaranteed. SD bit 47 is SSU25
It is reset to 0 by the memory control unit 41 at the power-on reset of 1 and is set to 1 when a serious failure occurs in the SSU 25.

The FEP 20 checks the DI bit via the SCI interface 44 in the IPL of the OS, judges that the data of the SSU 25 is invalid when it is 1, and the SSU 2
Writing valid data to 5 issues an instruction to reset DI bit 46 to 0. When a power failure occurs, the FEP 20 checks the value of the DI bit 46 from the SCI interface 44 according to the instruction, and the DI bit 46 is set to 1
When it is, it is judged that the data of SSU25 is invalid, and SS
When the U25 is accessed and the knot operation is performed a predetermined number of times, the SSU 25 determines that it cannot be used.

Upon receiving the power supply warning report from the ARC 29, the BEPs 21 and 22 check the value of the DI bit 46 from the SCI interface 44 by an instruction, judge that the data of the SSU 25 is invalid when the DI bit is 1, and access the SSU 25. Then, if the knot operation is performed a predetermined number of times, the SSU 25 determines that it cannot be used.

The SSU 25 includes FEP20 and BEP21,
When accessed from 22, when SD bit 47 is 1, the access is prohibited by setting MOVE 42 as a knot operation.

By thus providing the DI bit 46, useless access of the SSU 25 can be suppressed, and by providing the SD bit 47, the access of the SSU 25 can be prohibited and the failure can be prevented from expanding.

Next, the operation when a failure is detected in each cluster will be described. As shown in FIG. 7, a check stop detection circuit 71 is provided in the MCU 51 of the BEP 21, and when the check stop of the BEP 21 is detected, 1 is written in the check stop register (CSR) 72. The CSR 72 is reset to 0 at the power-on-recent time, and when 1 is written to the CSR 72, the NOR circuit 7
3 becomes 0.

MC which indicates the operating state of the BEP 21
The contents of the active state (AS) 74 in U51 are supplied to the interrupt controller 76. When the interrupt control unit 76 detects a failure such as a watchdog timer out from the contents of AS, it interrupts the SVP 27 through the SCI 56 and changes the status of AS74 to the result register 75 and S.
Notify via CI56. SVP27 is AS74 above
Issue a fault notification command from the state of
It is supplied to the decoder 77 through 56. Decoder 77
When this command is discriminated as a fault notification command, the decoder 7
7 starts a counter 78, and the counter 78 generates a signal of 1 only for a predetermined time and supplies it to the NOR circuit 73. The output of the NOR circuit 73 is supplied from the terminal 79 to the malfunction detection circuit 45 of the SSU 25 shown in FIG.
When the output is 0, the malfunction detection circuit 45 is BE
As a failure occurred in P21, another cluster BEP22
To notify.

In this way, the contents of the AS 74 are discriminated by the SVP 27, and the DEC 77 and the counter 78 are issued by the instruction of the SVP 27.
Since the abnormal signal is generated by the above, the circuit configuration in the MCU 51 is simplified, and the increase of external connection pins of each of the MCU 51 and the SCI 56 can be prevented.

[0041]

As described above, according to the control system of the multiprocessor system of the present invention, the FE connected to the SSU
There is no need to perform communication between SVPs of P and a plurality of BEPs, and the amount of hardware and software for communication between SPVs can be reduced, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of SCMP according to the present invention.

FIG. 2 is a block diagram of SCMP.

FIG. 3 is a block diagram of a main part of SCMP.

FIG. 4 is a flowchart of power-on processing.

FIG. 5 is a flowchart of power-on processing.

FIG. 6 is a diagram for explaining clock tuning.

FIG. 7 is a block diagram of a failure detection unit of BEP.

FIG. 8 is a block diagram of a conventional system.

[Explanation of symbols]

 20 FEP 21,22 BEP 25 SSU 26-28 SVP 29 ARC 30 CFR 31 CFX 32 CRR 40 Memory part 41 Memory control part 42,54 MOVER 43,55 GSIGP 44 SCI interface 50 MSU 51 MCU 52 SU 53SC 56 VU 57 VU

Claims (4)

[Claims] 1. In a control method of a multiprocessor system in which a plurality of clusters (21, 22) which are computer systems share a system storage device (25), a register (32) is provided in the system storage device (25), After turning on the power of the system storage device (25), the register (32) is turned on, and each cluster (21, 22) monitors the register (32) of the system storage device (25) at the time of turning on the power of the system storage device (25). A control system for a multiprocessor system, characterized in that when the register (32) is turned on, it is connected to the system memory device. 2. The multiprocessor system control system according to claim 1, wherein the powered-on cluster is a system storage device (25).
A control method for a multiprocessor system, which is characterized by generating an interrupt to the. 3. The multiprocessor system according to claim 1, wherein the system storage device (25) is provided with a bit (46) indicating whether the stored data is valid or invalid, and each cluster (21, 22) is A control method for a multiprocessor system, characterized in that the storage data of a system storage device (25) is determined by referring to the bit (46). 4. The control method for a multiprocessor system according to claim 3, wherein a flag (47) is set in the system storage device (25) when a serious failure occurs, and the flag (47).
A system for controlling a multiprocessor system, characterized in that access to the system storage device (25) is prohibited by setting the above.