JPH0622451A - Erroneous function preventive circuit for multi-output power supply load device - Google Patents

Erroneous function preventive circuit for multi-output power supply load device

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Publication number
JPH0622451A
JPH0622451A JP4177868A JP17786892A JPH0622451A JP H0622451 A JPH0622451 A JP H0622451A JP 4177868 A JP4177868 A JP 4177868A JP 17786892 A JP17786892 A JP 17786892A JP H0622451 A JPH0622451 A JP H0622451A
Authority
JP
Japan
Prior art keywords
power supply
load device
output
supply unit
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4177868A
Other languages
Japanese (ja)
Inventor
Toshio Innami
敏夫 印南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4177868A priority Critical patent/JPH0622451A/en
Publication of JPH0622451A publication Critical patent/JPH0622451A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent erroneous function of load device due to lag of output voltage falling time upon turn OFF of power under light load state. CONSTITUTION:A Zener diode D1 detects voltage and a transistor Q turns a relay RL ON/OFF. An erroneous function preventive circuit 4 for opening/ shorting the output depending on make/break of relay contact r1 is inserted between a power supply unit 3 and a load device control section 7 in order to control a sequence between the output voltages.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多出力電源の出力間の
シーケンス制御による負荷装置の誤動作防止に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to prevention of malfunction of a load device by sequence control between outputs of a multi-output power supply.

【0002】[0002]

【従来の技術】従来の電源ユニットの電源負荷装置誤動
作防止回路について図面を参照して説明する。
2. Description of the Related Art A conventional power supply load device malfunction prevention circuit for a power supply unit will be described with reference to the drawings.

【0003】図3は従来例の電源及び負荷装置制御回路
のブロック図、図4は図3の負荷装置制御部7の電源シ
ーケンスを示す図である。
FIG. 3 is a block diagram of a conventional power supply and load device control circuit, and FIG. 4 is a diagram showing a power supply sequence of the load device control section 7 of FIG.

【0004】図3において、従来例の電源及び負荷装置
制御回路は、交流電源1と、スイッチ2と、電源ユニッ
ト3と、制御IC5とRS232C6とを有する負荷装
置制御部7と、モデムと接続されたデータ分岐装置(以
下、DBUと称す)10と、端末装置12a,bとで構
成されている。
In FIG. 3, the conventional power supply and load device control circuit is connected to an AC power supply 1, a switch 2, a power supply unit 3, a load device control section 7 having a control IC 5 and an RS232C6, and a modem. And a data branching unit (hereinafter referred to as DBU) 10 and terminal units 12a and 12b.

【0005】ここで、電源ユニット3のOFF時の出力
電圧の立ち下り時間は、定格負荷状態の出力コンデンサ
C1,C2の放電時間によって規定されており、図3に
示すように、電源ユニット3と負荷装置制御部7とが直
接接続されており、スイッチ2により電源OFFする
と、電源ユニット3が停止し、電源ユニット出力コンデ
ンサC1,C2に残った電圧は負荷へ放電される。この
際、RS232C6を介してモデムと接続されたDBU
10により分岐されている端末装置12a,bの負荷が
軽負荷状態の場合は、出力コンデンサC1,C2の放電
に時間がかかり、図4に示すように、なだらかな立ち下
りとなる。
Here, the fall time of the output voltage when the power supply unit 3 is OFF is defined by the discharge time of the output capacitors C1 and C2 in the rated load state, and as shown in FIG. The load device controller 7 is directly connected to the power supply unit 3, and when the power is turned off by the switch 2, the power supply unit 3 is stopped and the voltage remaining in the power supply unit output capacitors C1 and C2 is discharged to the load. At this time, the DBU connected to the modem via RS232C6
When the load of the terminal devices 12a and 12b branched by 10 is in a light load state, it takes a long time to discharge the output capacitors C1 and C2, resulting in a gentle fall as shown in FIG.

【0006】[0006]

【発明が解決しようとする課題】上述した従来の電源ユ
ニットの電源負荷装置誤動作防止回路では、軽負荷時の
出力電圧の立ち下り時間は、規定されておらず、図3に
示すように、電源ユニット3において、+5V負荷が定
格負荷で+12V負荷が軽負荷の場合、+5Vは規定時
間内に立ち下るが、+12Vは負荷が軽いため、出力コ
ンデンサC2がなかなか放電されず、電圧が残ってしま
うため、+12V負荷であるRS232Cが、図4に示
すように、誤出力をDBU10へ送出し、接続された他
の端末装置が通信中の時、リトライが負荷となり、回線
異常となるという問題がある。
In the above-described conventional power supply load device malfunction prevention circuit for a power supply unit, the fall time of the output voltage at a light load is not specified, and as shown in FIG. In the unit 3, when the + 5V load is the rated load and the + 12V load is a light load, + 5V falls within the specified time, but + 12V is a light load, so the output capacitor C2 is not easily discharged and the voltage remains. , RS12C of + 12V load sends an erroneous output to the DBU 10 as shown in FIG. 4, and when another connected terminal device is communicating, there is a problem that the retry becomes a load and the line becomes abnormal.

【0007】本発明の目的は、シーケンス制御機能を備
えた誤動作防止回路を電源ユニットと負荷装置制御部に
挿入し、電源OFF時に制御系出力より他出力を早く立
ち下げることにより、上記の欠点を解消し、軽負荷状態
での電源OFFの際、出力電圧の立ち下り時間の遅延に
伴う負荷装置の誤動作を防止する多電源負荷装置誤動作
防止回路を提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks by inserting a malfunction prevention circuit having a sequence control function into a power supply unit and a load device control section, and causing other outputs to fall earlier than the control system output when the power is turned off. Another object of the present invention is to provide a multi-power supply load device malfunction prevention circuit that eliminates malfunctions of a load device due to delay of fall time of output voltage when power is turned off in a light load state.

【0008】[0008]

【課題を解決するための手段】本発明の多電源負荷装置
誤動作防止回路は、多出力電源を有する電源ユニット
と、電源ユニットより電源電圧が供給され接続されてい
る負荷装置を制御する負荷装置制御部との間に、電源ユ
ニットの出力電圧間のシーケンス制御を行う手段を備え
ている。
A multiple power supply load device malfunction prevention circuit of the present invention is a load device control for controlling a power supply unit having multiple output power supplies and a load device to which a power supply voltage is supplied from the power supply unit and which is connected. And a means for performing sequence control between the output voltages of the power supply unit.

【0009】[0009]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0010】図1は本発明の一実施例の多電源負荷装置
誤動作防止回路を適用した電源及び負荷装置制御回路の
ブロック図、図2は図1の負荷装置制御部7の電源シー
ケンスを示す図である。
FIG. 1 is a block diagram of a power supply and load device control circuit to which a multiple power supply load device malfunction prevention circuit according to an embodiment of the present invention is applied, and FIG. 2 is a diagram showing a power supply sequence of a load device control section 7 of FIG. Is.

【0011】図1において、本実施例の多電源負荷装置
誤動作防止回路を適用した電源及び負荷装置制御回路
は、交流電源1と、スイッチ2と、電源ユニット3と、
制御回路9を有する誤動作防止回路4と、制御IC5と
RS232C6とを有する負荷装置制御部7と、DBU
10へのRS出力8とで構成されている。
In FIG. 1, a power supply and load device control circuit to which the multiple power supply load device malfunction prevention circuit of this embodiment is applied includes an AC power supply 1, a switch 2, a power supply unit 3, and
Malfunction prevention circuit 4 having control circuit 9, load device control section 7 having control IC 5 and RS232C6, and DBU
RS output 8 to 10.

【0012】ここで、交流電源1を入力し、DC+5
V,+12Vを出力する電源ユニット3の各出力端と負
荷装置制御部7の入力端の間に誤動作防止回路4を挿入
し、DC+5VとDC+12V出力にシーケンスを作
り、DC+5V立ち下り時、DC+12Vを速く立ち下
るようにし、DC+12V出力の負荷であるRS232
C6の誤出力を無くし、DBU10により接続される他
の端末装置(図示せず)の回線障害を防止する。
Here, the AC power source 1 is input and DC + 5
Insert the malfunction prevention circuit 4 between each output terminal of the power supply unit 3 that outputs V and + 12V and the input terminal of the load device control section 7 to create a sequence for the DC + 5V and DC + 12V outputs, and to make DC + 12V faster when DC + 5V falls. RS232 which is a load of DC + 12V output
The erroneous output of C6 is eliminated, and the line failure of another terminal device (not shown) connected by the DBU 10 is prevented.

【0013】次に、シーケンス制御の動作の詳細につい
て説明する。
Next, details of the sequence control operation will be described.

【0014】スイッチ2がONすることにより、電源ユ
ニット3に交流電源1が入力され、電源ユニット3は動
作を開始し、DC+5V,+12Vを出力する。電源ユ
ニット3の出力端に接続した誤動作防止回路4は、制御
IC5へ供給されるDC+5Vが定電圧ダイオードD1
のツェナー電圧以上に達すると、抵抗器R1を通してト
ランジスタQのベースをドライブし、トランジスタQは
ONする。トランジスタQがONすると、リレーRLが
ONし、リレー接点rlがa側に切り替わり、DC+1
2VをRS232C6(負荷側)へ供給する。よって電
源ユニット3は誤動作防止回路4を中継し、負荷装置制
御部7へDC+5V,+12Vを供給していることにな
る。この状態からスイッチ2をOFFすると、電源ユニ
ット3は停止し、DC+5V,+12Vはそれぞれ出力
コンデンサC1,C2+C3と負荷装置制御部7の負荷
の放電時間で垂下する。誤動作防止回路4のOFF時の
動作は、まずDC+5V出力の電圧が低下し、停電圧ダ
イオードD1のツェナー電圧以下になると、トランジス
タQのベースをドライブできなくなり、トランジスタQ
はOFFする。トランジスタQがOFFすると、リレー
RLに印加されていた電圧もなくなり、リレー接点rl
はb側に切り替わり、DC+12V出力電圧の供給はた
たれ、負荷装置制御部7の入力コンデンサC3に残った
電圧は、放電抵抗器R3を通して放電される。よってR
S232C6に入力される+12Vの立ち下りは、負荷
装置制御部7の入力コンデンサC3と放電抵抗器R3の
放電時間によって決り、これは電源ユニット3の出力コ
ンデンサC1と比較すると、非常に小さい時定数なの
で、すばやく立ち下る。誤動作防止回路4を中継した負
荷装置制御部7の電源シーケンスを図2に示す。DC+
5Vがツェナー電圧11となると、動作時間t後、DC
+12Vが立ち下り、RS232C6の誤出力がなくな
る。
When the switch 2 is turned on, the AC power supply 1 is input to the power supply unit 3, the power supply unit 3 starts operating, and outputs DC + 5V and + 12V. In the malfunction prevention circuit 4 connected to the output terminal of the power supply unit 3, DC + 5V supplied to the control IC 5 is a constant voltage diode D1.
When the voltage exceeds the Zener voltage of, the base of the transistor Q is driven through the resistor R1 and the transistor Q is turned on. When the transistor Q turns ON, the relay RL turns ON, the relay contact rl switches to the a side, and DC + 1
2V is supplied to RS232C6 (load side). Therefore, the power supply unit 3 relays the malfunction prevention circuit 4 and supplies DC + 5V and + 12V to the load device controller 7. When the switch 2 is turned off in this state, the power supply unit 3 is stopped and DC + 5V and + 12V droop during the discharge time of the output capacitors C1, C2 + C3 and the load device controller 7, respectively. The operation of the malfunction prevention circuit 4 at the time of OFF is that when the voltage of the DC + 5V output drops and becomes equal to or lower than the Zener voltage of the quiescent voltage diode D1, the base of the transistor Q cannot be driven and the transistor Q does not operate.
Turns off. When the transistor Q is turned off, the voltage applied to the relay RL also disappears and the relay contact rl
Is switched to the b side, the supply of the DC + 12V output voltage is dropped, and the voltage remaining in the input capacitor C3 of the load device control unit 7 is discharged through the discharge resistor R3. Therefore R
The fall of + 12V input to S232C6 is determined by the discharge time of the input capacitor C3 and the discharge resistor R3 of the load device controller 7, which is a very small time constant compared with the output capacitor C1 of the power supply unit 3. , Get off quickly. FIG. 2 shows a power supply sequence of the load device controller 7 that relays the malfunction prevention circuit 4. DC +
When 5V becomes the Zener voltage 11, after operation time t, DC
+ 12V falls and RS232C6 erroneous output disappears.

【0015】[0015]

【発明の効果】以上説明したように、本発明の多電源負
荷装置誤動作防止回路は、多出力電源の+5V,+12
V出力電圧間の立ち下りシーケンスの制御する制御回路
と軽負荷時の立ち下りを速くするためのリレー接点と放
電抵抗器とを有するシーケンス制御機能を備えた誤動作
防止回路を電源ユニットと負荷装置制御部に挿入し、電
源OFF時に制御系出力より他出力を早く立ち下げるこ
とにより、軽負荷状態での電源OFFの際、出力電圧の
立ち下り時間の遅延に伴う負荷装置の誤動作を防止する
ことができるという効果がある。
As described above, the multiple power supply load device malfunction prevention circuit according to the present invention has a multi-output power supply of +5 V and +12.
A malfunction prevention circuit having a sequence control function having a control circuit for controlling a falling sequence between V output voltages, a relay contact for speeding up the falling at a light load, and a discharge resistor is provided for controlling a power supply unit and a load device. When the power supply is turned off in a light load state, the malfunction of the load device due to the delay of the fall time of the output voltage can be prevented by inserting the power supply into the control unit and turning off the other output earlier than the control system output when the power is turned off. The effect is that you can do it.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の多電源負荷装置誤動作防止
回路を適用した電源及び負荷装置制御回路のブロック図
である。
FIG. 1 is a block diagram of a power supply and load device control circuit to which a multiple power load device malfunction prevention circuit according to an embodiment of the present invention is applied.

【図2】図1の負荷装置制御部7の電源シーケンスを示
す図である。
FIG. 2 is a diagram showing a power supply sequence of a load device control section 7 in FIG.

【図3】従来例の電源及び負荷装置制御回路のブロック
図である。
FIG. 3 is a block diagram of a conventional power supply and load device control circuit.

【図4】図3の負荷装置制御部7の電源シーケンスを示
す図である。
FIG. 4 is a diagram showing a power supply sequence of the load device control section 7 of FIG.

【符号の説明】[Explanation of symbols]

1 交流電源 2 スイッチ 3 電源ユニット 4 誤動作防止回路 5 制御IC 6 RS232C 7 負荷装置制御部 8 RS出力 9 制御回路 10 DBU 11 ツェナー電圧 12a,b 端末装置 R1,R2,R3 抵抗器 C1,C2,C3 コンデンサ D1 ツェナーダイオード D2 ダイオード R1 リレー(コイル) rl リレー接点 Q トランジスタ t リレー動作時間 1 AC power supply 2 Switch 3 Power supply unit 4 Malfunction prevention circuit 5 Control IC 6 RS232C 7 Load device control section 8 RS output 9 Control circuit 10 DBU 11 Zener voltage 12a, b Terminal device R1, R2, R3 Resistor C1, C2, C3 Capacitor D1 Zener diode D2 Diode R1 Relay (coil) rl Relay contact Q Transistor t Relay operating time

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 多出力電源を有する電源ユニットと、前
記電源ユニットより電源電圧が供給され接続されている
負荷装置を制御する負荷装置制御部との間に、前記電源
ユニットの出力電圧間のシーケンス制御を行う手段を備
えることを特徴とする多出力電源負荷装置誤動作防止回
路。
1. A sequence between output voltages of the power supply unit between a power supply unit having a multi-output power supply and a load device control section for controlling a load device to which a power supply voltage is supplied from the power supply unit and which is connected. A multi-output power supply load device malfunction prevention circuit comprising means for performing control.
JP4177868A 1992-07-06 1992-07-06 Erroneous function preventive circuit for multi-output power supply load device Pending JPH0622451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4177868A JPH0622451A (en) 1992-07-06 1992-07-06 Erroneous function preventive circuit for multi-output power supply load device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4177868A JPH0622451A (en) 1992-07-06 1992-07-06 Erroneous function preventive circuit for multi-output power supply load device

Publications (1)

Publication Number Publication Date
JPH0622451A true JPH0622451A (en) 1994-01-28

Family

ID=16038473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4177868A Pending JPH0622451A (en) 1992-07-06 1992-07-06 Erroneous function preventive circuit for multi-output power supply load device

Country Status (1)

Country Link
JP (1) JPH0622451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292154A (en) * 2016-06-07 2018-07-17 富士电机株式会社 Power supply relay unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292154A (en) * 2016-06-07 2018-07-17 富士电机株式会社 Power supply relay unit

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