JPH06222741A - Driving method for liquid crystal display device and driving circuit - Google Patents

Abstract

PURPOSE:To perform display of high quality by using a low voltage drain driver. CONSTITUTION:Each pixel of a liquid crystal panel 120 is alternately connected to two signal driving circuits 114 and 115 in the direction of a line. An alternating current circuit 126 supplies a low level reference voltage and high level reference voltage, having reversed polarity to the opposed voltage of a constant voltage to the two signal driving circuits 114 and 115. Level shifters 110 and 113 transform a voltage level of display data to a voltage level between the low level reference voltage and the high level reference voltage supplied to the corresponding signal driving circuits 114 and 115, and supply it to the corresponding signal driving circuits 114 and 115. The signal driving circuits 114 and 115 operate with the supplied voltage between the low level reference voltage and the high level reference voltage, an drives connected pixels according to supplied display data. Voltage distortion is reduced by making polarity of the reference voltage supplied to the two signal driving circuits 114 and 115 AC with a frame period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique for a liquid crystal panel using a low withstand voltage drain driver, and more particularly to a technique for improving image quality.

[0002]

2. Description of the Related Art As a conventional driving technique for a TFT liquid crystal panel, a flat panel display 1991, "TF
T-color LCD multi-color technology, from 4096 colors to over 260,000 colors "(November 26, 1990, Nikkei B)
A technique using a high breakdown voltage drain driver described in P173, P173 to P180) is known. Further, as in the "liquid crystal drive circuit" described in JP-A-57-49995, there is known a technique of using a low breakdown voltage drain driver to drive a liquid crystal panel while alternating the counter electrode voltage.

Here, the drain driver is a circuit that applies a voltage to the drain electrode of the liquid crystal that determines the brightness of the liquid crystal. The high breakdown voltage drain driver is a drain driver having a breakdown voltage capable of generating a voltage corresponding to the maximum brightness and a minimum brightness for each of the positive polarity and the negative polarity. The low breakdown voltage drain driver is a drain driver having a breakdown voltage that can generate a voltage corresponding to the maximum brightness and the minimum brightness of the liquid crystal only for one polarity of positive polarity or negative polarity.

These two conventional techniques will be described below.

First, a liquid crystal display device using a high breakdown voltage drain driver will be described.

FIG. 40 shows the structure of a conventional liquid crystal display device using a high breakdown voltage drain driver.

In the figure, 101 is a system bus for transferring digital display data and a synchronizing signal. The display data and the synchronization signal transferred by the system bus 101 are transferred according to the line-sequential scanning method. That is, it is transferred in the same manner as the display data of the CRT display device and the synchronous bedding tail.

Next, 102 is a liquid crystal controller,
The digital display data and the sync signal transferred by the system bus 101 are converted into digital liquid crystal display data and timing signals for driving the liquid crystal display device. 103, 10
4, 105 are reference voltages, 103 is a digital low drive voltage VEE, 104 is a digital high drive voltage VCC,
Reference numeral 105 is a DC voltage having each voltage of the liquid crystal driving voltage. Signal drive circuit control buses 106 and 107 both transfer the digital liquid crystal display data converted for the signal drive circuit and the timing signal by the liquid crystal controller 102. Reference numeral 108 denotes a scan drive circuit control bus,
Transfers timing signals for the scan drive circuit. Reference numeral 109 is a liquid crystal alternating signal, which is a timing signal for alternating the voltage polarity applied to the liquid crystal.

Reference numerals 2401 and 2402 denote signal drive circuits, which take in digital liquid crystal display data transferred by the signal drive circuit control buses 106 and 107, respectively, by a timing signal and convert the liquid crystal applied voltage corresponding to the liquid crystal display data. Reference numerals 116 and 117 denote signal lines, which are liquid crystal applied voltages VD generated by the signal drive circuits 2401 and 2402, respectively.
Transfer U and VDL.

Reference numeral 118 is a scanning drive circuit, and 119 is a scanning line. The scan drive circuit 118 sequentially enables the scan lines 118 according to the timing signal transferred by the scan drive circuit control bus 108.

Next, 120 is a liquid crystal panel. Also,
Reference numeral 2403 is a reference DC voltage generating circuit, which generates various DC voltages serving as a reference for operating the liquid crystal display device. A scan driving circuit DC voltage line 122 is supplied to the scan driving circuit 118.

Reference numeral 123 is a counter electrode line, which transfers a DC counter voltage VCOM. 2404 is a signal drive circuit 240
High level reference voltage VC for driving 1, 2402
C is a reference voltage line for transferring C, similarly 2405 is a reference voltage line for transferring a low-level reference voltage VEE, and 2406 is a liquid crystal driving voltage VLCD for driving the liquid crystal driving circuit portion of the signal driving circuits 2401, 2402. Is a liquid crystal drive unit reference voltage line for transferring Reference voltage line 240
The reference voltages transferred at 4, 2405 and 2406 are all DC voltages.

Next, 125 is a DC liquid crystal applied voltage for the signal drive circuit. Reference numeral 131 is an AC circuit. Reference numeral 132 denotes a liquid crystal drive voltage line used for the upper signal drive circuit 2401 for transferring the AC liquid crystal drive voltage, and 133 denotes a liquid crystal drive voltage line used for the lower signal drive circuit 2402 for transferring the AC liquid crystal drive voltage. Is.

Next, FIG. 41 shows the internal structure of the signal drive circuit 2401. The signal drive circuit 2402 below the liquid crystal panel 120 also has the same configuration.

In FIG. 41, 2501-1 and 2501
-, ... Are drain drivers, and the signal drive circuit 2
401 is composed of a plurality of drain drivers 2501. The drain driver 2501 inputs digital liquid crystal display data, converts it into a liquid crystal applied voltage, and outputs it.

2 of the control buses 106 for the signal drive circuit
Reference numeral 502 is a shift clock, 2503 is a latch clock, and 2504 is a liquid crystal display data bus. The shift clock 2502 is synchronized with the digital liquid crystal display data transferred by the liquid crystal display data bus 2504, and the latch clock 2503 is valid after the digital liquid crystal display data for one horizontal line is transferred to the signal drive circuits 2401, 2402. Become.

Reference numeral 2505 is a shift register, and
6 is a latch signal. The shift register 2505 receives the shift clock 2502 and performs a shift operation.
By this shift operation, the latch signal 2506 is sequentially validated.

Reference numeral 2507 denotes a latch circuit, which sequentially latches the digital liquid crystal display data transferred by the liquid crystal display data bus 2504 by a latch signal 2503. Two
A data bus 508 transfers the data latched by the latch circuit 2507. A latch circuit 2509 latches the data transferred on the data bus 2508 with a latch clock 2503. A data bus 2510 transfers the data latched by the latch circuit 2509.

Reference numeral 2511 denotes a level shifter, which converts the voltage amplitude level of digital data transferred by the data bus 2510. Reference numeral 2512 is a data bus for transferring digital data after converting the voltage amplitude level. Reference numeral 2513 denotes a digital-analog conversion circuit, which is a data bus 2512.
The digital data transferred by the AC liquid crystal drive voltage line 1
Based on the AC voltage transferred at 32, it is converted into a liquid crystal applied voltage. A signal line 116 transfers the liquid crystal applied voltage generated by the digital-analog conversion circuit 2513. 25
Reference numeral 14 is an enable signal, and when the latch circuit 2507 finishes capturing the digital liquid crystal display data, that is,
When the shift operation of the shift register 2505 is completed, the shift register 250 of the next-stage drain driver 2501
5 is a control signal for activating No. 5 and the latch circuit 2507 of the drain driver 2501 at the next stage starts the operation of taking in digital liquid crystal display data.

In the drain driver 2501, the shift register 2505, the latch circuit 2507, and the digital circuit portion of the latch circuit 2509 are driven by the high-level reference voltage transferred by the reference voltage line 2404 and the low-level reference voltage transferred by the reference voltage line 2405. Level shifter 251
1. The analog circuit portion of the digital-analog conversion circuit 2513 is driven by the liquid crystal drive voltage transferred by the reference voltage line 2406.

Next, FIG. 5 shows an equivalent circuit of the liquid crystal panel 120.

In the figure, DU (m), DU (m + 1), DL
(M) and DL (m + 1) are both signal lines 116 and 117.
Is a signal line corresponding to the pixel portion constituting the. G (n-
All of 1), G (n), and G (n + 1) are scanning lines corresponding to the respective pixel portions forming the scanning line 119. 501 is a pixel portion. Of the pixel portion 501, 502 T hin F
ilm T ransister a (hereinafter, abbreviated as TFT.), 503 is a liquid crystal, 504 is an additional capacitor.

The drain electrode of the TFT 502 is the signal line 11
6 and the gate electrode is connected to the scanning line 119. The TFTs 5 in each pixel portion 501 arranged in the vertical direction
The drain electrode of 02 shares a signal line (for example, DU (m)). Further, the gate electrode of the TFT 502 in each pixel portion 501 arranged in the horizontal direction is a scanning line (for example, G
(N)) is shared.

On the other hand, the source electrode of the TFT 502 is connected to the liquid crystal 503 and one electrode of the additional capacitor 504.
The other electrode of the liquid crystal 503 is connected to the counter electrode line 123, and all the pixels share the common counter electrode line 123. The other electrode of the additional capacitor 504 is connected to the preceding scanning line, and for example, in the case of the additional capacitor 504 connected to the TFT 502 controlled by the scanning line G (n),
The other electrode is connected to the scanning line G (n-1).

As described above, the liquid crystal panel has a matrix structure having a plurality of pixel portions 501 in the horizontal and vertical directions. For example, to realize a screen with a horizontal resolution of 640 pixels and a vertical resolution of 480 lines, 1 is set in the horizontal direction.
920 pixels are arranged, and Re is applied to three adjacent pixels.
A horizontal resolution of 640 pixels is realized by adding color filters of d, Green, and Blue to form one pixel. Further, in the vertical direction, a vertical resolution of 480 lines is realized by configuring the pixel configuration described in the horizontal direction for 480 lines.

Hereinafter, the operation of such a liquid crystal display circuit will be described.
This will be described with reference to FIGS.

FIG. 42 shows a drive voltage waveform. It should be noted that this voltage waveform shows line AC drive in which the polarity of the voltage applied to the liquid crystal is switched for each line.

In FIG. 42, VG (n) is the voltage waveform of the scanning line G (n) shown in FIG. 5, and VG (n + 1) is the voltage waveform of the scanning line G (n + 1). VGH is scan line 1
19 is the selection voltage level and VGL is the non-selection voltage level. VCOM is a voltage value of the counter electrode 123.
The voltage level of the reference voltage line 2406 is VLCD and the voltage level of the reference voltage 2405 is VEE. VDU,
VDL is a drive waveform of the liquid crystal applied voltage output to the signal lines 116 and 117. It should be noted that this voltage waveform shows line AC drive in which the polarity of the voltage applied to the liquid crystal is switched for each line. Further, FIG. 43 is a diagram showing the relationship between the voltage of the liquid crystal and the luminance.

In the figure, the vertical axis represents the luminance and the horizontal axis represents the liquid crystal applied voltage. Reference numeral 901 denotes a luminance-voltage characteristic when the positive voltage is applied, and 902 is a voltage-luminance characteristic when the negative voltage is applied. As can be seen from the figure, the liquid crystal has a characteristic of displaying the same luminance as long as the absolute value is the same regardless of whether the positive or negative voltage is applied to the counter electrode voltage VCOM.
Further, in this figure, when the voltage value applied to the liquid crystal is small, that is, when the applied voltage is a voltage close to the voltage value of the counter electrode 123 (for example, voltage + VDW, voltage −VDW),
It has a characteristic that the brightness is high and the brightness becomes low as the applied voltage increases in both the positive voltage and the negative voltage (voltage + VDB, voltage -VDB). The voltage VEE is the drain driver 25
01 is a low level reference voltage, and the voltage VLCD is a liquid crystal drive unit reference voltage.

Now, referring to FIG. 40, the system bus 10
The digital liquid crystal display data transferred at 1 is converted into a liquid crystal applied voltage via the liquid crystal controller 102 and the signal drive circuits 2401 and 2402, and is output to the liquid crystal panel 120 to display. In the liquid crystal controller 102, the digital display data input through the system bus 101 is converted into a synchronous signal so as to follow the input interfaces of the signal drive circuits 2401 and 2402 and the pixel configuration of the liquid crystal panel 120, and the signal drive circuit control buses 106 and 107. Output via.
The digital liquid crystal display data and timing signals via the signal drive circuit control buses 106 and 107 are transferred to the signal drive circuit 1.
It is input to 14, 115 and converted into a liquid crystal applied voltage.

That is, the signal drive circuit 11 shown in FIG.
The shift register 2505-1 in the drain drivers 2501-1 of Nos. 4 and 115 starts its operation by the shift clock 2502 and sequentially validates the latch signal 2506-1. The storage circuit in the latch circuit 2507-1 corresponding to the validated latch signal 2506-1 sequentially latches the digital liquid crystal display data transferred by the display data bus 2504. The latched data is output to the data bus 2508-1. When the data capturing operation by the storage circuit in the latch circuit 2507-1 is completed,
That is, when the shift operation of the shift register 2505-1 is completed, the shift register 2505-1 enables the enable signal 2514-1. Enable signal 2514-
1 becomes valid, the drain driver 2501-of the next stage
The shift register 2505-2 in 2 starts operating.
Then, the latch circuit 2507-2 sequentially latches the data after being latched by the latch circuit 2507-1 in the drain driver 2501-1. Further, the latch circuit 250
When the operation of fetching the data by the storage circuit in 7-2 is completed, the enable signal 2514-2 is enabled, and the drain driver 2501 at the next stage is set to the drain driver 2501
-1, 2501-2. Each drain driver 2501 in the signal drive circuits 2401 and 2402
However, by performing such an operation, the liquid crystal display data for one horizontal line can be fetched.

After the liquid crystal display data for one horizontal line is fetched by the latch circuit 2507 in each drain driver 2501, the latch clock 2503 becomes valid, and the latch circuit 2508 transferred by the data bus 2508 of each drain driver 2501. The stored data is latched by the latch circuit 2509 for one horizontal line at the same time.

After the data is stored in the latch circuit 2509, the shift register 2 of each drain driver 2501
505 and the latch circuit 2507 start an operation similar to the above operation in order to take in the data of the next line.

Here, the driving voltage of the drain driver 2501 of the shift register 2505, the latch circuit 2507, and the latch circuit 2509 is different from that of the digital-analog conversion circuit 2513. The digital circuit portion operates with the low level reference voltage transferred by the reference voltage line 2405 and the high level reference voltage transferred by the reference voltage line 2404. However, the level shifter 2511 and the digital-analog conversion circuit 2513 need to be operated by the liquid crystal drive voltage VLCD transferred by the reference voltage line 2406.

By the way, the liquid crystal deteriorates when a DC voltage is continuously applied. Therefore, the voltage applied to the liquid crystal must be made alternating with a certain period. Further, during the display of one frame, the luminance display by the applied voltage of the positive polarity and the luminance display by the applied voltage of the negative polarity are made uniform, so that the deterioration of the image quality due to the flicker can be prevented. On the other hand, as shown in FIG. 43, the liquid crystal has a characteristic of performing the same brightness display as long as the absolute values thereof are equal to each other even if the positive and negative voltages are applied to the counter electrode voltage VCOM.

Therefore, the polarity of the applied voltage with respect to the counter voltage VCOM is made alternating for each line and each frame. However, for this purpose, therefore, the digital-analog conversion circuit 2513 must be able to periodically apply a negative polarity voltage and a positive polarity voltage to the liquid crystal. That is, when a negative voltage is applied to the voltage counter voltage, voltage -VDW is applied when high brightness display is performed, voltage -VDB is applied when low brightness display is performed, and the counter voltage is applied. On the other hand, in the case of applying a positive voltage, it is necessary to be able to apply the voltage + VDW when performing high-luminance display and to be able to apply the voltage + VDB when performing low-luminance display. Therefore, the digital-analog conversion circuit 2513 is
A liquid crystal drive voltage VLCD satisfying (VLCD−VEE)> (+ VDB − (− VDB) is applied by the reference voltage line 2406 to operate.

Further, in order to interface the digital-analog conversion circuit 2513 and the latch circuit 2509 which operate with different drive voltages, the level shifter 2511 which operates with the liquid crystal drive voltage VLCD includes a latch circuit 2509 and a digital-analog conversion circuit 2513. Convert voltage between The data stored in the latch circuit 2509 is voltage-converted by the level shifter 2511 via the data bus 2510, and the converted data is transferred via the data bus 2512.
It is transferred to the digital-analog conversion circuit 2513. In the digital-analog conversion circuit 2513, the liquid crystal drive voltage line 2
The liquid crystal drive voltage VLCD transferred at 406 is used to generate a liquid crystal applied voltage corresponding to the data and output it to the signal line 116.

Now, the signal drive circuits 2401, 2402,
The display data transferred through the system bus 101 is converted into liquid crystal applied voltages by the AC circuit 131, and the liquid crystal applied voltages VDU and VDL shown in FIG. 42 are output to the liquid crystal panel 120. That is, the signal line 116 is supplied with the voltage VDU described in the drive waveform diagram of FIG. 42 from the signal drive circuit 2401. The voltage VDL described in the drive waveform diagram of FIG. 42 is applied to the signal drive circuit 240 on the signal line 117.
Supplied from 2.

On the other hand, the scan drive circuit 118 performs a shift operation and sequentially applies the selection voltage VGH to each horizontal line via the scan drive circuit control bus 108. Selection voltage VG
The scanning line 119 connected to the horizontal line to which H is applied becomes effective. For example, the scanning line G (n) is selected by the selection voltage VG.
H becomes valid for one line period, and then the non-selection voltage VG
L continues for one frame period. Select voltage V of scanning line G (n)
When GH is valid, the TFT 502 of the pixel portion 501 connected to the scanning line G (n) illustrated in FIG. 5 is turned on, and the voltage appearing on the signal lines 116 and 117 is applied to the TFT 50.
2 is stored in the liquid crystal 503 and the load capacitance 504 via
The display of the brightness according to this is performed.

Next, a conventional liquid crystal display device using a low breakdown voltage drain driver will be described.

First, FIG. 44 shows the structure of the liquid crystal display device.

In the figure, reference numerals 2801 and 2802 denote signal driving circuits, which take in the digital liquid crystal display data transferred by the signal driving circuit control buses 106 and 107 by timing signals and convert them into liquid crystal applied voltage corresponding to the liquid crystal display data. To do. Signal lines 116 and 117 transfer the liquid crystal applied voltage generated by the signal drive circuits 114 and 115, respectively. Reference numeral 2803 is a reference DC voltage generating circuit, which generates various DC voltages serving as a reference for operating the liquid crystal display device. 2804 is a DC voltage line. Reference numeral 2805 is a DC voltage line for the signal drive circuit. Reference numeral 2806 is an AC circuit. Reference numeral 2807 denotes a reference voltage line that transfers the AC-selected non-selected voltage output from the scanning circuit 118. Reference numeral 123 is a counter electrode line, which transfers a counter voltage converted into an alternating current. 2808
Is an AC circuit, which is a circuit for converting the liquid crystal drive voltage supplied to the signal drive circuit 2801 into an alternating current, and 2809 is a liquid crystal application voltage line for transferring the alternating liquid crystal application voltage used in the upper signal drive circuit 2802, Reference numeral 2810 is a liquid crystal applied voltage line that transfers the AC applied liquid crystal applied voltage used in the lower signal drive circuit 115.

Next, FIG. 45 shows the structure of the signal drive circuit 2801.

In the figure, 2901-1, 2901-2, ...
Is a drain driver, and the signal drive circuit 2801 is composed of a plurality of drain drivers 2901. The drain driver 2901 inputs digital liquid crystal display data, converts it into a liquid crystal applied voltage, and outputs it to the liquid crystal panel 120. Of the signal drive circuit control bus 106, 2904 is a liquid crystal display data bus, 2902 is a shift clock, and 2903 is a latch clock. The shift clock 2902 is synchronized with the digital liquid crystal display data transferred by the liquid crystal display data bus 2904, and the latch clock 2903 is valid after the digital liquid crystal display data for one horizontal line is transferred to the signal drive circuits 2801 and 2802. Become. Reference numeral 2905 denotes a digital-analog conversion circuit, which converts digital data transferred by the data bus 2510 into liquid crystal applied voltage based on the liquid crystal drive voltage transferred by the liquid crystal drive voltage line 2809. A signal line 116 transfers the liquid crystal applied voltage generated by the digital-analog conversion circuit 409. The drain driver 2901 differs from the high withstand voltage drain driver shown in FIG. 41 in that all of the shift register 403, the latch circuit 405, the digital circuit portion of the latch circuit 407, and the digital-analog converter circuit 2905 are transferred by the reference voltage line 2404. That is, the low level reference voltage transferred by the level reference voltage and the reference voltage line 2405 is used for driving.

The operation of this liquid crystal display device will be described below.

First, FIG. 46 shows the waveform of the drive voltage supplied to the liquid crystal panel 120.

In the figure, VG (n) is the scanning line G shown in FIG.
(N) is a voltage waveform, and VG (n + 1) is a voltage waveform of the scanning line G (n + 1) shown in FIG. VGH is a selection voltage level of the scanning line 119, and VGLH and VGLL are non-selection voltage levels. VCOMH is the counter electrode 123
Is the high-level counter voltage value of VCOML, and VCOML is the low-level counter voltage value of the counter electrode 123. VDU, VDL
Is a liquid crystal applied voltage output from the signal drive circuits 114 and 115. The voltage waveform shows line AC drive in which the polarity of the voltage applied to the liquid crystal is switched for each line.

Next, FIG. 47 shows the relationship between the liquid crystal voltage and the luminance.

In the figure, the horizontal axis represents the luminance and the vertical axis represents the liquid crystal applied voltage. Reference numeral 901 denotes a brightness-voltage characteristic when the positive voltage is applied, and 902 is a brightness-voltage characteristic when the negative voltage is applied.

As shown in the figure, this liquid crystal has the highest brightness when no voltage is applied to the liquid crystal, that is, when the applied voltage is 0 V, and the brightness becomes lower as the applied voltage increases for both positive and negative voltages. Have characteristics. Regardless of the polarity of the applied voltage, the liquid crystal displays the same brightness if the absolute voltage value with respect to the voltage of the counter electrode 123 is the same. Therefore, if two counter voltages, VCOMH and VCOML, are provided, as shown in the figure. , Two voltage-luminance characteristics are obtained for each.

Now, referring to FIG. 44, the system bus 10
The digital display data transferred at 1 is converted into a liquid crystal applied voltage through the liquid crystal controller 102 and the signal drive circuits 2801 and 2802, and is output to the liquid crystal panel 120 for display. In the liquid crystal controller 102, the digital drive data input through the system bus 101 is supplied to the signal drive circuit 2
801, 2802 input interface and liquid crystal panel 1
It is converted by a synchronizing signal so as to follow the 20 pixel configuration and is output via the signal drive circuit control buses 106 and 107.

The operation of the drain driver 2901 of FIG. 45 is the same as that of the high withstand voltage drain driver (2501 in FIG. 45).
However, the difference is that the digital-analog conversion circuit 2908 has a shift register 2505 and a latch circuit 25.
07, the latch circuit 2509 operates at a low voltage of the same voltage as that of each digital circuit portion. However, in order to obtain the required display brightness at a low voltage, the drive system that applies a voltage to the liquid crystal is devised.

That is, as shown in the voltage-luminance characteristic diagram of FIG. 47, two opposing voltages of VCOML and VCOMH are provided. When the voltage applied to the liquid crystal is a positive polarity voltage, the voltage-luminance characteristic curve 901 is used. That is, the counter voltage VCOML is used, and the voltage applied to the liquid crystal is higher than the counter voltage VCOML. For example, when high brightness display is performed, the voltage VDWH
Is applied to the liquid crystal and low brightness display is performed,
The voltage VDBH is applied to the liquid crystal. On the other hand, when the voltage applied to the liquid crystal is a negative voltage, the voltage-luminance characteristic curve 902 is used. That is, the counter voltage VCOMH is used, and the voltage applied to the liquid crystal is lower than the counter voltage VCOMH. For example, the voltage VDWL is applied to the liquid crystal when performing high-luminance display, and the voltage VDBL is applied to the liquid crystal when performing low-luminance display.

Here, these liquid crystal applied voltages VDWH,
VDBH, VDWL, and VDBL are digital-analog conversion circuits 2908 in the drain driver 2901 illustrated in FIG. 45.
Can be generated within the voltage range of the reference voltage VCC-VEE supplied to the.

In order to prevent the occurrence of flicker,
As shown in FIG. 46, the counter voltage VCO of the counter electrode line 123
In synchronization with the liquid crystal alternating signal 109, M is converted into AC for each line. Therefore, the liquid crystal applied voltage generated by the signal drive circuits 2801 and 2802 becomes like VD, and the counter voltage VCO
With respect to M, when the potential difference is small, the brightness is high, and when the potential difference is large, the brightness is low.

Further, in the even-numbered frame, the deterioration of the liquid crystal can be prevented by changing the polarity of the voltage applied to the odd-numbered frame and the liquid crystal.

However, in FIG. 5, when the capacitance of the liquid crystal 503 constituting each pixel portion 501 is Clc and the capacitance of the additional capacitance 504 is Cadd, the positive voltage Vcl at the counter voltage VCOML is held by the liquid crystal 503. In this case, when the counter voltage is converted to VCOMH, the holding voltage of the liquid crystal 503 becomes Cadd / (Clc + Cadd) × (VCOM
(H-VCOML) voltage fluctuation will occur.

This is because one electrode of the additional capacitance Cadd is composed of the preceding scanning line 119, and the counter voltage VCO
This is because the voltage is constant despite the fluctuation of M. This means that the liquid crystal applied voltage changes in the liquid crystal 503 due to the alternating voltage of the counter voltage VCOM during the holding period, and the display brightness changes line by line.

Therefore, in order to eliminate the voltage fluctuation of the voltage applied to the liquid crystal during the holding period, the scanning line 119 in the preceding stage needs to be AC-converted by the AC voltage value of the counter voltage VCOM.

Therefore, when the counter voltage is VCOML, the non-selection voltage level of the scanning line 119 is VGLL, and when the counter voltage is VCOMH, the non-selection voltage level of the scanning line 119 is VGLH. Note that (VGLH-VGLL) =
By setting (VCOMH-VCOML), the voltage applied to the liquid crystal does not change.

Here, the alternating current of the non-selection voltage VGL is performed by the alternating current circuit 2806 in FIG.

By such an operation, the pixel section 5 of FIG.
The polarity of the voltage applied to 01 is as shown in FIG.

That is, since the counter electrode 123 is common to the liquid crystals 503 in all the pixel portions 501, when the counter voltage is VCOMH, all the voltages that can be applied to the liquid crystal are negative voltages, and the counter voltage is Is VCOML,
All voltages that can be applied to the liquid crystal are positive. Therefore, the polarity of the applied voltage is the same in one horizontal line, and the polarity is inverted line by line. Then, in the pixel portion 501 to which the positive voltage is applied,
A current flows out through the liquid crystal 503 to the counter electrode line 123, and a current flows out through the additional capacitor 504 to the preceding scanning line 119. Pixel portion 5 to which a negative voltage is applied
In 01, a current flows in from the counter electrode line 123 via the liquid crystal 503, and a current flows from the scanning line 119 in the preceding stage via the additional capacitance 504.

[0064]

In the case of using the high withstand voltage drain driver, the signal drive circuit 240 is used.
1 and 2402 are large and expensive. This is because it is necessary to use a high breakdown voltage process when manufacturing the signal drive circuits 2401 and 2402 in an LSI.

That is, the minimum size of the element used in the high breakdown voltage process is about 3 to 5 times larger than the minimum size of the low breakdown voltage process used in the digital circuit or the like. When a circuit having the same function and characteristics except the output voltage is constructed, the circuit area is about the square of the minimum element size. Therefore, the circuit constructed by the high breakdown voltage process is the circuit constructed by the low breakdown voltage process. However, the size is about 10 to 20 times. Moreover, since the price of the LSI depends on the size of the chip size, the drain driver 2501 configured by the high breakdown voltage process is more expensive than the drain driver 2501 configured by the low breakdown voltage process.

Furthermore, this makes it difficult to improve the performance of the liquid crystal display device, such as an increase in display colors. This is because the circuit scale of the drain driver 2501 increases as the display color increases.

On the other hand, since the drain driver having a low withstand voltage can be manufactured by a low withstand voltage process, such a problem does not occur. However, the counter voltage transferred by the counter electrode 123 described above is AC. In this technology, the voltage applied to each pixel portion 501 of the liquid crystal panel 120 is
As shown in FIG. 8, the polarity is inverted line by line. Therefore, the direction of the current input / output to / from the preceding scanning line 119 and the counter electrode line 123 is one for each scanning line 109.

For example, in the scanning line G (n-1),
Pixel portion 501-U (m)-(n), 501-L (m)-
Since the voltage applied to (n), 501-U (m + 1)-(n) has a positive polarity, the additional capacitance 50 of each pixel unit 501 is
The current through 4 is concentrated and flows out to the scanning line G (n-1). In the scan line G (n), the pixel portion 501-
U (m)-(n + 1), 501-L (m)-(n +
1), since the voltage applied to 501-U (m + 1)-(n + 1) has a negative polarity, the additional capacitance 5 of each pixel unit 501 is
The current flowing through 04 is concentrated and flows from the scanning line G (n).

Since the scanning line 109 has a wiring resistance, the scanning line 109 depends on the inflow / outflow current and the wiring resistance.
A voltage is generated at. In particular, in a high-definition liquid crystal panel having a large number of pixels such as a display device such as a workstation, the current between these lines is also large, so that the voltage value is large. Then, due to this voltage fluctuation, the additional capacitance 504
The applied voltage value of fluctuates. Further, a voltage fluctuation also occurs in the counter electrode line 123 due to the influence of the current concentration, and this voltage fluctuation also changes the voltage value applied to the liquid crystal 503.

The liquid crystal 503 and the additional capacitor 504
When a voltage fluctuation occurs, the normal luminance display for the display data cannot be obtained and the image quality deteriorates.

Therefore, an object of the present invention is to provide a liquid crystal display device using a drain driver having a low withstand voltage, which is superior in image quality.

[0072]

[Means for Solving the Problems] To achieve the above object,
The present invention relates to a liquid crystal display device provided with a liquid crystal panel in which liquid crystal cells are arranged in a matrix for displaying with a brightness according to an absolute value of a voltage difference between a counter voltage and an applied voltage when a selection voltage is supplied. A driving method, in which, for each line on the matrix, a common selection voltage is sequentially supplied to the liquid crystal cells belonging to the line, and a DC voltage common to all the liquid crystal cells of the liquid crystal panel is applied to each liquid crystal cell. To a liquid crystal cell of the column to which at least one column on the matrix is generated, and a voltage group in which the polarity with respect to the counter voltage is periodically inverted is generated. The generated voltage group is used to generate a voltage with a polarity corresponding to the polarity of the generated voltage group that realizes the brightness according to the content displayed on the liquid crystal cell of the line to which the selection voltage is supplied, and the applied voltage It provides a method of driving a liquid crystal display device which is characterized in that to supply.

In order to achieve the above object, the present invention provides
It is a drive circuit of a liquid crystal display device that drives a liquid crystal panel in which liquid crystal cells are arranged in a matrix for displaying with a brightness according to an absolute value of a voltage difference between an opposing voltage and an applied voltage when a selection voltage is supplied. Then, for each line on the matrix, a scanning means for sequentially supplying a common selection voltage to the liquid crystal cells belonging to the line and a voltage common to all the liquid crystal cells of the liquid crystal panel are opposed to the respective liquid crystal cells. The scan driving means applied as a voltage, and the two applied voltage values that realize the highest brightness and the lowest brightness of the liquid crystal cell used for display among the values of the applied voltage having a negative polarity with respect to the counter voltage And the minimum voltage, and
Of the applied voltage having a positive polarity with respect to the counter voltage that achieves the highest brightness or the lowest brightness, the applied voltage value having the larger absolute value of the voltage difference with respect to the counter voltage is set to the value between the maximum voltage and the lowest voltage. Of the negative drive voltage group and the positive applied voltage values that are not included as potentials, the two applied voltage values that realize the above-mentioned maximum brightness and minimum brightness are the maximum voltage and the minimum voltage. The applied voltage value of the larger absolute value of the voltage difference with respect to the counter voltage among the applied voltages of positive polarity with respect to the counter voltage that realizes the maximum brightness or the minimum brightness, which is included as a potential between the voltage and Means for generating a positive drive voltage group not included as a potential between the maximum voltage and the minimum voltage, and each liquid crystal cell in a corresponding column provided corresponding to each column on the matrix. The liquid crystal cell Of the liquid crystal cells of the column to which the selection voltage is supplied, a plurality of driving means for supplying, as an applied voltage, a voltage that realizes brightness according to the content displayed on the liquid crystal cells of the line to which the selection voltage is supplied, and the plurality of driving means. And a means for supplying the positive polarity driving voltage group and the negative polarity driving voltage group periodically and alternately to the two driving means groups that are divided, and the positive polarity driving voltage group is supplied. The drive means
The driving means, which supplies a positive applied voltage to the opposite voltage using the positive driving voltage group and is supplied with the negative driving voltage group, uses the negative driving voltage group Provided is a drive circuit for a liquid crystal display device, which is characterized by supplying a negative applied voltage with respect to a counter voltage.

[0074]

According to the driving method of the liquid crystal display device of the present invention, a DC voltage common to all the liquid crystal cells of the liquid crystal panel is applied to each of the liquid crystal cells as a counter voltage, and the polarity with respect to the counter voltage is periodically changed. By generating the voltage group to be inverted, the voltage having the polarity corresponding to the polarity of the generated voltage group is supplied to the liquid crystal panel as the applied voltage.

As described above, the applied voltage can be changed by changing the polarity of the voltage level of the voltage group. Further, since the voltage level of the voltage group used at a certain time is only on the polarity side of the applied voltage at that time, the withstand voltage of the driving means for generating the applied voltage satisfies the voltage level of the voltage group on one side of the polarity. It's enough. Therefore, a low withstand voltage drain driver can be used.

According to the drive circuit of the liquid crystal display device of the present invention, the drive means is divided into two drive means groups.
The positive polarity driving voltage group and the negative polarity driving voltage group are periodically and alternately supplied. For example, the negative polarity driving voltage group is a negative polarity applied voltage value with respect to the opposite voltage. , Which includes two applied voltage values for realizing the maximum brightness and the minimum brightness of the liquid crystal cell used for display as potentials between the maximum voltage and the minimum voltage, and which realizes the maximum brightness or the minimum brightness. Of the applied voltages of positive polarity with respect to the voltage, the applied voltage value having the larger absolute value of the voltage difference with respect to the counter voltage is not included as the potential between the maximum voltage and the minimum voltage. That is, a voltage level that is sufficient to generate a negative applied voltage and insufficient to generate a positive applied voltage is sufficient. Therefore, the withstand voltage of each drive means may be lower than the conventional high withstand voltage level. Here, for example, the negative driving voltage group includes two applied voltage values that realize the highest brightness and the lowest brightness of the liquid crystal cell used for display, among the values of the applied voltage that are negative with respect to the counter voltage. Is a voltage group in the minimum range of voltage levels including the potential between the maximum voltage and the minimum voltage, the withstand voltage can be minimized.

Further, the driving means supplied with the positive drive voltage group supplies a positive applied voltage to a part of the columns with respect to the counter voltage by using the positive drive voltage group, Since the driving means supplied with the negative drive voltage group supplies the negative applied voltage to the remaining column using the negative drive voltage group, the liquid crystal cells in one line are supplied. The voltage application characteristics of include positive polarity and negative polarity,
The voltage distortion can be reduced compared to the conventional one using a drain driver having a low withstand voltage.

[0078]

EXAMPLES Examples of the liquid crystal display device according to the present invention will be described below.

First, the first embodiment will be described with reference to FIGS.

First, the drawings used in the description of the first embodiment will be described.

FIG. 1 shows the structure of the liquid crystal display device according to the first embodiment.

In FIG. 1, 101 is a system bus for transferring digital display data and a synchronizing signal. In this embodiment, the display data and the synchronization signal transferred by the system bus 101 are signals for line-sequential scanning that conform to the display data and the synchronization signal transferred for display on the CRT display device. Reference numeral 102 denotes a liquid crystal controller, which converts digital display data and sync signals transferred by the system bus 101 into digital liquid crystal display data and timing signals for driving the liquid crystal display device. 103, 104, 105
Is a reference voltage line for transferring a reference voltage, 103 is a digital low level drive voltage VEE, 104 is a digital high level drive voltage VCC, and 105 is a liquid crystal drive voltage VLCD.
A DC voltage having each voltage level of 1.

Reference numerals 106 and 107 denote signal drive circuit control buses, both of which transfer the digital liquid crystal display data and timing signals converted by the liquid crystal controller 102 for the signal drive circuit. Reference numeral 108 denotes a scan drive circuit control bus, which transfers timing signals for the scan drive circuit. Reference numeral 109 denotes a liquid crystal alternating signal, which serves as a timing signal for alternating the drive voltage of the signal drive circuit and the voltage polarity applied to the liquid crystal. 110 and 111 are level shifters,
The voltage levels of the digital liquid crystal display data and the timing signal transferred by the signal drive circuit control buses 106 and 107, respectively, are converted into drive voltage levels of the signal drive circuit. 11
Reference numerals 2 and 113 denote signal drive circuit control buses, which transfer digital liquid crystal display data and timing signals whose voltage levels have been shifted by the level shifters 110 and 111.

Reference numerals 114 and 115 denote signal drive circuits, which take in the digital liquid crystal display data transferred by the signal drive circuit control buses 112 and 113, respectively, by a timing signal and convert them into liquid crystal applied voltages corresponding to the digital liquid crystal display data. , Output to LCD panel. Signal lines 116 and 117 transfer the liquid crystal applied voltage generated by the signal drive circuits 114 and 115, respectively. Reference numeral 118 is a scan drive circuit, and 119 is a scan line. The scan drive circuit 118 sequentially enables the scan lines 118 according to the timing signal transferred through the scan drive circuit control bus 108.

Reference numeral 120 is a liquid crystal panel. Reference numeral 121 denotes a DC reference voltage generation circuit, which generates various DC voltages serving as a reference for operating the present liquid crystal display device. A scan driving circuit DC voltage line 122 is supplied to the scan driving circuit 118. A counter electrode line 123 transfers a DC counter voltage. Reference numeral 124 is a DC reference voltage line for a signal drive circuit, and 125 is a DC liquid crystal drive voltage line for a signal drive circuit. Reference numeral 126 is an AC circuit.

Reference numeral 127 is a reference voltage line for transferring a high level reference voltage for driving the upper signal drive circuit 114, and similarly 128 is a high level reference voltage for driving the lower signal drive circuit 115. This is the reference voltage line to be transferred. Reference numeral 129 is a reference voltage line for transferring a low level reference voltage for driving the upper signal drive circuit 114,
Similarly, 130 is a reference voltage line for transferring a low level reference voltage for driving the lower signal drive circuit 115.
The reference voltage transferred by any of the reference voltage lines 129 and 130 becomes the reference voltage of the level shifters 110 and 111.
The voltage difference between the high-level reference voltage and the low-level reference voltage is
It is desirable to use 5V, which is widely used in ordinary digital circuits.

Reference numeral 131 is an AC circuit. Reference numeral 132 denotes a liquid crystal drive voltage line used for the upper signal drive circuit 114 to transfer the AC liquid crystal drive voltage, and 133 denotes a liquid crystal drive voltage line used for the lower signal drive circuit 115 to transfer the AC liquid crystal drive voltage. Is. The liquid crystal drive voltage is created according to the brightness characteristics of the liquid crystal panel used.

Next, the structure of the level shifter 110 shown in FIG. 2 is shown.

In FIG. 2, 201-1 to 201-N
Is an adder circuit that constitutes the level shifter 110. The level shifter 110 includes main adders 201-1 to 201-N.
Is added to the signal drive circuit control bus 106 for transfer, and in this embodiment, the adder circuit 201 is used for the synchronization signal.
-1 and 201-2, adder circuits 201-3 to 201-N (N- for the digital liquid crystal display data bus).
2) It has a circuit.

Reference numeral 202-1 is an amplifier, and 203-1 and
204-1, 205-1 and 206-1 are resistors. Of the signal drive circuit control bus 106, 106-1 is a shift clock, 106-2 is a latch clock,
Reference numerals 106-3 to 106-N are liquid crystal display data buses for transferring digital liquid crystal display data. 112-1 is a shift clock after level shift, 112-2 is a latch clock after level shift, and 112-3 to 1
Reference numeral 12-N is a liquid crystal display data bus for transferring the digital liquid crystal display data after the level shift, and an adding circuit 201-
The voltage level of the signal output from 1 to 201-N becomes a voltage value obtained by adding the reference voltage transferred by the reference voltage line 129 to the voltage level of the input signal. Therefore, the signals output from the adder circuits 201-1 to 201-N are
The amplitude of the voltage value representing 1'and '0' and the adding circuit 201-
The amplitudes of the voltage values representing "1" and "0" of the signals input from 1 to 201-N are the same. The level shifter 11
1 has the same configuration.

Next, FIG. 3 shows how the voltage levels are converted by the level shifters 110 and 111 shown in FIG.

Here, the latch clocks 106-1 and 10
The voltage value representing "1" of 7-1 is VCC and the voltage value representing "0" is VEE. That is, the voltage of the digital low level transferred by the reference voltage line 103 is VEE, and the voltage of the digital high level transferred by the reference voltage 104, that is, the voltage of the digital drive level is VCC. Further, the high potential voltage value of the reference voltage lines 129 and 130 is set to V with respect to VEE.
BH and the low potential voltage value are VBL with respect to VEE.

Next, FIG. 4 shows a signal drive circuit (see FIGS.
4) shows the configuration.

The signal drive circuit 115 on the lower side of the liquid crystal panel 120 has the same structure.

In FIG. 4, 401-1, 401-2,
, Are drain drivers, and the signal drive circuit 114 is composed of a plurality of drain drivers 401. The drain driver 401 has a function of inputting digital liquid crystal display data, converting it into a liquid crystal applied voltage, and outputting it to the liquid crystal panel 120. Of the signal drive circuit control bus 112, 402 is a liquid crystal display data bus, which is a general term for the liquid crystal display data buses 201-2 to 201-N shown in FIG.

112-1 is a shift clock, and 11
2-2 is a latch clock. Shift clock 112
-1 is synchronized with the digital liquid crystal display data transferred by the liquid crystal display data bus 402, and the latch clock 112-
2 is valid after the digital liquid crystal display data for one horizontal line is transferred to the signal drive circuits 114 and 115.

Reference numeral 403 is a shift register, and 404 is a latch signal. The shift register 403 receives the shift clock 112-1 and performs a shift operation. By this shift operation, the latch signal 404 becomes sequentially valid. 405 is a latch circuit, which is used for the liquid crystal display data bus 4
The digital liquid crystal display data transferred in 02 is sequentially latched by the latch signal 404. A data bus 406 transfers the data latched by the latch circuit 405. A latch circuit 407 latches the data transferred by the data bus 406 with the latch clock 112-2.

Reference numeral 408 is a data bus, which is a latch circuit 4.
The data latched at 07 is transferred. Reference numeral 409 denotes a digital-analog conversion circuit that converts the digital data transferred by the data bus 408 into a liquid crystal applied voltage based on the liquid crystal drive voltage transferred by the liquid crystal drive voltage line 132. 1
Reference numeral 16 is a signal line, which is a digital-analog conversion circuit 409.
The liquid crystal applied voltage generated in step 1 is transferred.

Reference numeral 410 denotes an enable signal. When the latch circuit 403 finishes fetching the digital liquid crystal display data, that is, when the shift operation of the shift register 403 is finished, the shift register 403 of the drain driver 401 at the next stage is operated. The next stage drain driver 401
The latch circuit 405 is a control signal for starting the operation of taking in the digital liquid crystal display data.

In the drain driver 401, the shift register 403, the latch circuit 405, and the latch circuit 407.
Digital circuit section and digital-analog conversion circuit 409
Both of them are driven by the high level reference voltage transferred by the reference voltage line 127 and the low level reference voltage transferred by the reference voltage line 129.

Next, FIG. 5 shows a liquid crystal panel (120 in FIG. 1).
Is an equivalent circuit of.

In FIG. 5, DU (m) and DU (m +
1), DL (m), DL (m + 1) are all signal lines 11
6 and 117 are signal lines corresponding to the pixel portions.
G (n-1), G (n), and G (n + 1) are scanning lines corresponding to the respective pixel portions that form the scanning line 119. 5
Reference numeral 01 is a pixel portion. In the pixel portion 501, 502 is T
hin F ilm T ransister (below, TF
Abbreviated as T. ), 503 is a liquid crystal, and 504 is an additional capacitance. The drain electrode of the TFT 502 is the signal line 1
16 and the gate electrode is connected to the scanning line 119. TFTs in each pixel portion 501 arranged in the vertical direction
The drain electrode of 502 shares a signal line (for example, DU (m)). TFTs in each pixel portion 501 arranged in the horizontal direction
The gate electrode of 502 shares a scanning line (for example, G (n)).

The source electrode of the TFT 502 is the liquid crystal 5
03, connected to one electrode of the additional capacitor 504. The other electrode of the liquid crystal 503 is connected to the counter electrode line 123, and all the pixels share the common counter electrode line 123. The other electrode of the additional capacitor 504 is connected to the preceding scanning line, and for example, T controlled by the scanning line G (n).
In the case of the additional capacitor 504 connected to the FT 502, the electrode is the scanning line G (n-1).

As described above, the liquid crystal panel 120 has a matrix structure having a plurality of pixel portions 501 in the horizontal and vertical directions. For example, when displaying a screen with a horizontal resolution of 640 pixels and a vertical resolution of 480 lines, 1920 pixels are arranged in the horizontal direction, and red, green, and blue color filters are added to three adjacent pixels, and 1 pixel is set. With the configuration, a horizontal resolution of 640 pixels can be realized. Further, in the vertical direction, a vertical resolution of 480 lines can be realized by configuring the pixel configuration described in the horizontal direction for 480 lines. In this embodiment, the signal lines of the adjacent pixel portions 501 are connected to the signal line 116.
And a signal line 117 are alternately drawn.

Note that the signal lines 116 and the signal lines 117 may be drawn out by alternating pixels.
This embodiment is also applicable to the liquid crystal panel 120 in which the other electrode of No. 4 is connected to a signal line that supplies a voltage equivalent to the counter electrode voltage supplied by the counter electrode line 123 instead of the scanning line in the preceding stage. In addition, the pixel portion 501 has an additional capacitance 50.
The present embodiment can be applied to the liquid crystal panel 120 in which 4 does not exist. Next, FIG. 6 shows the configuration of the AC circuit (126 in FIG. 1).

In FIG. 6, reference numeral 601 denotes an inverting circuit,
The polarity of the liquid crystal alternating signal 109 is inverted. 602 is an inverted liquid crystal alternating signal. 603, 604, 605,
Reference numeral 606 denotes a DC voltage line in the signal drive circuit DC reference voltage line 124. In this embodiment, the DC voltage line 6
03 is the voltage VDBHH, DC voltage line 604 is the voltage VDB
LH and the DC voltage line 605 transfer the voltage VDBHL, and the DC voltage line 606 transfers the voltage VDBLL.

Reference numerals 607, 608, 609 and 610 denote voltage selectors, which convert the input DC voltage into AC.
611, 612, 613 and 614 are voltage selectors 6, respectively.
07, 608, 609, and 610 are voltage lines that transfer the AC voltage output. 615, 616, 617, 618
Is an amplifier circuit, and voltage selectors 607, 608,
609 and 610 serve to enhance the driving capability of the AC voltage output.

Next, FIG. 7 shows the configuration of the AC circuit (131 in FIG. 1).

In FIG. 7, 701 is an inverting circuit,
The polarity of the liquid crystal alternating signal 109 is inverted. 702 is an inverted liquid crystal alternating signal. Reference numeral 703 is a DC liquid crystal drive voltage line for a signal drive circuit that transfers a positive voltage with respect to the counter voltage of the counter electrode line 123 in FIG. 1. Similarly, 704 is a DC for a signal drive circuit that transfers a negative voltage. It is a liquid crystal drive voltage line. 705 is a voltage selector for the signal drive circuit 114, and 706 is a voltage selector for the signal drive circuit 115. Reference numerals 707 and 708 denote voltage selectors 70, respectively.
5, a voltage line for transferring the liquid crystal drive voltage for the signal drive circuit, which has been converted into an alternating current by the selection operation. 70
Reference numerals 9 and 710 denote amplifier circuits, and voltage selectors 705 and 7
It plays a role of increasing the driving ability of the liquid crystal driving voltage for the signal driving circuits 114 and 115 generated in 06.

Next, FIG. 8 shows a frame AC drive for switching the polarity of the voltage applied to the liquid crystal for each frame.
The drive voltage waveform supplied to the liquid crystal panel 120 is shown.

In FIG. 8, VG (n) is the voltage waveform of the scanning line G (n) in FIG. VGH is a selection voltage level of the scanning line 119, and VGL is a non-selection voltage level. VCOM is a voltage value of the counter electrode 123. Of the voltage waveform of the high-level reference voltage line 127, VDBHH is the voltage level when the signal drive circuit 114 operates in the positive potential region, and is equivalent to the voltage level of the DC voltage line 603 in FIG. In the voltage waveform of the high-level reference voltage line 127, VDBLH is the signal drive circuit 114 in the negative potential region.
6 is the voltage level when operating, and is equivalent to the voltage level of the DC voltage line 604 in FIG. Of the voltage waveform of the low level reference voltage line 128, VDBHL is the voltage level when the signal drive circuit 114 operates in the positive potential region,
This is equivalent to the voltage level of the DC voltage line 605 in FIG. In addition, VD of the voltage waveform of the low-level reference voltage line 130
BLL is a voltage level when the signal drive circuit 114 operates in the negative potential region, and is equivalent to the voltage level of the DC voltage line 606 in FIG. In addition, the high-level reference voltage line 12
The voltage level of 8 is the same as the voltage level of the high level reference voltage line 127, and the polarity with respect to VCOM is opposite. The low-level reference voltage line 130 has the same voltage level as the low-level reference voltage line 129,
The polarities for are opposite. Further, VDU is a liquid crystal application voltage output from the signal drive circuit 114, and VDL is a liquid crystal application voltage output from the signal drive circuit 115.

Next, FIG. 9 shows the relationship between the voltage and the brightness of the liquid crystal used in this embodiment.

In FIG. 9, the vertical axis represents luminance and the horizontal axis represents liquid crystal applied voltage. Reference numeral 901 denotes a brightness-voltage characteristic when the positive voltage is applied, and 902 is a brightness-voltage characteristic when the negative voltage is applied.
The liquid crystal has a characteristic of displaying the same luminance as long as the absolute value is the same regardless of whether the positive or negative voltage is applied to the counter electrode voltage VCOM. Further, in the first embodiment, when the voltage value applied to the liquid crystal is small, that is, when the applied voltage is a voltage close to the voltage value of the counter electrode 123 (for example, voltage + VDW, voltage −VDW), the brightness is high, Both the positive voltage and the negative voltage have the characteristic that the brightness decreases as the applied voltage increases (for example, voltage + VDB, voltage −VDB).

Next, FIG. 10 shows the state of the voltage applied to each pixel portion 501 when the frame AC is performed, and the direction of the current generated in the pixel portion at that time.

Next, FIG. 11 shows a drive voltage waveform supplied to the liquid crystal panel by the line AC drive for switching the polarity of the voltage applied to the liquid crystal for each line.

In the figure, VG (n) is the scanning line G (n) in FIG.
VG (n + 1) is the voltage waveform of the scanning line G (n +
It is a voltage waveform of 1).

Next, FIG. 12 shows the state of the voltage applied to each pixel section 501 when line alternating current is performed, and the direction of the current generated in the pixel section at that time.

Next, FIG. 11 shows a circuit configuration of the digital-analog conversion circuit 409 in the drain driver (401 in FIG. 4).

Here, in the first embodiment,
The number of gradations that can be expressed per pixel will be described as 64 gradations corresponding to 6 bits of digital data.

Reference numeral 408-1-1 is 6-bit digital data, and the upper bits D5, D4, D3, D2,
Let D1 and D0. Reference numeral 1301 is a decoder, which is the top 2
It is composed of a decoder that decodes bits and a decoder that decodes the lower 4 bits.

Reference numeral 1302 denotes a high voltage selection circuit,
03-1, 1303-2, 1303-3, 1303-4
Is an analog switch that selects V4, V3, V2, and V1 voltages. 1304 is a low voltage selection circuit,
05-1, 1305-2, 1305-3, 1305-4
Is an analog switch that selects V3, V2, V1, and V0 voltages. Reference numeral 1306 is a voltage line for outputting any voltage from V4 to V1 selected by the high voltage selection circuit 1032, and 1307 is a voltage for outputting any voltage from V3 to V0 selected by the low voltage selection circuit 1034. It is a line.

As can be seen from the figure, when V4 is selected by the high voltage selection circuit 1032, the low voltage selection circuit 10
At 34, V3, similarly V3 and V2, V2 and V1, V1 and V0 form a pair, which are selected by the voltage selection circuits 1032 and 1034. 1308 is a series resistance circuit,
It is a circuit in which 16 resistors -1 to 1309-16 are connected in series. 1310-1 to 1310-15 are voltage lines that transfer the divided voltage generated by the series resistance circuit 1308. 1311 is a voltage selection circuit, and 1312-1
To 1312-16 are analog switches.

Even when the number of bits per pixel is increased, each circuit can be easily realized according to the increase in the number of bits.

Next, Table 1 shows a decoder (see FIGS. 11 and 130).
It is a truth table showing the decoding operation of 1).

[0125]

[Table 1]

In Table 1, as for the decoding result of the upper bits, SU3 is valid when D5 and D4 are "11", SU2 is valid when "10", SU1 is valid when "01", and "00". When it is', SU0 is valid.

Further, the decoding result of the lower bits is D3, D2, D1, when the latch clock 201-2 is valid.
SL0 is valid regardless of the value of D0. When the latch clock 201-2 is invalid, D3, D2, D1 and D0 are '
When it is 1111 ', SL15 becomes valid, and' 1110 '
SL14 becomes valid when, and SL when '1101'
13 is valid, SL12 is valid when '1100' and SL11 is valid when '1011'.
When 1010 ', SL10 becomes valid and' 1001 '
SL9 is valid when, and SL8 when '1000'
Is valid, SL7 is valid when '0111', SL6 is valid when '0110', and '010
SL5 is valid when it is 1 and S when it is 0100.
L4 becomes valid, SL3 becomes valid when '0011', SL2 becomes valid when '0010', and '00
When 01 ', SL1 is valid, and when' 0000 ', SL0 is valid.

The operation of the liquid crystal display device according to the first embodiment will be described below.

In FIG. 1, digital display data transferred by the system bus 101 is the liquid crystal controller 102,
Level shifters 110 and 111, signal drive circuits 114 and 1
The voltage is converted into a liquid crystal applied voltage via 15 and the liquid crystal panel 12
It is output to 0 and displayed. In the liquid crystal controller 102, the digital display data input through the system bus 101 is synchronized with the input interfaces of the signal drive circuits 114 and 115 and the pixel configuration of the liquid crystal panel 120 by using a synchronization signal so that the signal drive circuit control bus 106, Output via 107.

Now, in the first embodiment, the drive voltage level of the digital liquid crystal display data transferred by the signal drive circuit control buses 106 and 107 and the signal drive circuit 114,
The drive voltage level of 115 is different.

That is, there is a problem that the liquid crystal deteriorates when a DC voltage is applied. Further, in the first embodiment,
As shown in FIG. 10, by controlling so that the polarities of the voltages applied to the respective pixel units in the horizontal line direction do not match, the deterioration of the image quality due to the inter-line current is prevented. Therefore, the voltage applied to the liquid crystal must be made alternating with a certain period. Note that, as shown in FIG. 9, the liquid crystal has a characteristic of performing the same luminance display as long as the absolute value is the same even when the positive voltage and the negative voltage are applied to the counter voltage VCOM.

On the other hand, since the counter voltage VCOM controlled by the counter electrode line 123 is a direct current voltage, the signal drive circuits 114 and 115 have the signal lines 116 and 11 for this alternating current.
It is necessary to output the voltage in the range of VDU and VDL shown in FIG.

However, the reference voltage of the drain driver 401 is the digital section and the digital-analog conversion circuit 409.
Both must be driven by a common low voltage (VDD-VEE). Therefore, if the reference voltage is fixed, the required liquid crystal applied voltage cannot be supplied to the liquid crystal panel 120.

Therefore, the reference voltage lines 127, 128, 12
9 and 130 are liquid crystal applied voltage VD generated by the signal drive circuits 114 and 115 as shown in the drive waveforms of FIGS.
By alternating to U and VDL, it becomes possible to generate the required voltage level of the liquid crystal applied voltage.

However, since the reference voltage of the signal drive circuits 114 and 115 is changed to AC to change the drive voltage level, it is necessary to change the drive voltage levels of various signals input to the signal drive circuits 114 and 115. There is.

Therefore, the signal drive circuits 114 and 115 are different from the signal drive circuit control bus 106 having a different drive voltage level.
The digital liquid crystal display data and the timing signal transferred at 107 shift the drive voltage level by the level shifters 110 and 111.

In the first embodiment, the digital liquid crystal display data and timing signals transferred by the signal drive circuit control buses 106 and 107 are level shifters 110 and 11.
At 1, the voltages transferred by the reference voltages 129 and 130 are added and output to the signal drive circuit control buses 112 and 113.

Here, the control bus 10 for the signal drive circuit
The digital liquid crystal display data and the timing signal transferred at 6 and 107 are transferred by the level shifters 110 and 111.
The operation until the drive voltage level is shifted and output to the signal drive circuit control buses 112 and 113 will be described in detail with reference to FIGS.

In FIG. 2, the level shifter 110 is provided with adder circuits 201-1 to 201-N for the signal lines transferred by the signal drive circuit control bus 106. In the adder circuit 201, the resistors 203, 204, 205, 20
When the values of 6 are the same, the voltage level appearing at the output 112 is equal to the voltage level represented by the input signal 106 at the reference voltage line 129.
The result is the addition of the voltage levels transferred in.

The state will be described with reference to FIG.

As shown in the figure, by the liquid crystal alternating signal 109, the voltage values of the reference voltage line 129 for the level shifter 110 and the reference voltage line 130 for the level shifter 111 are high potential voltage value VBH and low potential with respect to the voltage VEE. Voltage value V
Only BL has a high value. Therefore, the liquid crystal alternating signal 109
When is "1", shift clock after level shift 11
In 2-1 the voltage value representing "1" is VCC + VBH and the voltage value representing "0" is VEE + VBH. Similarly, when the liquid crystal alternating signal 109 is "0", the shift clock 112-1 after the level shift has a voltage value representing "1" of VCC + VBL and a voltage value representing "0" of VEE.
It becomes + VBL. Shift clock 11 after level shift
2-1 is the voltage difference between the voltage value representing "1" and the voltage value representing "0" is VCC-VEE, which is the voltage value representing "1" and "0" of the input shift clock 106-1. Is the same as the voltage difference.

As described above, the voltage value after the level shift is the voltage VBH, "0" when the liquid crystal alternating signal 109 is "1".
At this time, the voltage VBL is added. Note that FIG.
Since the described latch clock 112-2 and the digital liquid crystal display data 112-2 to 112-N are configured by the same circuit, they operate in the same manner as the shift clock 112-1 and the latch clock 112-2. , Digital liquid crystal display data 112-2 to 112-N will be transferred.

The level shifter 111 shown in FIG. 1 has the same structure as the level shifter 110. However, contrary to the level shifter 110, the voltage value after the level shift is the voltage when the liquid crystal alternating signal 109 is "0". When VBH is '1', the voltage VBL is added.

By the level shifters 110 and 111, the drive voltage levels of the digital liquid crystal display data and the timing signals transferred by the signal drive circuit control buses 112 and 113 and the drive voltage levels of the signal drive circuits 114 and 115 coincide with each other, and the data Can be delivered.

The digital liquid crystal display data and the timing signal which are level-shifted by the level shifters 110 and 111 are input to the signal drive circuits 114 and 115 and converted into liquid crystal applied voltage.

This state will be described with reference to FIG.

In the drain driver 401-1 of FIG. 4, the shift register 403-1 starts its operation by the shift clock 112-1, and the latch signal 404-
Enable 1 The storage circuit in the latch circuit 405-1 corresponding to the validated latch signal 404-1 sequentially latches the digital liquid crystal display data transferred by the display data bus 402. The latched data is the data bus 4
It is output to 06-1.

When the storage circuit in the latch circuit 405-1 completes the data fetch operation, that is, when the shift operation of the shift register 403-1 ends, the shift register 403-1 enables the enable signal 410-1. When the enable signal 410-1 becomes valid, the shift register 403 in the drain driver 401-2 in the next stage
-2 starts operation.

Then, the latch circuit 405-2 sequentially latches the data after being latched by the latch circuit 405-1 in the drain driver 401-1. Further, when the data capturing operation by the storage circuit in the latch circuit 405-2 is completed, the enable signal 410-2 is validated, and the drain driver 401 at the next stage becomes the drain driver 401-.
1 and 401-2.

The respective drain drivers 401 in the signal drive circuits 114 and 115 perform the main operation so that the liquid crystal display data for one horizontal line can be taken in. The latch clock 112-2 becomes valid after the liquid crystal display data for one horizontal line is fetched into the latch circuit 405 in each drain driver 401, and each drain driver 401
Of the data stored in the latch circuit 405 transferred by the data bus 406 of the same circuit for one horizontal line at the same time.
Latched to 7.

After the data is stored in the latch circuit 407, the shift register 40 of each drain driver 401 is
3. The latch circuit 405 starts the same operation as that described above in order to fetch the data of the next line. Latch circuit 4
The data stored in 07 is transferred to the digital-analog conversion circuit 409 via the data bus 408, and the liquid crystal drive voltage transferred in the liquid crystal drive voltage line 132 generates the liquid crystal applied voltage corresponding to the digital data.
It is output at 6.

Next, this digital-analog conversion circuit 40
The operation of generating the liquid crystal applied voltage by 9 is shown in FIG.
This will be described in detail using 1.

In FIG. 11, the data line 408-1-1.
6-bit digital data transferred by the decoder 130
1 is input, and any one of the decode signals SU3 to SU0 is validated according to the values of D5 and D4 of the upper 2-bit data. When the latch clock 112-2 is valid,
The decode signal SL0 is enabled regardless of the values of the lower 4-bit data D3, D2, D1, and D0, and the latch clock 1
When 12-2 is invalid, the lower 4 bits of data D3, D
Depending on the value of 2, D1 and D0, any one of the decode signals SL15 to SL0 is validated.

Here, the operation when the 6-bit digital data transferred by the data line 408-1-1 is "101100" will be specifically described.

In this case, since the upper 2 bits are '10', the decode signal SU2 becomes valid, the analog switch 1303-2 is turned on in the high voltage selection circuit 1302, and the voltage V3 is output to the voltage line 1306. .
Further, in the low voltage selection circuit 1304, the analog switch 1305-2 is turned on, and the voltage V2 is output to the voltage line 1307. The voltages V3 and V2 are the series resistance circuit 13
08, and internal resistors 1309-1 to 1309
The voltage divided by -16 is the voltage line 1310-1 to 1
It is output to 310-15 and 1307.

In the lower bit decoder, since the decode signal SL0 is valid while the latch clock 112-2 is valid, the analog switch 1312-16 is turned on and the voltage V2 transferred on the voltage line 1307 is signaled. Output on line 116-1-1. After that, in the period after the latch clock 210-2 is invalidated, the decode signal SL12 is validated, so that the analog switch 13
12-14 is turned on, and the voltage (V2 + (V3-V2) × 12/16) transferred on the voltage line 1310-4 is output to the signal line 116-1-1. This voltage (V2 +
(V3-V2) x 12/16) is digital data '10
A liquid crystal applied voltage corresponding to 1100 ′.

As described above, switching the voltage to be output between the period in which the latch clock 112-2 is valid and the period in which the latch clock 112-2 is invalid is an effective means for improving the driving capability.
That is, the voltage V2 output during the effective period of the latch clock 112-2 is the analog switch 13 having a low resistance value.
Since it is a voltage that passes through the 05-2 and the analog switch 1312-16, its output impedance has a low value, and a large current can flow, so the driving capability is high. However, the voltage output during the invalid period of the latch clock 112-2 (V2 + (V3-V2) × 12/16)
Is an analog switch 1303-2 having a low resistance value,
1305-2 and series resistance circuit 1308 having high resistance value
Via all resistors 1309-1 to 1309-16 in
Since the voltage is selected by the analog switch 1312-4, its output impedance has a high value.
It cannot pass a large current and its driving ability is low. Assuming that the total resistances 1309-1 to 130 in the series resistance circuit 1308 are
When the resistance value of 9-16 is low, the inflow / outflow current of the liquid crystal drive voltage line 132 is large even when the liquid crystal applied voltage is sufficiently accumulated in each pixel portion 501 in the liquid crystal panel 120, so that the power consumption is reduced. Interfere with Therefore, the present method of driving by dividing the period for generating the liquid crystal applied voltage and the voltage level to be output into two is effective in improving the driving capability.

Further, as in the present embodiment, the liquid crystal drive voltages V4 to V0 are supplied from the outside of the drain driver 401 and a multi-level voltage is internally generated, whereby the reference voltage line 127 of the drain driver 401, 128, 12
Even if some noise or the like is mixed in the reference voltage transferred by 9, 130, if the liquid crystal drive voltages V4 to V0 supplied from the outside are stable, a stable output voltage can be obtained.

In the drain driver 401 shown in FIGS. 4 and 11, the signals controlling the decode signals SL15 to SL0 of the low potential voltage selection circuit 1304 are:
A signal that can be similarly controlled other than the latch clock 112-2 may be used.

Next, the level shifters 110 and 111 and the drain driver 401 transfer the high level reference voltage transferred by the reference voltage line 127 used in such an operation, the high level reference voltage transferred by the reference voltage line 128, and the reference voltage line. Low-level reference voltage transferred by 129, reference voltage line 1
Low level reference voltage transferred by 30 and liquid crystal drive voltage line 1
The liquid crystal drive voltage transferred by 32 and the liquid crystal drive voltage transferred by the liquid crystal drive voltage line 133 will be described with reference to FIGS. 6, 7, and 8.

FIG. 6 shows the level shifter 110 shown in FIG.
111 is an AC circuit that generates a reference voltage for operating 111 and the signal drive circuits 114 and 115. In the first embodiment, the reference voltage line 127 is connected to the voltage selector 607,
By the amplifier circuit 615, the DC voltages VDBHH and VDBLH transferred on the voltage lines 603 and 604 are converted into alternating current according to the liquid crystal alternating current signal 109 and output.

Similarly, as shown in FIG. 6, the reference voltage line 12
9 includes a voltage selector 608 and an amplifier circuit 616,
DC voltage VDBH transferred by voltage lines 605 and 606
L and VDBLL are converted into alternating current according to the liquid crystal alternating current signal 109 and output.

A voltage selector 60 is connected to the reference voltage line 128.
9. The DC voltages VDBHH and VDBLH transferred by the voltage lines 603 and 604 are converted into an alternating current according to the liquid crystal alternating current signal 602 and output by the amplifier circuit 617.

The reference voltage line 130 is connected to the voltage selector 61.
0, by the amplifier circuit 618, the DC voltages VDBHL and VDBLL transferred by the voltage lines 605 and 606 are converted into AC in accordance with the liquid crystal AC conversion signal 602 and output.

This state will be described with reference to FIG.

When the liquid crystal alternating signal 109 is "1", the signal drive circuit 114 shown in FIG. 1 operates with the liquid crystal high level reference voltage value as VDBHH and the low level reference voltage value as VDBHL, and the signal drive circuit 115 has the liquid crystal high level. The level reference voltage value is VDBLH and the low level reference voltage value is VDBL
Operates as L. When the alternating signal 109 is "0", the signal drive circuit 114 shown in FIG. 1 sets the high level reference voltage value to VDBLH and the low level reference voltage value to VDBL.
The signal drive circuit 115 operates as L and the high level reference voltage value is VDBHH and the low level reference voltage value is VDBH.
Operates as L.

In the first embodiment, the reference voltage value VDB
HL is the same value as the voltage value VEE + VBH described in FIG. 3, and the reference voltage value VDBLL is the voltage value VE described in FIG.
It is the same value as E + VBL. In addition, the reference voltage value VDBHH
Is the same value as the voltage value VCC + VBH described in FIG.
The reference voltage value VDBLH is the voltage value VCC + described in FIG.
It is the same value as VBL.

Therefore, the operating voltages of the digital liquid crystal display data and the timing signals transferred by the signal drive circuit control buses 112 and 113 by the level shifters 110 and 111 are the reference voltages 127 and 128 generated by the AC circuit 126.
The drive voltage levels of the signal drive circuits 114 and 115 by 129 and 130 are the same.

Next, the AC circuit 131 for generating the voltage to be transferred by the liquid crystal drive voltage lines 132 and 133 will be described with reference to FIG.

The liquid crystal drive voltage line 132 is connected to the voltage selector 7
05, the DC liquid crystal drive voltage for the signal drive circuit transferred by the DC liquid crystal drive voltage lines 703 and 704 for the signal drive circuit is converted into an alternating current and output through the amplifier circuit 709. The liquid crystal drive voltage line 133 is connected to the voltage selector 706 and the amplifier circuit 7.
DC voltage driving line 70 for signal drive circuit
The DC liquid crystal drive voltage for the signal drive circuit transferred at 3, 704 is converted into an alternating current and output. When the alternating signal 109 is "1", the liquid crystal drive voltage line 132 outputs the voltage to be transferred by the DC liquid crystal drive voltage line 703 for the signal drive circuit. Similarly, when the alternating signal 109 is "0", the signal is output. The voltage to be transferred is output on the DC liquid crystal drive voltage line 704 for the drive circuit.

On the contrary, the liquid crystal drive voltage line 133 outputs the voltage to be transferred by the DC liquid crystal drive voltage line 704 for the signal drive circuit when the alternating signal 109 is "1", and the alternating signal 10
When 9 is “0”, the voltage to be transferred on the DC liquid crystal drive voltage line 703 for the signal drive circuit is output. Therefore, the voltage transferred on the liquid crystal drive voltage lines 132 and 133 is always opposite in polarity to the counter voltage of the counter electrode line 123.

The liquid crystal drive voltage transferred through the liquid crystal drive voltage line 132 is input to the digital-analog conversion circuit 409 of the drain driver 401 shown in FIG. 4, becomes a liquid crystal drive voltage, and is output to the liquid crystal panel 120 via the signal line 116. .

This will be described with reference to FIG. The voltage transferred through the liquid crystal applied voltage lines 132 and 133 is the digital-analog conversion circuit 409 of the drain driver 401 shown in FIG.
To the liquid crystal drive voltage and the signal lines 116 and 11
7 is output to the liquid crystal panel 120. Signal line 11 of FIG.
The voltage range output by 6 is converted to AC when the reference voltages 127 and 129 are changed to AC, and the voltage range output from the signal line 117 is changed to AC when the reference voltages 128 and 130 are changed. Here, when the voltage transferred on the liquid crystal drive voltage lines 132 and 133 is not a voltage value within the operating region of the reference voltage,
The signal driving circuits 114 and 115 do not operate normally, and the voltage required for displaying does not appear on the signal lines 116 and 117.

Next, the liquid crystal applied voltage is generated by the signal drive circuits 114 and 115, and the liquid crystal panel 12 shown in FIG.
How the voltage is applied to 0 will be described.

The level shifters 110 and 111 shown in FIG.
The display data transferred on the system bus 101 is converted into liquid crystal applied voltages by the signal drive circuits 114 and 115, the AC circuit 126, and the AC circuit 131 to become the liquid crystal applied voltages VDU and VDL shown in FIG. When output to 120, the scan drive circuit 118 performs the shift operation by the scan drive circuit control bus 108. The scanning line 119 connected to the horizontal line for applying the liquid crystal applied voltage output from the signal drive circuits 114 and 115 becomes effective. This state will be described in detail with reference to FIG.

The drive waveform of the VDU shown in FIG. 8 is supplied to the signal line 116 from the signal drive circuit 114. Also,
The signal line 117 has VD described in the timing chart of FIG.
The drive waveform of L is supplied from the signal drive circuit 115.

The selection voltage VGH is supplied to the scanning line G (n) for one line period, and then the non-selection voltage VGL is supplied for one frame period.

When the selection voltage VGH of the scanning line G (n) is valid, the TFT 502 of the pixel portion 501 connected to the scanning line G (n) shown in FIG.
The voltage appearing at 16, 117 passes through the TFT 502,
It is stored in the liquid crystal 503 and the load capacitance 504.

Here, as described above, it is necessary to prevent the liquid crystal 503 from deteriorating by alternating the liquid crystal with a certain period. On the other hand, as shown in FIG. 9, the brightness can be changed by the voltage accumulated in the liquid crystal 503. That is,
When a positive potential voltage is applied to the counter electrode 123, the brightness-voltage curve 901 has characteristics, and when a negative potential voltage is applied, the brightness-voltage curve 902 has characteristics. Therefore, the liquid crystal can control the brightness by the effective voltage value regardless of the polarity of the applied voltage.

Therefore, in the first embodiment, in order to prevent the deterioration of the liquid crystal, the polarity of the applied voltage is changed to the alternating voltage VCOM for each frame.

This is to convert the liquid crystal alternating signal 109 into alternating signals for each frame, and as described above, in synchronization with this,
This can be achieved by alternating the voltage values of the digital liquid crystal display data and the timing signal after the level shift by the level shifters 110 and 111, the reference voltage values of the signal drive circuits 114 and 115, and the liquid crystal drive voltage value supplied from the outside.

Further, in the first embodiment, in order to prevent current concentration on the electrode lines, the counter voltage VCOM is set for each adjacent pixel.
On the other hand, the polarity of the voltage applied to the liquid crystal 503 is reversed to drive.

As described above, this corresponds to the signal drive circuits 114 and 11 which are alternately connected to the pixels arranged in one line.
5, digital liquid crystal display data 112 and 113,
This is realized by setting the reference voltages (127, 129), (128, 130) and the liquid crystal drive voltages 132, 133 supplied from the outside to the opposite polarities to the opposite voltage VCOM.

The state of polarity in each pixel due to this applied voltage will be described with reference to FIG. In the second embodiment, the pixel portion driven by the signal line 116 is applied with a positive voltage, and the pixel portion driven by the signal line 117 is applied with a negative voltage.

Pixel portions 501-U (m)-(n) and 501-U (m)-connected to DU (m) of the signal line 116.
, (N + 1), ..., And the pixel units 501-U (m + 1)-(n), 501-U (m + 1) connected to DU (m + 1)
In − (n + 1), ..., The current direction through the liquid crystal 503 flows out toward the counter electrode line 123, and the current direction through the additional capacitor 504 is toward the preceding scanning lines G (n−1) and G (n). leak. Further, the pixel portions 501-L (m)-(n) and 501-L (m)-connected to the DL (m) of the signal line 117.
In (n + 1), ..., The current direction through the liquid crystal 503 flows in from the counter electrode line 123, and the current direction through the additional capacitor 504 flows in from the preceding scanning lines G (n-1) and G (n). .

Therefore, when each pixel portion in the horizontal direction is in the selected state, the counter electrode line 123, the scanning lines G (n-1), G (n).
Since it is possible to control so that the current directions of the pixels are different in the adjacent pixels, it is possible to prevent the current concentration on each electrode. Therefore, since the voltage distortion of the counter electrode line 123 and the scanning line 119 can be reduced, high-quality display can be obtained without changing the liquid crystal applied voltage effective values of the liquid crystal 503 and the additional capacitor 504. Further, in order to prevent the deterioration of the liquid crystal, the polarity of the voltage applied to each pixel portion is reversed in the next frame, but the concentration of current on each electrode can be prevented for the same reason.

The first embodiment of the present invention has been described above.

By the way, the voltage applied to the liquid crystal panel may be made alternating for each line.

This point will be described with reference to FIGS.

FIG. 12 shows a drive voltage waveform supplied to the liquid crystal panel by the line AC drive for switching the polarity of the voltage applied to the liquid crystal for each line.

In the figure, VG (n) is the scanning line G (n) in FIG.
VG (n + 1) is the voltage waveform of the scanning line G (n +
It is a voltage waveform of 1).

FIG. 13 shows the state of the voltage applied to each pixel portion 501 when line AC is performed and the direction of the current generated in the pixel portion at that time.

By the way, in this case, as shown in FIG.
The liquid crystal alternating signal 109 is converted into alternating current with a period of one horizontal period. In addition, the polarity of the liquid crystal alternating signal 109 is
For each frame, control is performed so as to invert for the same horizontal period (scanning period of the same line).

As a result, the voltage selectors 607, 608, 609, 610 in the AC circuit 126 shown in FIG. 6 and the voltage selectors 705, 70 in the AC circuit 131 shown in FIG.
In No. 6, the selection operation is repeated with a cycle of one horizontal period. Therefore, in the signal drive circuit 114, as shown in FIG.
As described in 2, when the scanning line G (n) is in the selected state, that is, the voltage level VGH, the reference voltages 127 and 129 are VDBHH, which are positive potential voltages with respect to the counter voltage VCOM, respectively.
VDBHL, and the counter voltage VCOM is also applied to the signal line 116.
A positive potential voltage is applied to.

When the scanning line G (n + 1) of the next line is in the selected state, the reference voltages 127 and 129 are negative potential voltages VDBLH and VDB with respect to the counter voltage VCOM.
It becomes LL, and a voltage of negative potential with respect to the counter voltage VCOM is also applied to the signal line 116.

In the signal drive circuit 115, when the scanning line G (n) is in the selected state, that is, the voltage level VGH,
The reference voltages 128 and 130 are negative potential voltages VDBLH and VDBLL with respect to the counter voltage VCOM, respectively, and the signal line 117 is also applied with a voltage having a negative potential with respect to the counter voltage VCOM. Then, the scanning line G (n + 1) of the next line
Is in a selected state, the reference voltages 129 and 130 are positive potential voltages VDBHH and VD with respect to the counter voltage VCOM, respectively.
The voltage becomes BHL, and a voltage having a positive potential with respect to the counter voltage VCOM is also applied to the signal line 117.

By such an operation, the polarities of the voltages applied to the pixel portion are reversed for each line. As a result, the polarity of the voltage applied to the liquid crystal pixel portion becomes as shown in FIG.

As shown in the figure, among the pixel units connected to the scanning line G (n), the pixel units 501-U (m)-(n) and DU (connected to the DU (m) of the signal line 116. In the pixel unit 501-U (m + 1)-(n) connected to (m + 1),
The current direction through the liquid crystal 503 flows out in the counter electrode line 123 direction, and the current direction through the additional capacitor 504 flows out in the preceding scanning line G (n-1). Further, D of the signal line 116
Pixel portion 501-L (m)-(n) connected to L (m)
Then, the current direction through the liquid crystal 503 is the counter electrode line 123.
And the current flows through the additional capacitor 504 from the previous scanning line G (n-1).

Further, among the pixel portions connected to the scanning line G (n + 1), the pixel portions 501-U (m)-(n) and DU (m + 1) connected to the DU (m) of the signal line 116 are connected. In the connected pixel portion 501-U (m + 1)-(n), the liquid crystal 5
The current direction via 03 flows from the counter electrode line 123 direction, and the current direction via the additional capacitor 504 is the previous scanning line G.
Inflow from (n). Further, DL of the signal line 116
In the pixel portion 501-L (m)-(n) connected to (m), the current direction via the liquid crystal 503 flows out toward the counter electrode line 123, and the current direction via the additional capacitor 504 is the previous scanning. It flows out to the line G (n).

Therefore, even if the alternating current is applied line by line, the current directions of the counter electrode lines 123, the scanning lines G (n-1), and G (n) are changed when the horizontal pixel portions are in the selected state. Since it can be controlled differently in adjacent pixels, current concentration on each electrode can be prevented, and in the next frame, the polarity of the voltage applied to each pixel portion is reversed, and deterioration of the liquid crystal is prevented. .

The second embodiment of the liquid crystal display device according to the present invention will be described below.

The second embodiment relates to the case of using a single signal drive circuit.

Hereinafter, the second embodiment will be described with reference to FIGS. 14 to 17.
Will be explained.

First, FIG. 14 shows a system configuration of a liquid crystal display device.

In FIG. 14, 1401 is a signal drive circuit, 1402 is a signal line, and 1403 is a liquid crystal panel. In the second embodiment, the signal drive circuit 140
The liquid crystal panel 1 is driven from above the liquid crystal panel 1403. However, it may be driven from below.

Next, FIG. 15 shows the configuration of the signal drive circuit 1401. In FIG.
2, ... Are drain drivers, and the signal drive circuit 14
01 is composed of a plurality of drain drivers 401.

The drain driver 401 has a structure in which digital display data is input, converted into a liquid crystal applied voltage, and output. Odd-numbered drain driver 401-
, 401-3 are driven by using the signal drive circuit control bus 112, and even-numbered drain drivers 401-
, 401-4, ... Are driven by using the signal drive circuit control bus 113. Therefore, the control bus 11 for the signal drive circuit
Shift clock 112-1 and latch clock 11 in 2
2-2, the digital display data bus 402 for transferring the digital display data is an odd-numbered drain driver 401.
, 401-3, ... Further, the shift clock 113-1 in the signal drive circuit control bus 113, the latch clock 113-2, and the digital display data bus 1501 for transferring digital display data include even-numbered drain drivers 401-2, 401-4 ,. Connect to.

Odd-numbered drain drivers 401-1,
, 401-3, ... Convert into liquid crystal applied voltage based on the liquid crystal drive voltage transferred by the liquid crystal drive voltage line 132, and the even-numbered drain drivers 401-2, 401-4 ,.
The liquid crystal drive voltage transferred through the liquid crystal drive voltage line 133 is converted into a liquid crystal applied voltage based on the liquid crystal drive voltage and output to each signal line 1402.

Here, the odd-numbered drain driver 40
, 401-3, ... Use the high-level reference voltage transferred on the reference voltage line 127 and the low-level reference voltage transferred on the reference voltage line 129 as reference voltages, and even-numbered drain drivers 401-2, 401-4, ... are high-level reference voltages transferred by the reference voltage line 128, 1
The low level reference voltage transferred at 30 is used as the reference voltage.

Reference numeral 1502 denotes an enable signal output from the drain driver 401, which is a signal equivalent to the enable signal 410 shown in FIG. A level shifter 1503 shifts the operating voltage level of the enable signal 1502 to the operating region of the next stage drain driver 401-2. The level shifter 1503 is provided between all drain drivers 401. Reference numeral 1504 is a level-shifted enable signal, which is an input signal to the drain driver 401.

Next, FIG. 16 shows an equivalent circuit of the liquid crystal panel 1403.

In FIG. 16, D (1-1), D (1-
2), ..., D (1-k) are drain drivers 401-
1 is a signal line driven by 1, and D (2-1) is a signal line driven by the drain driver 401-2.

Others are the same as the equivalent circuit of the liquid crystal panel according to the first embodiment shown in FIG.

The configurations of the liquid crystal controller 102, the level shifters 110 and 111, the scan drive circuit 118, the DC reference voltage generation circuit 121, the AC circuit 126, and the AC circuit 131 are the same as those in the first embodiment.

The operation of the liquid crystal display device according to the second embodiment will be described below.

In FIG. 14, the digital display data transferred by the system bus 101 is the liquid crystal controller 10
2, level shifters 110 and 111, signal drive circuit 140
1 is converted into a liquid crystal applied voltage through the liquid crystal panel 140.
It is output to 3 and displayed.

At this time, the liquid crystal controller 102 and the level shifters 110 and 111 operate in the same manner as in the first embodiment. Further, the scan drive circuit 118, the DC reference voltage generation circuit 121, the AC circuit 126, and the AC circuit 131 also operate in the same manner as in the first embodiment.

Here, the difference from the first embodiment is that the signal line 140 for supplying the liquid crystal applied voltage to the liquid crystal panel 1403.
2 is drawn out from one side above. That is, the signal drive circuit 1401 is provided on one side of the liquid crystal panel 1403.

Similar to the first embodiment, the drain driver 401 shown in FIG. 15 is driven by a common low voltage for the digital section and the digital-analog conversion circuit 409 for the reference voltage. Therefore, it is necessary to control the voltage applied to the liquid crystal to be alternating with a certain period and to control the polarities of the voltages applied to all the pixel portions in the horizontal line direction not to match.

The voltage applied to the liquid crystal can be converted to alternating current with a certain period by alternating various signals input to the signal drive circuit 1401 including the reference voltage, as in the first embodiment.

On the other hand, regarding the control so that the polarities of the voltages applied to all the pixel portions in the horizontal line direction do not match, in the embodiment shown in FIG. 1, with respect to the counter voltage VCOM transferred by the counter electrode line 123. It is possible to control the lower signal drive driver 115 to operate at the drive voltage level in the negative potential direction when the upper signal drive driver 114 operates at the drive voltage level in the positive potential direction. However, in the first embodiment, since the signal driving circuit 1401 is provided on one side of the liquid crystal panel 1403, the positive polarity positive driving voltage level and the negative polarity driving are performed with respect to the counter voltage VCOM transferred by the counter electrode line 123. Each drain driver 401 is connected to the signal drive circuit 140 so that it operates at the voltage level.
Controlled within 1.

This operation will be described with reference to FIGS. 14 and 15.

In the second embodiment, the signal drive circuit 1401
The plurality of drain drivers 401 included in the drain driver 40 such that the timing of the liquid crystal applied voltage and the drive voltage level generate the voltage VDU shown in FIG.
1 and a drain driver 40 for generating the voltage VDL
It is separated into 1. That is, in the second embodiment,
Odd-numbered drain drivers 401-1 and 401-3,
, Share the signal drive circuit control bus 112, the liquid crystal drive voltage line 132, and the reference voltage lines 127 and 129. on the other hand,
Even-numbered drain drivers 401-2, 401-4,
, Share the signal control circuit control bus 113, the liquid crystal drive voltage line 133, and the reference voltage lines 128 and 130.

Then, for a certain period, the signal drive circuit control bus 112, the liquid crystal drive voltage line 132, the reference voltage line 127,
129 is the counter voltage VCOM transferred by the counter electrode line 123
On the other hand, when it has the positive polarity, the signal drive circuit control bus 113, the liquid crystal drive voltage line 133, the reference voltage line 128, 1
30 is the counter voltage VCOM transferred by the counter electrode line 123.
On the other hand, it may be operated so as to have a negative potential polarity. This is because the odd-numbered drain drivers 401-1, 401-3, ... Of the signal drive circuit 1401 are even-numbered drain drivers 401-2, 401 like the signal drive circuit 114 of the first embodiment. -4, ... Is the same as operating the signal drive circuit 115 of the first embodiment.

Here, the operation of the signal driving circuit 1401 will be described in detail.

The drain driver 401-1 uses the shift clock 112-1 to shift register 403-1.
Starts the operation, sequentially validates the latch signal 404-1, and the storage circuit in the latch circuit 405-1 sequentially latches the digital liquid crystal display data transferred by the display data bus 402.

The latched data is transferred to the data bus 406-
It is output to 1. The shift register 403-1 validates the enable signal 1502-1 when the data capturing operation by the storage circuit in the latch circuit 405-1 is completed, that is, when the shift operation of the shift register 403-1 is completed.

Here, in the first embodiment, all the drain drivers 401 in the signal drive circuit 114 operate at the same drive voltage level, but in the second embodiment, odd-numbered drain drivers 401-1 and 401-3, ..., And even-numbered drain drivers 401-2, 401-4,
..., the output liquid crystal applied voltage is the counter electrode line 12
Since they have different polarities with respect to the counter voltage VCOM of No. 3, the drive voltage level must also be different.

Therefore, the drive voltage level of the enable signal 1502-1 is shifted to the drive voltage level of the drain driver 401-2 of the next stage by the level shifter 1503-1.

Enable signal 1504 after level shift
−1 has a drive voltage level of the drain driver 401.
-2, the enable signal 1504-
1 becomes valid, the internal shift register 403-2 is the same as the drain driver 401-2 of the first embodiment.
Starts to work.

Then, the latch circuit 405-2 sequentially latches the data after being latched by the latch circuit 405-1 in the drain driver 401-1.

Next, when the data fetch operation by the memory circuit in the latch circuit 405-2 is completed, the enable signal 1502-2 is validated, and the drain driver 4 of the next stage is activated.
01 indicates the drive voltage level of the drain driver 401-
Make it the same as 1. Thereafter, the same operation is sequentially performed. When each drain driver 401 in the signal drive circuit 1401 performs this operation, liquid crystal display data for one horizontal line can be fetched.

After that, the latch circuit 407 and the digital-analog conversion circuit 409 further operate in the same manner as in the first embodiment to output the liquid crystal applied voltage to the signal line 1402.

By the way, the internal structure of the liquid crystal panel 1403 according to the second embodiment is the same as that of the liquid crystal panel 1 of the first embodiment.
20 is the same as and different from 20 is the structure in which the signal line 1402 is drawn from one side of the panel as described above. Therefore, the liquid crystal panel 14
The state in which a voltage is applied to each pixel unit 501 inside the 03
This is the same as the first embodiment.

However, as described above, in the second embodiment, the odd-numbered drain drivers 401-1 and
401-3, ... And even-numbered drain drivers 401-
2, 402-4, ... Operate with opposite polarities with respect to the counter electrode voltage VCOM. Therefore, the liquid crystal applied voltage VDU shown in FIG.
, 401-3, ..., The liquid crystal applied voltage VDL is an even-numbered drain driver 401-2, 4-4.
02-4, ... Are voltages output.

Here, in the first embodiment described above, FIG.
In the case of performing the line alternating current shown by using, the counter electrode voltage V
The polarity of the voltage applied to the pixel portion with respect to COM is shown in FIG.
As shown in 7. . In the figure, + indicates that a positive potential is applied, and − indicates that a negative potential is applied.

That is, of the signal lines 1502, the signal line controlled by the drain driver 401-1 is D (1-1),
D (1-2), ..., D (1-k) (where k is a natural number and the number of signal lines controlled by the drain driver 401), and the signal line controlled by the drain driver 401-2 is D. (2-1), D (2-2), ..., D (2-k)
Then, in an even frame, a positive voltage is applied to the horizontal line controlled by the scanning line G (1) and the pixel portion controlled by the drain driver 401-1. A negative voltage is applied to the pixel portion controlled by -2. Similarly, the other odd-numbered drain drivers 401-3, 401-5,
A positive voltage is applied to the pixel unit controlled by ..., Even-numbered drain drivers 401-4, 401-6 ,.
A negative voltage is applied to the pixel portion controlled by.

Odd-numbered drain drivers 401-1 and 401- in the horizontal line controlled by the scanning line G (2).
A negative voltage is applied to the pixel portion controlled by 3, ..., And even-numbered drain drivers 401-2, 401-
A positive voltage is applied to the pixel unit controlled by 4, ...

In addition, the voltage polarity applied to each pixel portion in the odd-numbered frame is opposite to the voltage polarity applied to each pixel portion in the even-numbered frame. By repeating the voltage polarities applied in the even frame and the odd frame, deterioration of the liquid crystal is prevented.

As described above, also in the second embodiment, when each pixel portion in the horizontal direction is in the selected state, the current directions of the counter electrode 123, the scanning lines G (1), G (2), etc. are odd-numbered. , And the even-numbered drain drivers 401-2, 401-4, ... Can be controlled differently from each other in the pixel portion controlled by the drain drivers 401-1, 401-3 ,.
It is possible to prevent current concentration on each electrode.

Therefore, as in the first embodiment, since the voltage distortion of the counter electrode line 123 and the scanning line 119 can be reduced, the liquid crystal applied voltage effective value of the liquid crystal 503 and the additional capacitor 504 does not fluctuate and is high. A quality display can be obtained. Further, deterioration of the liquid crystal can be prevented.

The third embodiment of the liquid crystal display device according to the present invention will be described below.

First, FIG. 18 shows a block diagram of a liquid crystal display device according to the third embodiment.

In FIG. 18, reference numerals 1801 and 1802 denote signal drive circuits, which are the signal drive circuit control buses 112 and 180, respectively.
The digital liquid crystal display data transferred at 113 is fetched by a timing signal and converted into a liquid crystal applied voltage corresponding to the digital liquid crystal display data. Signal lines 1803 and 1804 transfer the liquid crystal applied voltages generated by the signal drive circuits 1801 and 1802, respectively. Reference numeral 1805 denotes a reference DC voltage generating circuit, which generates various DC voltages serving as a reference for operating the liquid crystal display device of the third embodiment. 18
Reference numeral 06 is a DC reference voltage line for a signal drive circuit. 1807
Is an AC circuit. 1808 is the upper signal drive circuit 18
01 is a reference voltage line for transferring a liquid crystal drive unit reference voltage, and similarly, 1809 is a reference voltage line for transferring a liquid crystal drive unit reference voltage for driving the lower signal drive circuit 1802.

Next, FIG. 19 shows the configuration of the signal drive circuit 1801. The signal drive circuit 1802 on the lower side of the liquid crystal panel 120 has the same configuration.

In FIG. 19, 1901-1 and 1901
-, ... Are drain drivers, and the signal drive circuit 1
Reference numeral 801 includes a plurality of drain drivers 1901. The drain driver 1901 inputs digital display data, converts it into a liquid crystal applied voltage, and outputs it.

Four of the signal drive circuit control buses 112
Reference numeral 02 is a liquid crystal display data bus. Further, 201-1 is a shift clock, and 201-2 is a latch clock. The shift clock 201-1 operates in synchronization with the digital liquid crystal display data transferred by the liquid crystal display data bus 402. In the latch clock 201-2, the digital liquid crystal display data for one horizontal line is the signal drive circuits 1801 and 18
It becomes valid after being transferred to 02. A level shifter 1902 converts the voltage amplitude level of the digital data transferred by the data bus 408. Reference numeral 1903 is a data bus for transferring the converted digital data.

Reference numeral 1904 denotes a digital-analog conversion circuit, which converts the digital data transferred by the data bus 1903 into a liquid crystal applied voltage based on the AC voltage transferred by the AC liquid crystal applied voltage line 132 serving as a reference. 1803
Is a signal line, and transfers the liquid crystal applied voltage generated by the digital-analog conversion circuit 1904.

In the drain driver 1901, the shift register 403, the latch circuit 405, and the latch circuit 40.
The digital circuit unit 7 is driven by the high-level reference voltage transferred by the reference voltage line 127 and the low-level reference voltage transferred by the reference voltage line 129, and the level shifter 1902 and the digital-analog conversion circuit 1904 are driven by the high-level reference voltage transferred by the reference voltage line 127. The liquid crystal drive unit is driven by the reference voltage and the reference voltage of the liquid crystal driving unit transferred by the reference voltage line 1808.

Next, FIG. 20 shows the configuration of the AC circuit 1807. In FIG. 20, 2001 and 2002 are both DC voltage lines in the DC reference voltage line 1806 for the signal drive circuit. Transfers the DC voltage that serves as the reference for the output AC voltage.

Reference numerals 2003 and 2004 denote voltage selectors, which convert the input DC voltage into AC. 2005,
Reference numeral 2006 is a voltage line that transfers the AC voltage output from the voltage selectors 2003 and 2004, respectively. 2007, 20
Reference numeral 08 denotes an amplifier circuit, which are voltage selectors 2003 and 2 respectively.
It serves to enhance the driving ability of the AC voltage output by 004.

The liquid crystal controller 102, the level shifters 110 and 111, the scan drive circuit 118, the AC circuit 1
The configuration of 31 is the same as that of the first embodiment.

The operation of the liquid crystal display device according to the third embodiment will be described below.

In FIG. 18, the digital display data transferred by the system bus 101 is the liquid crystal controller 10
2, level shifters 110 and 111, signal drive circuit 180
1 is converted to a liquid crystal applied voltage via the liquid crystal panel 120.
Is output to and displayed. At this time, the liquid crystal controller 1
02, level shifters 110 and 111, scan drive circuit 11
8. The AC circuit 131 operates similarly to the first embodiment.

The third embodiment is different from the first embodiment in that the signal drive circuit 1801 shown in FIG.
The drain driver 1901 described is different from the drain driver (401 in FIG. 4) of the first embodiment.
That is, the drain driver 401 according to the first embodiment.
In the above, all of the shift register 403, the latch circuit 405, the digital circuit portion of the latch circuit 407, and the digital-analog conversion circuit 409 operate at the common reference voltage. However, in the drain driver 1901 of the third embodiment, the digital circuit Section and the digital-analog converter circuit 1904 operate with different reference voltages.

Therefore, in the third embodiment, the configurations of the reference DC voltage generation circuit 1805 and the AC circuit 1807 for supplying the reference voltage to the signal drive circuit 1801 are the same as the reference DC voltage generation circuit 121 and the AC circuit 126. Is different.

The signal drive circuit 1801 is composed of a plurality of drain drivers 1901. However, the shift register 403, the latch circuit 405, the latch circuit 4
07 operates with the low level reference voltage transferred by the reference voltage line 127 and the high level reference voltage transferred by the reference voltage line 129. This operation is similar to that of the first embodiment.

On the other hand, the digital-analog conversion circuit 1904 for generating the liquid crystal applied voltage operates by the low level reference voltage transferred by the reference voltage line 127 and the liquid crystal drive unit reference voltage transferred by the reference voltage line 1808. That is, in the drain driver 1901 of the third embodiment, the driving voltage of the digital section and the digital-analog conversion circuit 1904 are different.
Therefore, the level shift circuit 1 that performs voltage conversion during this period
It is necessary to provide 902.

The level shift circuit 1902 voltage-converts the data latched by the latch circuit 407 and transferred by the data line 408, and the voltage-converted data is converted into the data line 1903.
To the digital-analog conversion circuit 1904 via the. In the digital-analog conversion circuit 1904, the first
Similar to the digital-analog conversion circuit 409 according to the embodiment, the liquid crystal drive voltage transferred by the liquid crystal drive voltage line 132 generates a liquid crystal applied voltage corresponding to digital data and outputs it to the signal line 1803. This operation is similar to that of the first embodiment.

Next, an AC circuit 180 for generating a reference voltage
7 will be described.

In FIG. 20, in the AC circuit 1807, the circuit for generating the AC reference voltage transferred by the reference voltage lines 127, 128, 129 and 130 is the same as that of the first embodiment.

However, in the third embodiment, the reference voltage line 1
It is necessary to generate a liquid crystal drive unit reference voltage to be transferred at 808 and 1809.

The AC-converted liquid crystal drive unit reference voltage transferred by the reference voltage line 1808 is generated by the voltage selector 2003 and the amplifier circuit 2007, and the AC-converted reference voltage transferred by the reference voltage line 1809 is the voltage selector 2004. And the amplifier circuit 2008. At this time, when the liquid crystal alternating signal 109 is “1”, the voltage transferred on the reference voltage line 1808 is the voltage transferred on the signal drive circuit reference voltage line 2001, and the voltage transferred on the reference voltage line 1809. Becomes the voltage transferred on the signal drive circuit reference voltage line 2002.

When the liquid crystal alternating signal 109 is “0”, the voltage transferred on the reference voltage line 1808 is the voltage transferred on the signal drive circuit reference voltage line 2002 and transferred on the reference voltage line 1809. Voltage becomes a voltage transferred on the reference voltage line 2001 for the signal drive circuit.

Therefore, the voltage transferred on the reference voltage line 1808 is in phase with the voltage transferred on the reference voltage lines 127 and 129, and the voltage transferred on the reference voltage line 1809 is the same voltage as the voltage transferred on the reference voltage lines 128 and 130. Can be in phase. Accordingly, if the DC voltages 2001 and 2002 are appropriately set, the liquid crystal driving voltage transferred by the liquid crystal driving voltage lines 132 and 133 is within the driving voltage level of the liquid crystal driving unit reference voltage transferred by the reference voltage lines 1808 and 1809. Will be things.

By using the AC circuit 1807 in this way, the same drive as in the embodiment shown in FIG. 1 can be performed by the signal drive circuit 18.
01 and 1802 can be used.

Here, the internal structure of the liquid crystal panel 120 is as follows.
Similar to the first embodiment, the signal drive circuit 1801,
Since the configuration of 1802 is also provided above and below the liquid crystal panel 120, the drive waveform of the liquid crystal applied voltage is similar to the drive waveform of the first embodiment (FIGS. 8 and 12), and digital-analog conversion is performed. Since the high level drive voltage of the circuit 1904 is the liquid crystal drive unit reference voltage transferred by the reference voltage lines 1808 and 1809, the reference voltage line 129 of FIGS.
The waveform represented by is the waveform represented by the reference voltage line 1808,
The waveform represented by the reference voltage line 130 is the waveform represented by the reference voltage line 1809.

Therefore, the same driving as that of the embodiment shown in FIG. 1 can be realized.

Therefore, since a voltage is applied to the liquid crystal panel 120 as in the first embodiment, a high quality display can be performed. The drain driver 1901 forming the third signal drive circuit may be used in the second embodiment.

The fourth embodiment of the liquid crystal display device according to the present invention will be described below.

The present embodiment relates to the case where the input display data is an analog value.

FIG. 21 shows the structure of the liquid crystal display device according to the fourth embodiment.

In FIG. 21, reference numeral 2101 denotes a system bus, which transfers analog display data and a synchronizing signal. In this embodiment, the display data and the synchronizing signal transferred by the system bus 2101 are signals for line sequential scanning which are compliant with the display data and the synchronizing signal transferred for displaying the CRT display device.

Reference numeral 2102 denotes a liquid crystal controller, which converts the analog display data and the synchronizing signal transferred by the system bus 2101 into the analog liquid crystal display data and the timing signal for driving the liquid crystal display device.

Reference numerals 2103 and 2104 are signal drive circuit control buses, both of which are controlled by the liquid crystal controller 2102.
The converted analog liquid crystal display data and timing signal for the signal drive circuit are transferred. Reference numerals 2105 and 2106 are polarity inversion circuits, and 2107 and 2108 are signal drive circuit control buses that transfer the analog display data and the synchronization signal after the polarity inversion. Reference numerals 2109 and 2110 denote level shifters, which shift the voltage levels of the analog liquid crystal display data and the timing signal transferred by the signal drive circuit control buses 2107 and 2108, respectively, to the operation area of the signal drive circuit. 21
Reference numerals 11 and 2112 denote signal drive circuit control buses, which transfer the analog liquid crystal display data and the timing signals whose voltage levels have been converted by the level shifters 2109 and 2110. Two
Reference numerals 113 and 2114 denote signal drive circuits, which take in analog liquid crystal display data transferred by the signal drive circuit control buses 2111 and 2112, respectively, by a timing signal and convert the data into liquid crystal applied voltage. 2115 and 2116 are signal lines, which transfer the liquid crystal applied voltage generated by the signal drive circuits 2113 and 2114, respectively. Reference numeral 2117 is a DC reference voltage generation circuit, which generates various DC voltages serving as a reference for operating the present liquid crystal display device.

Next, FIG. 22 shows the configuration of the signal drive circuit 2113.

The signal drive circuit 2114 on the lower side of the liquid crystal panel 120 has the same structure.

In FIG. 22, 2201-1, 2201.
-, ... Are drain drivers, and the signal drive circuit 2
Reference numeral 113 is composed of a plurality of drain drivers 2201.
The drain driver 2201 has a configuration in which analog display data is input, liquid crystal applied voltage is applied, and output.
2202 is a shift clock, and 2203 is a latch clock. The shift clock 2202 is synchronized with the digital liquid crystal display data transferred by the liquid crystal display data bus 2204, and the latch clock 2203 is the analog liquid crystal display data for one horizontal line, which is the signal drive circuit 2113, 2.
After being transferred to 114, it becomes valid. Reference numeral 2204 is a liquid crystal display data bus for transferring analog display data. Two
Reference numeral 205 is a shift register, and 2206 is a latch signal. The shift register 2205 has a shift clock 22.
02 is input to perform the shift operation. By this shift operation, the latch signal 2206 becomes sequentially valid. 220
Reference numeral 7 is a sample circuit, which latches the analog liquid crystal display data transferred by the liquid crystal display data bus 402 into a latch signal 2
Sequentially latch by 206. A data bus 2208 transfers the data sampled by the sampling circuit 2207. Reference numeral 2209 denotes a hold circuit that latches the data transferred on the data bus 2208 with the latch clock 22.
In 03, the signals are simultaneously captured and held, and are transferred as a liquid crystal applied voltage by the signal line 2215. 2210 is an enable signal, which operates in the same manner as the enable signal 410 of the first embodiment. In the drain driver 2201, all of the shift register 2205, the sample circuit 2207, and the hold circuit 2209 are driven by the high-level reference voltage transferred by the reference voltage line 127 and the low-level reference voltage transferred by the reference voltage line 129.

The operation of the station layer display device according to the fourth embodiment will be described below.

In FIG. 21, the analog display data transferred by the system bus 2101 is the liquid crystal controller 2
102, polarity inversion circuits 2105 and 2106, level shifters 2109 and 2110, signal drive circuits 2113 and 211
4 is converted into a liquid crystal applied voltage via the liquid crystal panel 120.
Is output to and displayed. In the liquid crystal controller 2102, analog display data input by the system bus 2101 is converted into a signal drive circuit 2113, 2114 by a synchronous signal according to the input interface and the pixel configuration of the liquid crystal panel 120, and the signal drive circuit control bus 2103, 2104.
Output via.

Here, the control bus 210 for the signal drive circuit
3, the driving voltage levels of the analog data and the timing signal transferred in 2104, and the signal driving circuits 2113 and 211
There is a problem that the drive voltage levels of 4 are different.

Further, the signal drive circuit 2113 of this embodiment,
Reference numeral 2114 has a configuration in which analog display data is sampled and the voltage held therein is output as a liquid crystal applied voltage.

On the other hand, the liquid crystal, with respect to the counter voltage VCOM,
It has a characteristic that the luminance is high at low potential voltage and is low at high potential voltage regardless of polarity.

Therefore, the polarity of the analog display data having the luminance information is transferred in accordance with the liquid crystal alternating signal 109 by the voltage of only the positive polarity to be transferred. In addition, the level shifter shifts the voltage level to the corresponding operation area of the signal drive circuit. The level-converted analog display data and timing signals are used for the signal drive circuit control buses 2111 and 211.
2 is input to the signal drive circuits 2113 and 2114, respectively.

The signal drive circuits 2113 and 2114 convert the signal drive control buses 2111 and 2112 into liquid crystal applied voltages. This situation will be described with reference to FIG.

In FIG. 22, the drain driver 220
1-1, the shift register 2205-1 starts its operation by the shift clock 2202, and the latch signal 22
Enable 06-1. Latch signal 220 enabled
The storage circuit in the latch circuit 2207-1 corresponding to 6-1 sequentially latches the analog liquid crystal display data transferred by the display data bus 2204. The latched analog data is output to the data bus 2208-1. When the data capturing operation by the storage circuit in the latch circuit 2207-1 is completed, that is, the shift register 2205-
When the shift operation of 1 is completed, the shift register 2205-
1 enables the enable signal 2210-1. When the enable signal 2210-1 becomes valid and valid, the shift register 2205 in the drain driver 2201-2 at the next stage is activated.
-2 starts operation.

The latch circuit 2207-1 is the latch circuit 2207-1 in the drain driver 2201-1.
The data after being latched by is sequentially latched. When the storage circuit in the latch circuit 2207-2 finishes the data fetching operation, the enable signal 2210-2 is validated, and the drain driver 2201 at the next stage operates similarly to the drain drivers 2201-1 and 2201-2. .
When each drain driver in the signal drive circuit performs this operation, analog liquid crystal display data for one horizontal line can be taken in.

The latch clock 2203 becomes valid after the liquid crystal display data for one horizontal line is fetched by the latch circuit 2207 in each drain driver 2201 and stored in the latch circuit 2207 transferred by the data bus 2208 of each drain driver 2201. The generated data is stored in the latch circuit 2209 in the same manner for one horizontal line.

After the data is stored in the latch circuit 2209, the shift register 2 of each drain driver 2201 is
205 and the latch circuit 2207 repeat the same operation in order to fetch the data of the next line.

The latch circuit 2209 has an amplifier circuit inside, and improves the driving capability of the latched analog data and outputs it as a liquid crystal applied voltage to the signal line 2115.

In the fourth embodiment, the internal structure of the liquid crystal panel 120 is the same as that of the first embodiment, and the signal drive circuits 2113 and 2114 are also configured as the liquid crystal panel 12.
Since it is configured above and below 0, the drive waveform of the liquid crystal applied voltage and the like are the same as in the first embodiment (FIGS. 8 and 11).

That is, the same drive as in the first embodiment can be realized by using the signal drive circuits 2113 and 2114.
Therefore, a high quality display can be obtained.

The drain driver 2201 according to the present embodiment may be applied to the liquid crystal display device in which the signal line of the liquid crystal panel according to the second embodiment is drawn from either the upper side or the lower side.

The embodiments of the liquid crystal display device according to the present invention have been described above. As described above, according to this embodiment, it is possible to realize a high quality display by using the low withstand voltage drain driver.

Finally, the paths of the respective voltages are shown in FIG. 24, taking the first embodiment as an example. In FIG. 24, reference numeral 3301 is a drain driver that constitutes the lower signal drive circuit 115. As shown in this figure, the AC circuit 126 performs a switching operation in synchronization with the liquid crystal alternating signal 109, whereby the level shifters 110 and 11 are switched.
1. The voltages 127 to 130 used by the drain driver 401 forming the upper signal drive circuit 114 and the drain driver 3301 forming the lower signal drive circuit 115 are made alternating.

Next, an information doctor apparatus using the liquid crystal display device according to the first, second and third embodiments will be described.

FIG. 24 shows the structure of this information processing apparatus. .

In FIG. 23, 2301 is a main body of an information processing apparatus such as a personal computer, and 2302 is a liquid crystal display device of the present invention. 2303 is a central processing unit, 2304 is a main memory, and 2305 is a system bus. 2306 is a display controller, 2307 is a display memory, and 2308 is a display bus. A system bus 2309 transfers display data and a synchronization signal.

The central processing unit 2303 has a main memory 23.
The program stored in 04 is read out, arithmetic processing is performed, and the system bus 2305 and display controller 2306 are executed.
The display data is written to the display memory 2307 via the. The display controller 2306 reads the display data stored in the display memory 2307, outputs the read display data and the synchronization signal to the liquid crystal display device 2302 via the system bus 2309, and performs display.

The structure of the liquid crystal display device according to this example will be described below.

FIG. 25 is a plan view showing one pixel and its periphery of an active matrix type liquid crystal panel using thin film TFTs according to this embodiment, and FIG.
The figure which shows the cross section in a cutting line, FIG. 27 is 4-4 of FIG.
It is sectional drawing in a cutting line.

As shown in FIG. 25, each pixel has two adjacent pixels.
Scanning signal lines (gate signal lines or horizontal signal lines) GL
And an adjacent two video signal lines (drain signal line or vertical signal line) DL are intersected with each other (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction. Video signal line DL
Extend in the up-down direction and are arranged in the left-right direction.

As shown in FIG. 26, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with the liquid crystal layer LC as a reference, and a color filter FIL, and a color filter FIL are formed on the upper transparent glass substrate SUB2 side.
A black matrix pattern BM for shading is formed. Silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2.

On the inner (liquid crystal LC side) surface of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

<< Outline of Matrix Periphery >> FIG. 28 shows a display panel PNL including upper and lower glass substrates SUB1 and SUB2.
29 is a plane in which the peripheral portion is further exaggerated, and FIG. 30 is a plan view in FIG. 28 and FIG.
7 is a diagram showing an enlarged plane near the seal portion SL corresponding to the upper left corner of the panel of FIG. Further, FIG. 31 is a diagram showing a cross section taken along a cutting line 8a-8a in FIG. 39 on the left side and a cross section near the external connection terminal DTM to which the video signal drive circuit is to be connected on the right side with the cross section of FIG. is there. Similarly, FIG.
Is an external connection terminal GT to which the scanning circuit should be connected on the left side.
It is a figure which shows the cross section near M, and the cross section near the seal part where there is no external connection terminal on the right side.

[0306] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared In each type of product, a standardized glass substrate is processed, and then the size is reduced to a size suitable for each product. In each case, the glass is cut after going through one step. 28 to 39 show an example of the latter case. In both of FIGS. 28 and 29, the upper and lower substrates SUB are shown.
FIG. 39 shows the state after cutting the substrates 1 and SUB2, and FIG. 39 shows the state before cutting, LN indicates the edges of the substrates before cutting, and CT1 and CT2 indicate the positions where the substrates SUB1 and SUB2 should be cut. In either case, in the completed state, the external connection terminal group T
g and Td (subscript omitted) exist (upper side and left side in the figure)
The upper substrate SUB2 is limited in size to the inside of the lower substrate SUB1 so as to expose them. The terminal groups Tg and Td are respectively those of the scanning circuit connection terminal GTM and the video signal circuit connection terminal DTM, which will be described later, and the lead wiring portions thereof of the tape carrier package TCP (FIG. 47, FIG. 48) in which the integrated circuit chip CHI is mounted. This is the name given to multiple units collectively. The lead wiring from the matrix portion of each group to the external connection terminal portion is inclined toward both ends. This is to match the terminals DTM and GTM of the display panel PNL with the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.

A liquid crystal LC is provided between the transparent glass substrates SUB1 and SUB2 along the edge thereof except for the liquid crystal sealing port INJ.
A seal pattern SL is formed so as to seal the. The sealing material is made of epoxy resin, for example. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to at least one of the lead wirings INT formed on the lower transparent glass substrate SUB1 side by the silver paste material AGP at four corners of the panel in this embodiment. ing. The lead wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.

The orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2, and their respective layers are formed inside the seal pattern SL. Polarizing plate P
OL1 and POL2 are lower transparent glass substrates SUB, respectively.
1. Formed on the outer surface of the upper transparent glass substrate SUB2. The liquid crystal LC is enclosed in a region partitioned by a seal pattern SL between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules. The lower alignment film ORI1 is a protective film P on the lower transparent glass substrate SUB1 side.
It is formed on top of SV1.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and the seal pattern SL is applied to the substrate SUB2.
Formed on the side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, the liquid crystal LC is injected from the opening INJ of the sealing material SL, and the injection port INJ is sealed with epoxy resin or the like to form the upper and lower substrates. It is assembled by cutting.

<< Thin Film Transistor TFT >> Next, referring to FIG.
5, the configuration on the TFT substrate SUB1 side will be described in detail. In the thin film transistor TFT, when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is set to zero,
The channel resistance operates so as to increase.

A plurality (two) of thin film transistors TFT1 and TFT2 are redundantly provided in each pixel. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same), and has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic,
intrinsic, conductivity type determination impurities are not doped)
It has an i-type semiconductor layer AS made of amorphous silicon (Si), a pair of source electrodes SD1 and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

<< Gate Electrode GT >> The gate electrode GT has a shape protruding in the vertical direction from the scanning signal line GL (branched into a T shape). The gate electrode GT projects so as to extend beyond the respective active regions of the thin film transistors TFT1 and TFT2. Thin film transistor TFT
The gate electrodes GT of the TFT 1 and the TFT 2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of the single-layer second conductive film g2. An aluminum (Al) film formed by sputtering, for example, is used as the second conductive film g2, and an Al anodic oxide film AOF is provided thereon.

The gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below), and is devised so that the i-type semiconductor layer AS is not exposed to outside light or backlight light. .

<< Scanning Signal Line GL >> The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Also, an Al anodic oxide film AOF is provided on the scanning signal line GL.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected and is formed to a thickness of 1200 to 2700Å (in this embodiment, about 2000Å). As shown in FIG. 39, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. The insulating film GI also contributes to the electrical insulation between the scanning signal line GL and the video signal line DL.

<< i-Type Semiconductor Layer AS >> i-Type Semiconductor Layer AS
In this example, each of the thin film transistors TFT1 and TFT2 is formed as an independent island, and is made of amorphous silicon and has a thickness of 200 to 2200Å (2 in this example.
The film thickness is about 000Å). The layer d0 is a phosphorus (P) -doped N (+)-type amorphous silicon semiconductor layer for ohmic contact, the i-type semiconductor layer AS exists on the lower side, and the conductive layer d2 (d3) exists on the upper side. It is left only where you do.

The i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

<< Transparent Pixel Electrode ITO1 >> Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to both source electrodes SD1 of FT2. Therefore, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by laser light or the like, and if not, the other thin film transistor operates normally. You can leave it alone because it does. The transparent pixel electrode ITO1 is composed of the first conductive film d1.
Is a transparent conductive film (Indium-Tin) formed by sputtering.
-Oxide ITO: Nesa film), 1000-200
With a thickness of 0Å (in this embodiment, a film thickness of about 1400Å)
It is formed.

<< Source Electrode SD1, Drain Electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is composed of a second conductive film d2 in contact with the N (+) type semiconductor layer d0 and a third conductive film d3 formed thereon.

The second conductive film d2 is a chromium (Cr) film formed by sputtering and is formed to a thickness of 500 to 1000 Å (in this embodiment, about 600 Å). If the Cr film is formed thicker, the stress increases.
It is formed within a range not exceeding the film thickness of 0Å. Cr film is N
It is used for the purpose of improving adhesion to the (+) type semiconductor layer d0 and preventing Al of the third conductive film d3 from diffusing into the N (+) type semiconductor layer d0 (so-called barrier layer). Second
As the conductive film d2, in addition to the Cr film, refractory metal (Mo, T
i, Ta, W) film, refractory metal silicide (MoS
An i ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The third conductive film d3 is formed by sputtering Al to a thickness of 3000 to 5000 Å (400 in this embodiment).
0 Å) formed. The Al film has less stress than the Cr film and can be formed to have a large film thickness, and the source electrode SD1, the drain electrode SD2 and the video signal line DL can be formed.
Of the gate electrode GT and the i-type semiconductor layer AS are ensured (step coverage is improved).

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as masks. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

<Video Signal Line DL> The video signal line DL is composed of the second conductive film d2 and the third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2.

<< Protective Film PSV1 >> Thin Film Transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

As shown in FIG. 39, the protective film PSV1 is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM.
In addition, the common electrode COM of the upper substrate SUB2 is connected to the lower substrate SU.
The portion connected to the lead wire INT for external connection terminal connection of B1 with the silver paste AGP is also removed. Protective film PSV
Regarding the thickness relationship between 1 and the gate insulating film GI, the former is made thicker in consideration of the protection effect, and the latter is made thin in the transconductance gm of the transistor. Therefore, as shown in FIG. 39, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, external light or backlight is exposed to the i-type semiconductor layer A.
A light shielding film BM is provided so as not to enter S. Figure 2
The closed polygonal contour line of the light-shielding film BM shown in 5 indicates an opening inside which the light-shielding film BM is not formed. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300Å.

Therefore, the thin film transistors TFT1 and TF
The i-type semiconductor layer AS of T2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT,
External natural light or backlight does not hit. The light-shielding film BM is formed in a lattice shape around each pixel (so-called black matrix), and the effective display area of one pixel is partitioned by this lattice. Therefore, the outline of each pixel is the light-shielding film BM.
Improves clarity and contrast. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Since the edge portion (lower right portion in FIG. 25) on the root side of the transparent pixel electrode ITO1 in the rubbing direction is also shielded from light by the light shielding film BM, even if a domain is generated in the above portion, the domain cannot be seen. The display characteristics do not deteriorate.

As shown in FIG. 29, the light-shielding film BM is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. 25 in which a plurality of dots-like openings are provided. There is. The light shielding film BM in the peripheral portion is shown in FIG.
As shown in FIG. 32, extended to the outside of the seal portion SL,
This prevents leaked light such as reflected light from a mounting machine such as a personal computer from entering the matrix section. On the other hand, the light-shielding film BM is retained inside about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green and blue at positions facing the pixels. The color filter FIL is formed to have a large size so as to cover all of the transparent pixel electrode ITO1, and the light shielding film BM overlaps with the edge portions of the color filter FIL and the transparent pixel electrode ITO1.
It is formed inside the peripheral portion of TO1.

The color filter FIL can be formed as follows. First, a dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

<< Protective Film PSV2 >> The protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

<< Common Transparent Pixel Electrode ITO2 >> The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this embodiment, the common voltage Vcom is the minimum level drive voltage Vdmin and the maximum level drive voltage V applied to the video signal line DL.
It is set to an intermediate DC potential with respect to dmax. 28 and 29 for the planar shape of the common transparent pixel electrode ITO2.

<< Structure of Storage Capacitance Element Cadd >> The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. This overlay is shown in FIG.
As is clear from the above, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode P2.
A holding capacitance element (electrostatic capacitance element) Cadd that is L1 is configured. The dielectric film of the storage capacitor element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodized film AOF.

The storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL.

Even if the transparent pixel electrode ITO1 is broken at the step portion of the electrode PL1 of the storage capacitor Cadd, the second conductive film d2 and the third conductive film d2 formed so as to cross the step.
The defect is compensated by the island region formed of the conductive film d3.

<Gate Terminal Section> FIG. 33 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM. (A) is a plane and (B) is B of (A). -B shows a cross section taken along the line B. Note that the same drawing corresponds to the lower part of FIG. 30, and the diagonal wiring portions are shown in a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodization,
The pattern AO shown in the figure does not remain as a finished product, but since the oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view, its locus remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized. Anodized A
The oxide Al ₂ O ₃ film AOF is formed on the surface of the L layer g2, and the volume of the conductive portion therebelow is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect with the scanning line GL by a single straight line, but is bent in a crank shape and intersects.

In the figure, the AL layer g2 is hatched for easy understanding, but the region which is not anodized is patterned in a comb shape. This is because whiskers are generated on the surface when the width of the Al layer is wide. Therefore, by narrowing the width of each one and arranging a plurality of them in parallel, whiskers can be prevented and wire breakage can be prevented. The aim is to minimize the probability of and the sacrifice of conductivity. Therefore, in this example, the portion corresponding to the base of the comb is also displaced along the mask AO.

The gate terminal GTM is a Cr layer g1 having a good adhesiveness to the silicon oxide SIO layer and a higher electric contact resistance than Al or the like.
Further, the surface thereof is protected and is composed of a transparent conductive layer d1 of the same level (same layer, simultaneously formed) as the pixel electrode ITO1.
In addition, the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have their regions so that the conductive layers g2 and g1 are not etched together due to pinholes or the like during the etching of the conductive layers d3 and d2. It remains as a result of being covered with photoresist. In addition, the ITO layer d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the terminal portion GTM located at the left end is formed.
Are exposed from them to allow electrical contact with external circuitry. In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically as shown in FIG.
(FIGS. 29 and 30), and the left end of the gate terminal is
In the manufacturing process, it extends beyond the cutting region CT1 of the substrate and is short-circuited by the wiring SHg. Such a short-circuit line SHg in the manufacturing process is used for power supply during anodization and for the orientation film OR.
Useful for preventing electrostatic damage during I1 rubbing.

<< Drain Terminal DTM >> FIG. 34 is a diagram showing a connection from the video signal line DL to the external connection terminal DTM thereof. (A) shows the plane thereof, and (B) shows B of (A).
-B shows a cross section taken along the line B. Note that the drawing corresponds to the vicinity of the upper right of FIG. 30, and although the orientation of the drawing is changed for convenience, the right end direction corresponds to the upper end portion (or lower end portion) of the substrate SUB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but has a width wider than the wiring portion so that a probe needle or the like can come into contact therewith. Similarly, the drain terminal D
The width of the TM is also wider than that of the wiring portion so that the TM can be connected to an external circuit. The inspection terminals TSTd and the external connection drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the substrate SUB1 as shown in the figure, but the drain terminal DTM.
Is a terminal group Td (subscript omitted) as shown in FIG. 30, and is further extended beyond the cutting line CT1 of the substrate SUB1,
During the manufacturing process, all of them are short-circuited to each other by the wiring SHd to prevent electrostatic breakdown. The drain connection terminal is connected to the opposite side of the matrix of the video signal lines DL in which the inspection terminal TSTd exists, and conversely, the drain connection terminal DTM.
The inspection terminal is connected to the opposite side of the matrix of the video signal lines DL in which is present.

The drain connection terminal DTM has the Cr layer g1 and the ITO layer d1 for the same reason as the above-mentioned gate terminal GTM.
Is formed of two layers, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. The protective film PSV1 is, of course, removed on the terminal DTM to connect to an external circuit. AO is the anodizing mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask, but the layer g2 is covered in the part not covered in this figure. This pattern is not directly relevant as it does not exist.

The lead-out wiring from the matrix portion to the drain terminal portion DTM is as shown in the portion (C) of FIG.
The layers d2 and d3 having the same level as the video signal line DL are laminated to the middle of the seal pattern SL just above the layers d1 and g1 having the same level as the drain terminal portion DTM. Is to be minimized, and the Al layer d3, which is easy to contact with electricity, is protected as much as possible by the protective film PSV1 and the seal pattern SL.

<< Equivalent Circuit of Entire Display Device >> FIG. 35 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

SUP is a DC reference voltage generating circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CRT (cathode ray tube) information from a host (upper processing unit) to a TFT. It is a circuit including other parts such as a liquid crystal controller for exchanging information for a liquid crystal display device.

<< Function of Retaining Capacitance Element Cadd >> The retaining capacity element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and source electrode SD1, C
pix is a capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM), ΔV
lc represents a change amount of the pixel electrode potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. Further, the storage capacitor element Cadd also has the function of prolonging the discharge time, and thus the thin film transistor TFT
Accumulates video information for a long time after is turned off. The reduction of the direct current component applied to the liquid crystal LC improves the life of the liquid crystal LC,
It is possible to reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, so that the parasitic capacitance Cgs is increased. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, this demerit can be eliminated by providing the storage capacitor element Cadd.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is the common transparent pixel electrode ITO2.
Set to the same potential as (Vcom). In the example of FIG. 30, the scanning signal line at the first stage is short-circuited to the common electrode COM through the terminal GT0, the lead wire INT, the terminal DT0 and the external wiring. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is the scanning signal line Ye in the last stage.
It may be connected to nd, connected to a DC potential point (AC ground point) other than Vcom, or connected to receive one extra scanning pulse Y ₀ from the vertical scanning circuit V.

<< Overall Structure of Liquid Crystal Display Module >> FIG.
[Fig. 3] is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, and BLS is a backlight. The support and the LCA are the lower case, and the modules MDL are assembled by stacking the respective members in a vertical arrangement relationship as shown in the figure.

The module MDL is a shield case SH.
The whole is fixed by the claw CL and the hook FK provided on D.

The intermediate frame MFR is formed in a frame shape so that an opening corresponding to the display window LCW is provided, and the frame portion has a diffusion plate SPB, a backlight support BLS, and various circuit components in accordance with their shapes and thicknesses. There are irregularities and openings for heat dissipation.

The lower case LCA also serves as a reflector of backlight light, and a reflection mountain RM is formed corresponding to the fluorescent tube BL so as to efficiently reflect light.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 37 is a top view showing a state in which the video signal drive circuits He and Ho, the vertical scanning circuit V, and the power supply circuit are connected to the display panel PNL shown in FIG. 28 and the like.

CHI is a driving IC chip for driving the display panel PNL (the lower three are driving ICs on the vertical scanning circuit side).
Chips, 6 each on the left and right are drive I on the video signal drive circuit side
C chip). The TCP is a tape carrier package in which the driving IC chip CHI is mounted by the tape automated bonding method (TAB) as described later with reference to FIGS. 38 and 39, and the PCB1 is a driving in which the TCP and the capacitor CDS are mounted. It is divided into four on the circuit board. FGP is a frame ground pad,
A spring-like fragment FG provided by cutting into the shield case SHD is soldered. FC is a lower drive circuit board PCB1 and a left drive circuit board PCB1, and a lower drive circuit board PCB1 and a right drive circuit board PCB1,
Upper drive circuit board PCB1 and left drive circuit board PC
The flat cable electrically connects B1 and the upper drive circuit board PCB1 to the right drive circuit board PCB1. As the flat cable FC, as shown in the figure, a plurality of lead wires (phosphor bronze material plated with Sn) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer are used.

Electronic components such as a control circuit TCON, a level shifter IC, a capacitor and a resistor are mounted on the drive circuit board PCB1 on the upper side of the liquid crystal display unit LCD which is held and housed in the intermediate frame MFR. The drive circuit board PCB1 is provided with a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CRT (cathode ray tube) information from a host (upper processing unit). A circuit SUP including a circuit for converting information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected.

<< TCP Connection Structure >> FIG. 38 shows a sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI, which constitutes the scanning signal driving circuit V and the video signal driving circuits He and Ho, is mounted on a flexible wiring substrate. FIG. 48 is a cross-sectional view of essential parts showing a state where it is connected to a liquid crystal display panel, in this example, a video signal circuit terminal DTM.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu and has inner end portions (commonly called inner leads). ) Is the integrated circuit C
The HI bonding pad PAD is connected by a so-called face-down bonding method. Terminals TTB, T
Outer end portions (commonly called outer leads) of TM correspond to the input and output of the semiconductor integrated circuit chip CHI,
CRT / TFT conversion circuit / power supply circuit S by soldering, etc.
A liquid crystal display panel P is formed on the UP by an anisotropic conductive film ACF.
Connected to NL. The package TCP has a protective film PS whose front end exposes the connection terminal DTM on the panel PNL side.
Since it is connected to the panel so as to cover V1, and therefore the external connection terminal DTM (GTM) is covered by at least one of the protective film PSV1 and the package TCP, it is strong against electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not stick to unnecessary places during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX or the like after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 for multiple protection.

As described above, according to the embodiment of the present invention,
The drain driver has a positive polarity with respect to the opposite voltage of the liquid crystal,
Even with a low breakdown voltage drain driver that does not have a driving breakdown voltage capable of driving a negative polarity voltage at the same time, it is possible to equally apply a positive polarity voltage and a negative polarity voltage to each pixel portion on one horizontal line. Current can be prevented from being concentrated, and the voltage distortion of the counter voltage and the voltage distortion of the scanning line in the previous stage can be reduced, so that high quality display can be realized.

Further, according to the embodiment of the present invention, even when the signal line of the liquid crystal panel is drawn from one of the upper side and the lower side, positive and negative voltages are applied to each pixel portion on one horizontal line. Since the voltage can be applied evenly, it is possible to prevent current concentration on the counter electrode or the like, and it is possible to realize high quality display.

Further, according to the embodiment of the present invention, the signal drive circuit does not have a driving withstand voltage for inputting analog display data and capable of simultaneously driving a positive polarity voltage and a negative polarity voltage with respect to the counter voltage of the liquid crystal. Even with a low breakdown voltage drain driver, since positive and negative voltages can be applied uniformly to each pixel portion on one horizontal line, it is possible to prevent current concentration on a counter electrode or the like, and There is an effect that quality display can be realized.

Further, since a low breakdown voltage drain driver can be used while realizing high quality display, the chip size of the drain driver can be reduced, and the cost of the drive circuit of the liquid crystal display device and the liquid crystal display device can be reduced. There is an effect that can be achieved.

Further, by constructing the drain driver with a low breakdown voltage, even if the number of circuits is increased for multicoloring, the cost increase rate can be suppressed.

Further, according to the embodiment of the present invention, since the drain driver inputs the liquid crystal drive voltage which is the reference of the liquid crystal applied voltage from the external power source, it is possible to generate the liquid crystal applied voltage according to the voltage-luminance characteristic of the liquid crystal. Therefore, a liquid crystal display device having excellent gradation characteristics can be realized.

Further, since the drain driver according to the embodiment of the present invention has a function of generating a liquid crystal applied voltage having a high current driving capability, it is possible to easily cope with high definition and large screen of the liquid crystal panel.

Further, according to the embodiment of the present invention, there is an effect that the cost of the information processing device which employs the liquid crystal display device can be reduced.

[0376]

As described above, according to the present invention, it is possible to provide a liquid crystal display device using a drain driver having a low withstand voltage, which is superior in image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a level shifter according to the first exemplary embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the level shifter according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a signal drive circuit according to the first exemplary embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an equivalent circuit of the liquid crystal panel according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a first AC circuit according to the first embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a second AC circuit according to the first embodiment of the present invention.

FIG. 8 is a timing chart showing drive waveforms during a frame AC operation of the liquid crystal panel according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram showing voltage-luminance characteristics of the liquid crystal according to the first embodiment of the present invention.

FIG. 10 is an explanatory diagram showing voltage application polarities of the liquid crystal panel during a frame AC operation in the first embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a digital-analog conversion circuit according to the first exemplary embodiment of the present invention.

FIG. 12 is a timing chart showing drive waveforms during a line AC operation of the liquid crystal panel in the first embodiment of the present invention.

FIG. 13 is an explanatory diagram showing the voltage application polarities of the liquid crystal panel during the line AC operation in the first embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a signal drive circuit according to a second embodiment of the present invention.

FIG. 16 is an explanatory diagram showing an equivalent circuit of the liquid crystal panel according to the second embodiment of the present invention.

FIG. 17 is an explanatory diagram showing a voltage application polarity of the liquid crystal panel during a frame AC operation in the second embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of a signal drive circuit according to a third embodiment of the present invention.

FIG. 20 is a block diagram showing a configuration of an AC circuit of the present invention according to a third embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a signal drive circuit according to a fourth example of the present invention.

FIG. 23 is an explanatory diagram showing voltage supply paths of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of an information processing device to which the liquid crystal display device according to the embodiment of the invention is applied.

FIG. 25 is a main-portion plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device according to an embodiment of the present invention.

FIG. 26 is a cross-sectional view showing one pixel and its periphery of a liquid crystal display unit according to an example of the present invention.

FIG. 27 is a cross-sectional view of an additional capacitor of a liquid crystal display unit according to an example of the present invention.

FIG. 28 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel according to the example of the present invention.

FIG. 29 is a plan view for specifically explaining the peripheral portion of the matrix according to the embodiment of the present invention.

FIG. 30 is an enlarged plan view of a corner portion of a display panel including electrical connection portions of upper and lower substrates according to an embodiment of the present invention.

FIG. 31 is a cross-sectional view showing the pixel portion of the matrix according to the embodiment of the present invention in the center, the panel angle on both sides and the video signal terminal portion.

FIG. 32 is a scanning signal terminal on the left side according to the embodiment of the present invention;
It is sectional drawing which shows the panel edge part without an external connection terminal on the right side.

FIG. 33 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL according to an example of the present invention.

FIG. 34 is a plan view and a cross-sectional view showing the vicinity of the connection portion between the drain terminal DTM and the video signal line DL according to the example of the present invention.

FIG. 35 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device according to an embodiment of the present invention.

FIG. 36 is an exploded perspective view of a liquid crystal display module according to an embodiment of the present invention.

FIG. 37 is a top view showing a state in which a peripheral drive circuit is mounted on the liquid crystal display panel according to the example of the present invention.

FIG. 38 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI which constitutes a drive circuit according to an example of the present invention is mounted on a flexible wiring board.

FIG. 39 is a main-portion cross-sectional view showing a state in which the tape carrier package TCP according to the embodiment of the present invention is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.

FIG. 40 is a block diagram showing a configuration of a liquid crystal display device according to a first conventional technique.

FIG. 41 is a block diagram showing a configuration of a signal drive circuit according to a first conventional technique.

FIG. 42 is a timing chart showing drive waveforms in the liquid crystal display device according to the first conventional technique.

FIG. 43 is a diagram showing voltage-luminance characteristics of the liquid crystal according to the first conventional technique.

FIG. 44 is a block diagram showing a configuration of a liquid crystal display device according to a second conventional technique.

FIG. 45 is a block diagram showing a configuration of a signal drive circuit according to a second conventional technique.

FIG. 46 is a timing chart showing drive waveforms in the liquid crystal display device according to the second conventional technique.

FIG. 47 is an explanatory diagram showing voltage application polarities in the liquid crystal display device according to the second conventional technique.

FIG. 48 is a diagram showing voltage-luminance characteristics of the liquid crystal according to the second conventional technique.

[Explanation of symbols]

101: System bus 102: Liquid crystal controller 103-105: Reference voltage line 106, 107: Control bus for signal drive circuit 108: Control bus for scan drive circuit 109: Liquid crystal alternating signal 110, 111: Level shifter 112, 113: Signal drive Circuit control buses 114 and 115: Signal drive circuit 118: Scan drive circuit 119: Scan line 120: Liquid crystal panel 121: DC reference voltage generation circuit 122: Scan drive circuit DC voltage line 123: Counter electrode line 126: AC circuit 401 : drain driver 403: shift register 405: latch circuit 407: latch circuit 409: digital-to-analog converter 501: the pixel portion 502: T hin F ilm T ransister 503: LCD 504: additional capacitor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makiko Ikeda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Naruhiko Kasai 2880, Kokuzu, Odawara, Kanagawa Address Stock Company Hitachi Storage Systems Division (72) Inventor Toshio Futami 3300 Hayano, Mobara, Chiba Prefecture Hitachi Electronic Devices Division (72) Inventor Tetsuya Suzuki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ceremony company Hitachi Image Information System

Claims (13)

[Claims] 1. A liquid crystal display device comprising a liquid crystal panel in which liquid crystal cells are arranged in a matrix for displaying with a brightness corresponding to an absolute value of a voltage difference between a counter voltage and an applied voltage when a selection voltage is supplied. In each of the lines on the matrix, a common selection voltage is sequentially supplied to the liquid crystal cells belonging to the line, and a DC voltage common to all the liquid crystal cells of the liquid crystal panel is applied to each liquid crystal. A voltage group that is applied as a counter voltage to the cell and in which the polarity with respect to the counter voltage is periodically inverted is generated, and in at least one column of liquid crystal cells on the matrix, among the liquid crystal cells of the column to which the liquid crystal cell belongs The generated voltage group is used to generate and apply a voltage having a polarity corresponding to the polarity of the generated voltage group, which realizes brightness according to the content displayed on the liquid crystal cell of the line to which the selection voltage is supplied. A method of driving a liquid crystal display device, characterized in that the liquid crystal display device is supplied as a voltage. 2. A liquid crystal display device for driving a liquid crystal panel in which liquid crystal cells are arranged in a matrix for displaying at a brightness corresponding to an absolute value of a voltage difference between a counter voltage and an applied voltage when a selection voltage is supplied. A scanning circuit for sequentially supplying a common selection voltage to the liquid crystal cells belonging to the line for each line on the matrix, and a voltage common to all the liquid crystal cells of the liquid crystal panel. A scan driving unit that applies each liquid crystal cell as an opposite voltage, and two applied voltage values that realize the highest brightness and the lowest brightness of the liquid crystal cell that is used for display, among the values of the applied voltage that is negative with respect to the opposite voltage. Of the applied voltage of the positive polarity with respect to the counter voltage that includes, as a potential between the maximum voltage and the minimum voltage, and realizes the maximum brightness or the minimum brightness,
A negative driving voltage group that does not include the applied voltage value having the larger absolute value of the voltage difference with respect to the counter voltage as a potential between the maximum voltage and the minimum voltage, and the positive voltage applied to the counter voltage. Among the voltage values, two opposing voltage values that realize the above-mentioned maximum brightness and the minimum brightness are included as potentials between the maximum voltage and the minimum voltage, and the counter voltage that realizes the maximum brightness or the minimum brightness On the other hand, among positive applied voltages, a positive driving voltage group that does not include the applied voltage value having the larger absolute value of the voltage difference with respect to the opposite voltage as the potential between the maximum voltage and the minimum voltage. And a selection voltage of the liquid crystal cells of the column to which the liquid crystal cell belongs is supplied to each liquid crystal cell of the corresponding column provided corresponding to each column on the matrix. Display on line LCD cell A plurality of driving means for supplying a voltage that realizes a brightness according to the content as an applied voltage, and two driving means groups obtained by dividing the plurality of driving means into the positive driving voltage group and the negative driving voltage group. And a driving means supplied with the positive driving voltage group, using a positive driving voltage group, and a positive voltage with respect to the opposite voltage. The driving means, which is supplied with a negative applied voltage group and is supplied with a negative driving voltage group, supplies a negative applied voltage to the counter voltage using the negative driving voltage group. Drive circuit for liquid crystal display device. 3. A drive circuit for a liquid crystal display device according to claim 2, wherein the scan drive means applies a DC voltage common to all liquid crystal cells of the liquid crystal panel to each liquid crystal cell as the counter voltage. A drive circuit of a liquid crystal display device characterized by the above. 4. The drive circuit for a liquid crystal display device according to claim 2, wherein one of the two drive means groups obtained by dividing the plurality of drive means is an even number on the matrix. A group of drive means corresponding to the column of
A drive circuit of a liquid crystal display device, which is a group of drive means corresponding to an odd number of columns on the matrix. 5. A liquid crystal display device for driving a liquid crystal panel, in which liquid crystal cells are arranged in a matrix for displaying with a brightness according to an absolute value of a voltage difference between a counter voltage and an applied voltage when a selection voltage is supplied. A driving circuit for sequentially supplying a common selection voltage to the liquid crystal cells belonging to the line for each line on the matrix, and a DC voltage common to all the liquid crystal cells of the liquid crystal panel. , Scan driving means to be given as a counter voltage to each liquid crystal cell, a set of a negative drive voltage group having a negative polarity with respect to the counter voltage and a negative operation reference voltage, and a positive drive voltage having a positive polarity with respect to the counter voltage Group and a group of positive operating reference voltages, and two driving means groups obtained by dividing the plurality of driving means into a group of a negative driving voltage group and a negative operating reference voltage, and a positive polarity. Drive voltage and positive polarity Means for supplying a set of operation reference voltages alternately and periodically for each set, and one of a positive operation reference voltage and a negative operation reference voltage provided corresponding to each column on the matrix. The supplied data is used to process the supplied display data, and a voltage that realizes brightness according to the display data is generated from the supplied positive drive voltage group or the negative drive voltage group. Then, among the plurality of driving means supplied as the applied voltage and the driving means group to which the positive polarity operation reference voltage is applied, among the display data strings that define the display contents on the liquid crystal panel,
The voltage level of the display data that defines the display content displayed in the column corresponding to the drive means group is converted into a voltage level that can be processed using the positive polarity operation reference voltage and supplied, and the negative polarity operation reference voltage is applied. The voltage level of the display data that defines the display content to be displayed in the column corresponding to the drive means group in the display data row that defines the display content on the liquid crystal panel is set to the negative operation standard. A drive circuit for a liquid crystal display device, comprising: a level conversion circuit that converts the voltage to a processable voltage level and supplies the voltage level. 6. A drive circuit for a liquid crystal display device according to claim 5, wherein one drive means group of the two drive means groups obtained by dividing the plurality of drive means is an even-numbered column on the matrix. Which is a group of driving means corresponding to
A drive circuit of a liquid crystal display device, which is a group of drive means corresponding to an odd number of columns on the matrix. 7. The drive circuit for a liquid crystal display device according to claim 5, wherein the drive means is supplied to the driver in accordance with a high-order bit of display data defining display contents of a corresponding column. A selection circuit that selects an upper voltage and a lower voltage from one of the positive drive voltage group and the negative drive voltage group, and first applies the lower voltage selected by the first selection circuit to each of the display data. After the voltage is output as the applied voltage for a certain period of time, the voltage division ratio is determined according to the displayed lower bit, and the voltage divided between the supplied upper voltage and lower voltage is used as the applied voltage at the determined voltage division ratio. A driving circuit for a liquid crystal display device, comprising: a voltage dividing circuit for outputting. 8. A drive circuit for a liquid crystal display device according to claim 5, wherein a display is provided between drive means supplied with a positive drive voltage group and drive means supplied with a negative drive voltage group. In order to send and receive a control signal for notifying the data acquisition timing, the voltage level of the control signal is set to the negative operation reference voltage or the positive operation reference voltage supplied to the receiving side driving means. A drive circuit for a liquid crystal display device, comprising a level conversion circuit for a control signal for converting to a voltage level that can be processed using any one of the above. 9. A drive circuit for a liquid crystal display device according to claim 5, wherein said drive means uses one of a positive polarity operation reference voltage and a negative polarity operation reference voltage which is supplied to said drive means. And a level conversion unit, and a digital / analog conversion unit, the digital unit cyclically stores the display data stored in the shift register and the shift register that sequentially stores the display data. , And a latch group for fetching and storing in parallel, and the level conversion unit supplies the voltage level of the display data stored in the latch to the drive means of the positive drive voltage group and the negative drive voltage group. One of the positive drive voltage group and the negative drive voltage group that is supplied to the drive means is used to convert the voltage level into a processable voltage level using A drive circuit for a liquid crystal display device, which supplies the applied voltage. 10. A liquid crystal display device for driving a liquid crystal panel in which liquid crystal cells are arranged in a matrix form to perform display at a brightness corresponding to an absolute value of a voltage difference between a counter voltage and an applied voltage when a selection voltage is supplied. A driving circuit for sequentially supplying a common selection voltage to the liquid crystal cells belonging to the line for each line on the matrix, and a DC voltage common to all the liquid crystal cells of the liquid crystal panel. A scan driving means for applying a counter voltage to each liquid crystal cell, a negative operation reference voltage having a negative polarity with respect to the counter voltage, and a positive operation reference voltage having a positive polarity with respect to the counter voltage, Means for periodically and alternately supplying a negative operation reference voltage and a positive operation reference voltage to two drive means groups obtained by dividing the plurality of drive means, and a positive operation reference voltage and a negative operation reference voltage. A plurality of driving means including a holding means for operating and using the supplied one of the supplied display signals, and a driving means group to which a positive polarity operation reference voltage is applied, Of the display signals, the voltage level of the display signal that defines the display content to be displayed in the column corresponding to the drive means group is converted to a voltage level that can be processed using the positive polarity operation reference voltage and is supplied. To the drive means group to which a sexual operation reference voltage is applied, the voltage polarity of the display signal that defines the display content to be displayed in the column corresponding to the drive means group among the display signals is inverted, and the voltage level is changed to A drive circuit for a liquid crystal display device, comprising: a conversion circuit for converting and supplying a voltage level that can be processed using a negative polarity operation reference voltage. 11. A liquid crystal panel in which liquid crystal cells are arranged in a matrix for displaying with a brightness corresponding to an absolute value of a voltage difference between a counter voltage and an applied voltage when a selection voltage is supplied, and the liquid crystal panel. Driving, claim 2, 3, 3, 5, 6,
A liquid crystal display device comprising the drive circuit according to 7, 8, 9 or 10. 12. A liquid crystal display device according to claim 11, wherein the liquid crystal display device is an active matrix liquid crystal panel using the liquid crystal TFT (Thin Film Transister). 13. A liquid crystal display device according to claim 11, wherein information is processed, the display content is determined according to the processing result,
An information processing apparatus, comprising: a data processing unit for requesting the liquid crystal display device to display data or a display signal defining the determined display content.