JPH06216772A - A/d converter and completely differential operational amplifier circuit - Google Patents

Abstract

PURPOSE:To provide an A/D converter capable of suppressing the deterioration of S/H characteristic by the influence of a noise to a minimum even when the converter is loaded by mixing with a large scale digital circuit. CONSTITUTION:A differential signal forming circuit 6 as an invertible amplifier is constituted by using a completely differential operational amplifier circuit 4 equipped with an in-phase feedback input terminal CMF and a resistor means. An analog input signal of single end is converted to a differential signal by inputting an analog signal to the negative input terminal side of the completely differential operational amplifier circuit, connecting the positive input terminal side to analog signal ground, and feeding back the midpoint potential of differential output to the in-phase feedback input terminal. After the differential signal is A/D-converted, a digital signal is converted to the digital signal of single end by applying digital substraction to it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the field of A / D converters used in digital / analog mixed LSIs and the like. TECHNICAL FIELD The present invention relates to a technique effectively applied to prevent deterioration of S / N characteristics, and to prevent deterioration of S / N characteristics of an A / D converter due to a decrease in analog signal amplitude in a low-voltage operation LSI. It is a thing.

[0002]

2. Description of the Related Art As an A / D converter mounted on a microprocessor or the like, for example, a reference voltage created by resistance-dividing a power supply voltage and a ground voltage (ground potential), and a sample hold Input signal and
Compare with a chopper type comparator using an inverter,
There is a successive approximation type A / D converter in which a reference voltage is changed by a control circuit based on the magnitude judgment result and the digital data is sequentially determined from upper bits. Further, Japanese Patent Application Laid-Open No. 61-123313 discloses that an analog input signal is differentiated and two systems of A / D conversion circuits and both A's are used.
An A / D conversion circuit that obtains a single-ended digital signal by using an arithmetic circuit that calculates the difference between A / D conversion outputs is shown. This is suitable for TV signals, and has two systems of A
It is based on a technique for achieving high accuracy by using a D / D conversion circuit. Single-ended analog signals use a non-inverting amplifier circuit and an inverting amplifier circuit each configured by a separate operational amplifier circuit. A feedback loop is configured by using another operational amplifier circuit so that the added value of the output of the above-mentioned becomes equal to the reference voltage. As a result, DC drift can be prevented, and the dynamic ranges of the A / D conversion circuits can be connected to each other in character, so that an A / D conversion circuit with high linearity and high accuracy can be obtained.

[0003]

When a digital circuit mounted together with an analog circuit on the same semiconductor substrate operates, a relatively large current flows in the power supply line according to the operating state, the power supply voltage fluctuates, and the transistor The junction capacitance formed between the diffusion layer and the semiconductor substrate is charged / discharged according to the operation of the transistor, which causes noise through the semiconductor substrate. Such noise is also transmitted to analog circuits sharing the semiconductor substrate. When the analog circuit includes an A / D conversion circuit or a local D / A conversion circuit using a switched capacitor integration circuit or a capacitor array, the junction capacitance is connected to the storage node of the capacitor during the charging / discharging operation of the capacitor by the switch operation. Potential fluctuation due to the influence of digital noise is given through such as. Then, an error occurs in the charge / discharge amount of the capacitor, and the S / N characteristic of the A / D conversion result deteriorates. Deterioration of the characteristics of the analog circuit due to digital noise is not limited to this, but also occurs due to power supply fluctuations due to digital noise and crosstalk with the power supply line whose level fluctuates. The successive approximation type A / D
In the converter, since the dynamic range of the analog signal is full of the power supply voltage, general analog element circuits such as an operational amplifier and a comparator cannot be used, and the circuit system is limited. Further, since the reference voltage is provided by dividing the power supply voltage and the ground voltage by resistance division, noise is added to the reference voltage due to ground noise due to noise of other large-scale digital circuits and input / output buffer circuits, and the A / D converter S
There is a problem that the / N characteristic is deteriorated. Further, in an A / D converter realized by using a general analog element circuit such as an operational amplifier or a comparator by limiting the dynamic range of an analog signal, a board using another large-scale digital circuit or an input / output buffer circuit. It has been found by the present inventor that characteristics may deteriorate due to noise. For example, in the above-mentioned Japanese Patent Laid-Open No. 61-123313, since the individual non-inversion amplifier circuits are used for differential operation, respectively, the respective inversion amplifier circuits are used, and therefore, the output of each output against the power supply fluctuation is It was found by the present inventors that the S / N characteristics are different and the noise component cannot be canceled even if the difference between the A / D conversion results in the latter stage is taken. In addition, in an LSI used in a portable terminal device or the like, a low voltage operation is required to reduce the power consumption, but the dynamic range of the analog signal has to be reduced with the decrease in the voltage and the S / N characteristic is deteriorated. The present inventor has also revealed that there is a problem of

An object of the present invention is to provide an A / D converter capable of minimizing deterioration of the S / N characteristic due to the influence of noise even if it is mounted on a large-scale digital circuit. Another object of the present invention is to provide an A / D converter capable of increasing the dynamic range of an analog signal even with a low power supply voltage and minimizing deterioration of S / N characteristics. Still another object is to provide a fully differential operational amplifier circuit most suitable for the A / D converter.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

(1) That is, a differential signal conversion circuit as an inverting amplifier is constructed by using a fully differential operational amplifier circuit having an in-phase feedback input terminal and a resistance means, and a negative input terminal side of the fully differential operational amplifier circuit. An analog signal is input to, the positive input terminal side is connected to the analog signal ground, and the midpoint potential of the differential output is fed back to the common-mode feedback input terminal to convert the single-ended analog input signal to a differential signal. Then, after each A / D conversion, the digital signal is digitally subtracted to be converted into a single end digital signal. (2) The fully differential operational amplifier circuit has a negative input terminal to which a single-ended analog signal is supplied via the first input resistance means and a positive input to which an analog ground potential is supplied via the second input resistance means. A terminal, a positive output terminal connected to the negative input terminal via the first feedback resistance means, a negative output terminal connected to the positive input terminal via the second feedback resistance means, a positive output terminal and a negative output A common-mode feedback input terminal to which a voltage formed based on the common-mode voltage of the terminal is supplied, and a common-mode feedback terminal between the positive output terminal and the negative output terminal so that the input voltage of the common-mode feedback input terminal approaches the analog signal ground. Of the analog input signal is output to the negative output terminal and a signal having the opposite phase of the analog signal is output to the positive output. (3) The gain of the differential signal conversion circuit is determined according to the ratio of the input resistance means and the feedback resistance means. (4) Such a fully differential operational amplifier circuit includes a MOS transistor of a current source, a pair of MOS transistors corresponding to positive and negative input terminals and having sources connected to each other, and a load MOS transistor of the pair of MOS transistors. An input differential stage, a source ground amplifier circuit for amplifying the output of the input differential stage to form positive and negative outputs, an output of the source ground amplifier circuit and the input differential stage. A phase compensation circuit connected in series with the output and an in-phase feedback input differential stage are provided. The in-phase feedback input differential stage has a current source MOS transistor and one input is an analog signal ground. A pair of MOS transistors whose sources are connected to each other and whose other inputs are common-mode feedback input terminals,
And a drain connected to the differential MOS transistor, and the output of the common mode feedback input terminal side is connected to the gate of the load MOS transistor of the input differential stage. It can be realized as a class A differential amplifier circuit including a differential stage for input feedback. This fully differential operational amplifier circuit has circuit configuration symmetry between the circuit configuration on the positive output terminal side viewed from the negative input terminal and the circuit configuration on the negative output terminal side viewed from the positive input terminal. There is. (5) In order to reduce the input offset in such a fully differential operational amplifier circuit, each of the MOS transistors forming a pair of differential stages included therein has a unit size of M.
The required transistor size is secured by arranging a plurality of OS transistors in parallel, and each pair M
The unit-sized MOS transistors forming the OS transistors are laid out in close proximity to each other and regularly dispersed.

[0008]

(1) According to the above means, the single-ended analog signals are made into the differential signals having the opposite phases by the differential signal conversion circuit. A differential signal conversion circuit configured by a fully differential operational amplifier circuit uses, as common noise, a noise component that is applied to an analog input signal and an in-phase output signal and an anti-phase output signal, respectively. Then, each signal is converted into a digital signal by an A / D converter, then subtracted and converted into a single-ended digital signal. Substrate noise generated by a large-scale digital circuit or input / output buffer circuit is in-phase on the differential signal conversion circuit or each A / D converter, and the noise components of the differential output of the differential signal conversion circuit are mutually Since it is common noise, the common noise and common-mode noise components are canceled by the final digital subtractor. As a result, the characteristics such as S / N are not deteriorated even if they are mixed with many noise sources such as large-scale digital circuits and input / output buffer circuits, and the target performance of the A / D converter is satisfied. You can (2) Since the differential signal conversion circuit can adjust the gain, for example, even if the input analog signal has a dynamic range in which the power supply voltage is full, if the gain is selected to be 1 time, a pair of A / D
The dynamic range of the differential analog output signal to be converted by the conversion circuit can be halved of the power supply voltage, and the normal analog circuit such as the operational amplifier circuit can be used. Further, if the gain is selected to be doubled, the signal amplitude can be effectively doubled, and even a low voltage operation LSI can handle a large signal amplitude. In this respect also, deterioration of the S / N characteristic is minimized. (3) A differential A / D conversion circuit capable of minimizing deterioration of characteristics such as S / N even when mounted on an LSI mounted together with a large-scale digital circuit is realized even for low voltage operation.

[0009]

FIG. 1 is a block diagram showing an embodiment of an A / D converter according to the present invention. A / D converter 1 of this embodiment
Is a differential signal conversion circuit 6, A / D conversion circuits ADM, AD
P and a subtractor 5. The differential signal conversion circuit 6 is configured by using the fully differential operational amplifier circuit 4. The fully differential operational amplifier circuit 4 includes a positive input terminal (non-inverting input terminal) NP, a negative input terminal (inverting input terminal) NM, a positive output terminal (non-inverting output terminal) NOP, a negative output terminal (inverting output terminal). NOM and common mode feedback input terminal (common mode
Feedback terminal) CMF is provided. The fully differential operational amplifier circuit 4 includes a positive output terminal NOP and a negative output terminal NOM.
By feeding back the voltage formed based on the common-mode potential of the common-mode feedback input terminal CMF to the input voltage of the common-mode feedback input terminal CMF, the positive output terminal NOP and the negative output terminal are brought close to the analog signal ground. It operates so that the voltage of the same phase between the NOMs is constant. Further, the fully differential operational amplifier circuit 4 has a circuit configuration on the positive output terminal NOP side as viewed from the negative input terminal NM and a positive input terminal N.
The circuit configuration has symmetry with the circuit configuration on the negative output terminal NOM side viewed from P.

Analog signal input terminal A of A / D converter 1
An input resistor R1M is arranged between IN and the negative input terminal NM of the fully differential operational amplifier circuit 4, and the analog signal ground V
An input resistor R1P is arranged between B and the positive input terminal NP. A feedback resistor R2M is arranged between the negative input terminal NM and the positive output terminal NOP, and a feedback resistor R2P is arranged between the positive input terminal NP and the negative output terminal NOM. The voltage of the positive output terminal NOP and the voltage of the negative output terminal NOM are the resistance R3M.
And R3P, and the midpoint potential of the positive and negative outputs is input to the in-phase feedback input terminal CMF. According to this embodiment, the resistors R1M, R1P, R2M and R2P have the same resistance value, respectively, and the feedback resistors R3M and R3P have the same resistance value. As a result, the fully differential operation amplifier circuit 4 makes the input signal amplitude of the analog signal input terminal AIN equal to the potential difference between the negative output terminal NOM and the positive output terminal NOP (that is, fully differential operation). The amplifier circuit has a gain of 1), and the negative output terminal NOM
And a negative feedback operation is performed so that the midpoint potential of the positive output terminal NOP reaches the analog signal ground VB. As a result, the negative output terminal NOM is connected to the analog signal input terminal AIN.
A signal with half the amplitude is output in phase with the positive output terminal NO
A signal having a reverse phase and a half amplitude is output to P. The output of the negative output terminal NOM in phase with the input signal is the A / D conversion circuit AD
The signal is converted into a digital signal by P, and the output of the positive output terminal NOP having a phase opposite to that of the input signal is converted into a digital signal by the A / D conversion circuit ADM. The subtractor 5 is an A / D conversion circuit AD
The digital signal of the A / D conversion circuit ADM is digitally subtracted from the digital signal of P to be converted into the final digital signal Dout of the single end output. In this way, the single-ended analog signals are made into differential signals of opposite phases in the fully differential operational amplifier circuit 4, and the respective signals are converted into digital signals in parallel by the A / D converters ADP and ADM. Then, it is subtracted by the subtractor 5 and converted into a single-ended digital signal. Differential operational amplifier circuit 4
The common noise is a noise component that rides on each of the in-phase output signal and the anti-phase output signal of the analog input signal. Substrate noise generated by a large-scale digital circuit and an input / output buffer circuit formed on the same chip together with the A / D converter 1 is caused by the differential signal conversion circuit 6 and each A / D conversion circuit AD.
Riding M and ADP in-phase. Therefore, such in-phase noise and the common noise are canceled by the final digital subtractor 5. As a result, the A / D converter 1 does not deteriorate in characteristics such as S / N even when mixed with many noise sources such as a large-scale digital circuit and an input / output buffer circuit, and the A / D converter 1 does not deteriorate. The target performance of the converter can be satisfied.

FIG. 2 shows an embodiment in which the A / D converter 1 is applied to an A / D converter having a dynamic range of which power supply voltage is full. The analog signal ground VB is divided by half from the power supply voltage VDD by (1/2) VD
It is set to D and used through a buffer amplifier 8A such as a voltage follower. Further, the reference voltage of the A / D converter 1 is set to (1/4) · VDD which is ¼ of the power supply voltage VDD by resistance division, and is used through the buffer amplifier 8B. The differential signal conversion circuit 6 having a gain of 1 is used to increase the signal dynamic range of the power supply voltage to (1 /
2) The signal voltage range is compressed in half by ± (1/4) · VDD centering on VDD. The differential signals AOP and AOM are received by A / D conversion circuits ADP and ADM. The A / D conversion circuit AMD has an input capacitance CI and a local D
/ A conversion circuit 30, analog integration circuit 31, comparison circuit 3
2 and the control circuit 33. This A / D
The conversion circuit AMD includes an output and an input capacitance CI of a local charge redistribution type D / A conversion circuit 30 of a switched capacitor type.
An analog input signal via the analog input signal is analogly subtracted by the analog integration circuit 31, the output thereof is compared by the comparison circuit 32, and the control circuit 33 determines the local D / A based on the comparison result.
It controls the conversion circuit 30 and outputs a digital signal that matches the analog input signal. In FIG. 2, the digital output of the A / D conversion circuit AMD is obtained from the control circuit 33.
The other A / D conversion circuit ADP is similarly configured. The digital outputs of both A / D conversion circuits ADP and ADM are digitally subtracted by the subtractor 5 and converted into a single-ended digital signal. With such a circuit,
An input signal with a full power supply voltage can be processed by using an analog circuit technology such as a normal switched capacitor with ± (1/4) · VDD centered at (1/2) · VDD, and the reference potential therefor is an operational amplifier circuit. Buffer amplifiers 8A, 8B
It is possible to realize buffering, and it is possible to realize a good S / N characteristic in A / D conversion in addition to the effect of noise resistance due to the above-mentioned differential. The local D / A conversion circuit 30
The capacitors Cn to C1 included in are connected at their lower electrodes to (1/4) .VDD as the reference potential or the ground potential GND by the precharge operation prior to the integration operation of the A / D conversion circuit ADM. The control circuit 33 determines whether the output of the local D / A conversion circuit 30 is a positive potential or a negative potential with respect to the analog ground.

FIG. 3 is a circuit diagram showing an example of the fully differential operational amplifier circuit 4. The operational amplifier 4 is a class A differential amplifier circuit including a differential stage for in-phase input feedback as a whole. In the input differential stage of the operational amplifier 4, the gate is connected to the bias potential BIAS1 and the current source is a P-channel type MOS transistor M5 of the current source and the MOS transistor M5.
Source-coupled P-channel type M connected to the drain of
A pair of OS transistors M3 and M4 (the gates of which are respectively a negative input terminal NM and a positive input terminal NP), an N-channel load MOS transistor M1 to which the drain of the MOS transistor M3 is connected, A drain of the MOS transistor M4 and an N-channel type load MOS transistor M2 connected to the drain,
The node N which is the drain of the OS transistors M3 and M1
D2 is connected to a source ground amplifier circuit on the negative output side composed of MOS transistors M11 and M12, and the node ND3 which is the drain of the MOS transistors M4 and M2 is M
The source of the load MOS transistors M1 and M2 is connected to the source grounded amplifier circuit on the positive output side composed of the OS transistors M13 and M14, and the source is grounded.
The gates of M2 are connected to each other, and further the transistor M6
~ M10 connected to the output of the common mode feedback input differential stage. The source grounded amplifier circuit on the negative output side is a P-channel type current source MOS transistor M1 whose source is connected to the power supply voltage VDD and whose gate is connected to the bias potential BIAS1.
2, the source is the ground potential GND, and the gate is the node ND2.
Drive MOS transistor M11 connected to
The drains of the transistors M11 and M12 serve as a negative output terminal negative output terminal NOM. The source grounded amplifier circuit on the positive output side is a P-channel type current source M whose source is connected to the power supply voltage VDD and whose gate is connected to the bias potential BIAS1.
The OS transistor M14 and the source are ground potential GND,
The gate is composed of a drive MOS transistor M13 connected to the node ND3, and the drains of the transistors M13 and M14 serve as the positive output terminal positive output terminal NOP. Further, between the negative output terminal NOM and the node ND2, a capacitor CC1 and a gate are connected to the bias potential BIA for phase compensation.
The MOS resistor MC1 connected to S2 is inserted. Further, between the positive output terminal NOP and the node ND3, the capacitor CC2 and the gate are connected to the bias potential BIAS for phase compensation.
The MOS resistor MC2 connected to 2 is inserted. The in-phase feedback input differential stage is a P-channel type current source MOS transistor M whose gate is connected to the bias potential BIAS1.
10 and a P-channel type MOS transistor pair M8 and M9 whose sources are commonly connected to the drain of the transistor M10 (the gate of the transistor M8 is connected to the analog signal ground, and the gate of the transistor M9 is a common mode feedback input). Terminal CMF), an N-channel load MOS transistor M6 having a drain connected to the drain of the transistor M8, and a transistor M9.
Drain MOS, and an N-channel load MOS transistor M7 to which the drain and the gate are connected, and the drain connection node ND6 of the transistors M7 and M9 is connected to the gates of the transistors M1 and M2 of the input differential stage. To be done. The circuit shown in the figure is configured with a minimum number of elements.

For example, the negative output terminal NOM and the positive output terminal NO
When the common mode voltage of P (voltage obtained by resistance-dividing between terminals NOM and NOP) is input to the common mode feedback input terminal CMF, the potential of the node ND6 becomes high when the common mode voltage is lower than the analog signal ground. With node ND2
And the potential of the node ND3 becomes low, the drive capability of the MOS transistors M11 and M13 is made small, and the positive output terminal NO
It operates so as to raise the potentials of P and the negative output terminal NOM. On the contrary, when the common-mode voltage is higher than the analog signal ground, the potential of the node ND6 becomes low, and accordingly, the node ND2.
And the potential of the node ND3 becomes high, the drive capability of the MOS transistors M11 and M13 is increased, and the positive output terminal NO
It operates so as to lower the potentials of P and the negative output terminal NOM. In this way, negative feedback is applied so that the in-phase voltage of the differential output matches the analog signal ground, and a differential output centered on the analog signal ground can be obtained.

FIG. 4 shows a simulation result of frequency characteristics of the fully differential operational amplifier circuit 4 designed in the circuit form of FIG. Load capacitance is 10pF and DC gain is 83d
B, gain bandwidth product ft is 2.5 MHz, phase margin is 59
The angle was °, and stable operation was confirmed.

FIG. 5 shows a simulation result of the output waveform of the differential signal conversion circuit 6 having a gain of 1. 4 kHz
Input sine wave is 1.7V which is analog signal ground
It can be seen that they are converted into differential outputs with opposite phases centering on and with half the amplitude. The output of the negative output terminal NOM is in phase with the input signal, and the output of the positive output terminal NOP is in phase with the input signal. The differential output, which is the difference between the output V (NOM) of the negative output terminal NOM and the output V (NOP) of the positive output terminal NOP, has an output delay of 0.12 μs and high frequency distortion (THD: Total).
It can be seen that Harmonic Distortion) has a low distortion of −79.8 dB and can be applied to an A / D converter up to about 13-bit precision even with a large amplitude.

FIG. 6 shows a power supply noise rejection ratio (PSRR) of the differential signal conversion circuit 6 having a gain of 1.
tio) simulation results are shown. Simply speaking, PSRR is the rate of change of the output with respect to the rate of change of the power supply of the circuit, and the smaller the value, the smaller the power supply noise component. PSR of positive output terminal NOP and negative output terminal NOM
R individually shows the PSRR characteristic of a normal operational amplifier, but in the differential output that is the difference between the output V (NOM) of the negative output terminal NOM and the output V (NOP) of the positive output terminal NOP, power supply noise components are mutually generated. These are offset, resulting in a very high PSRR characteristic. In the simulation, since the pairing of transistors and the like is in an ideal state, the numerical value is 200 dB or more. Actually, although deterioration due to variations in MOS characteristics and asymmetry of layout is considered, good PSRR characteristics can still be expected. This can be realized because of the symmetry of the fully differential operational amplifier circuit 4. Thus, the differential signal conversion circuit 6 of FIG. 1 has a very high PSRR.
It can be seen that the characteristics, in other words, good noise resistance can be realized.

FIG. 7 shows an example in which a differential signal conversion circuit equivalent to that in FIG. 1 is realized by using a single-ended operational amplifier. In this circuit, the analog input signal AIN is gain-controlled by an inverting amplifier 81, and then converted into a differential signal by using a voltage follower circuit 82 and an inverting amplifier 83 having a gain of 1. As a result of simulating the output waveform with this circuit, the output delay time is 0.17 μs, which is not much different from the circuit in FIG. 1, but the harmonic distortion THD is 66.1 dB and only an A / D converter with about 10-bit accuracy is realized. I see that I can't.

FIG. 8 shows a simulation result of the PSRR characteristic of the circuit of FIG. Since the overall PSRR characteristic is limited by the PSRR characteristic of the inverting amplifier 81 for the first stage gain adjustment, the characteristic is significantly worse than the result of FIG. That is, the noise component appearing in the inverting amplifier 81 is not reflected as the common noise in the outputs of the voltage follower 82 and the inverting amplifier 83, and as a result, it acts in a direction to expand the noise.

FIG. 9 shows an example in which a differential signal conversion circuit equivalent to that of FIG. 1 is realized by using two single-ended operational amplifiers as a normal amplification circuit and an inverting amplification circuit. It is a circuit that does not employ an input gain adjustment amplifier in the configuration of FIG. 7, but converts the analog input signal AIN into a differential signal by the gain-adjusted non-inverting amplifier circuit 90 and inverting amplifier circuit 91. The result of simulating the phase characteristics of PSRR of the differential output terminals NOB and NOC in this circuit is shown in FIG. 10, and the result of simulating the PSRR characteristics is shown in FIG. It can be seen from FIG. 11 that the individual PSRR characteristics of the positive output terminal NOB and the negative output terminal NOC have the same tendency as in FIG. That is, with respect to the output NOB of the non-inversion amplifier circuit, it has a relatively good PSR.
R characteristics are shown, but PSRR is relatively high for the inverting amplifier circuit.
The characteristics are poor. Therefore, the negative output terminal NOC
In the differential output {(NOC)-(NOB)}, which is the difference between the output of the positive output terminal and the output of the positive output terminal NOB, the power supply noise components are not canceled with each other, and the overall PSRR characteristic is poor as in the case of FIG. Has become. In other words, the PSRR of the inverting amplifier circuit
The overall PSRR characteristic of the differential output is determined by the characteristic, and a good result cannot be obtained. From the simulation results of FIGS. 7 to 11, it can be said that in the pseudo-differential operational amplifier circuit using a plurality of operational amplifier circuits, the circuit symmetry cannot be obtained, and the noise component of the signal obtained at the differential output terminals is This means that it cannot be common noise. Therefore, even if the single-ended signal is differentiated, it is not possible to sufficiently cancel the noise component after that.

FIG. 12 shows an output waveform when the gain of the circuit of FIG. 1 is double. The negative output terminal NOM outputs a signal with the same phase and the same amplitude as the input signal, and the positive output terminal NOP outputs a signal with the same amplitude and the opposite phase as the input signal.
As a result, the differential signal, which is the difference between the output V (NOM) of the negative output terminal NOM and the output V (NOP) of the positive output terminal NOP, has a signal amplitude twice that of the input AIN, and noise is generated even in a low-voltage operation LSI. Since the signal amplitude can be made large with respect to the floor level, deterioration of S / N and the like can be suppressed to a minimum.

FIG. 13 shows an embodiment of a differential signal conversion circuit in which the gain of the fully differential operational amplifier circuit 4 is variable (soft selectable). The amplification factor can be changed by selecting the feedback point to the input terminal with the resistor string and analog switch. That is, the feedback point to the input terminal NM can be selected by closing any one of the analog switches S1M to SnM for the series resistance string R2M to RnM. Similarly, the analog switch S1 is connected to the series resistor string R2P to RnP.
The feedback point to the input terminal NP can be selected by closing any one of P to SnP. In the figure, the resistor R1
The resistance values of M to RnM and the resistances R1P to RnP are the same. With this circuit configuration, an A / D converter including a gain control function can be realized.

FIG. 14 shows an example of a circuit for converting a differential signal into a single end signal by using the fully differential operational amplifier circuit 4. By inputting the output of the positive output terminal NOP to the common-mode feedback input terminal CMF, it acts so that the potential of the opposite phase of the differential signal (that is, the potential of the output terminal NOP) becomes the analog signal ground, resulting in a negative output. The output of the terminal NOM can be converted into a single-ended output having the same phase as AINP and the same amplitude. The output of the negative output terminal NOM is A / D converted by an A / D conversion circuit (not shown). FIG. 15 shows the simulation result of the output waveform of the present single-ended output circuit.

FIG. 16 is a block diagram of a digital / analog mixed LSI in which the A / D converter 1 of the above embodiment is used. The LSI shown in the figure has a central processing unit (CPU) 13, a digital signal processor (DSP) 10, a direct memory access controller (DMAC) 11, a peripheral circuit 12 such as a random access memory. , Input / output circuit (I / O) 14,
The A / D converter 1 as one of the input / output circuits, the clock generation circuit (CPG) 15 and the like are formed on one semiconductor substrate such as single crystal silicon. The circuit block shown in the figure is connected to an address bus and a data bus (not shown), and operates under the control of the CPU 13 and the like.
In such a digital / analog mixed LSI, since the analog circuit and the digital circuit share the semiconductor substrate,
Analog circuits must operate in the noisy environment created by the operation of digital circuits. In such a case, in the noise environment of a large-scale high-speed digital circuit, A
In order to realize sufficient performance as an A / D converter, the A / D converter 1 of the present invention is applied.

FIG. 17 shows a system block diagram of a digital cellular (mobile terminal device for mobile radio).
This digital cellular includes a speech CODEC 20, a channel CODEC 21, a modem 22, an intermediate frequency section 23,
The high-frequency section 24 is provided, and each is implemented as an LSI. The speech CODEC 20 converts a voice signal into a digital signal and vice versa. Channel CODEC21
Performs multiplexing of digital signals supplied from the speech CODEC and demultiplexing of digital signals to be supplied to the speech CODEC. The modem 22 uses the channel CO
The digital signal supplied from the DEC is converted into an analog signal, and the analog signal supplied through the equalizer (EQ) 26 is converted into a digital signal. In FIG. 17, A indicates an analog signal and D indicates a digital signal. Speech CODEC 20 and modem 22 are analog front ends (AFE) that interface analog signals.
have. Speech CODEC 20 and modem 22
The A / D converter 1 according to the above-described embodiment is adopted in the above. The analog front end (AFE) of the modem is connected to the intermediate frequency section 23 and performs conversion between baseband and intermediate frequency. For example, the analog signal output from the modem 22 is converted into an intermediate frequency signal. High frequency section 24
Is a circuit for converting the intermediate frequency signal into a high frequency signal, converting the high frequency signal into an intermediate frequency signal, and inputting / outputting the signal as a radio wave to / from the antenna 25. Speech CODEC
20, channel CODEC 21, and modem 22
It is operated at a low voltage of 3.3V system. This makes this L
By applying the A / D converter 1 of the present invention to an A / D converter or the like used for SI, deterioration of analog characteristics can be suppressed to a small extent, and a particularly great effect can be expected.

FIG. 18 shows an embodiment of a differential A / D converter using the fully differential operational amplifier circuit 4. This differential A /
The D converter 40 has an analog positive input AI as a differential input.
NP and analog negative input AINM are supplied and
D / D converted digital positive output as differential output Dou
Obtain tP and the digital negative output DoutM. The configuration of FIG. 18 has the input capacitances CIP and CIM and the comparison circuits 43P and 4P.
3M, digital integrating circuits 42P, 42M, and local D
A / A converters 41P and 41M are individually provided on the positive input side and the negative input side, respectively, and the fully differential operational amplifier circuit 4 is applied to the analog integrator circuit 44, and the analog integrator circuit 44 is connected to the positive input side. It adopts a configuration in which processing and processing on the negative input side are shared. In the analog integration circuit 44, the integration capacitors CSP and CSM are equal, and the voltage dividing resistors RCP and RC are also included.
M is also made equal. The local D / A converters 41M and 41P are constituted by a switched capacitor type charge redistribution type using a capacitor array (CnM to C2P, C1M and C1P) and a resistor string (Rm to R1) for lower bits. The differential A / D converter 40 configured in this way is
It can be applied by replacing the A / D conversion circuits ADM and ADP.

FIG. 19 shows a layout example of MOS transistors which require the same characteristics, such as paired MOS transistors which form the differential stage of the fully differential operational amplifier circuit 4. In the figure, the pair MOS transistors M3 and M4 of FIG.
Are typically shown, and ND1, ND2, ND3, N
P and NM correspond to the symbols in FIG. The pair MOS transistors M3 and M4 are formed in pairs (in other words, in close proximity) to the single diffusion layer 50. Further, the size required for each of the transistors M3 and M4 is secured by forming a plurality of unit size transistors M3u and M4u. At this time, the unit size transistors M3u and M4u are regularly dispersed. Is formed. The source region formed in the diffusion layer 50 is indicated by S,
The drain region is indicated by D. 51 is a contact CNT
A wiring layer made of aluminum or the like, which is coupled to the drain region D of the transistor M3 via a contact CNT.
A wiring layer such as aluminum which is coupled to the drain region D of the transistor M4 via 53;
A wiring layer made of aluminum or the like, to which the source regions S of the transistors M3 and M4 are commonly connected via 54, a gate wiring forming a gate region (G) of the transistor M4, 5
Reference numeral 5 is a gate wiring forming a gate region (G) of the transistor M3. In this way, by arranging the paired MOS transistors close to each other in the distance and arranged regularly, the characteristics can be averaged. Therefore, the input offset of the fully differential operational amplifier circuit 4 and the like can be reduced by applying such a layout to other pair MOS transistors.

According to the above embodiment, there are the following effects. (1) The single-ended input analog signals are made into differential signals having opposite phases by the differential signal conversion circuit 6. The differential signal conversion circuit 6 configured by the fully differential operational amplifier circuit 4 uses, as common noise, noise components that are added to the analog input signal and the in-phase output signal and the anti-phase output signal, respectively. Then, each signal is converted into a digital signal by the A / D conversion circuits ADM and ADP, and then subtracted and converted into a single-ended digital signal, which is generated by a large-scale digital circuit or an input / output buffer circuit. Substrate noise is in-phase on the differential signal conversion circuit 6 and the respective A / D conversion circuits ADM and ADP. Therefore, such common noise and common-mode noise components are canceled by the final digital subtractor 5. As a result, it is possible to realize an A / D converter having a good S / N characteristic even if it is mounted together with many noise sources such as a large-scale digital circuit and an input / output buffer circuit. (2) The gain of the differential signal conversion circuit 6 is determined according to the ratio of the input resistance and the feedback resistance. By setting the ratio of the corresponding input resistance and feedback resistance of the differential signal conversion circuit 6 to 1: 1, the amplitude of the output differential signal with respect to the analog input signal can be halved with the analog signal ground as the center. Therefore, for example, even if the dynamic range of the input analog signal is full of the power supply voltage, the dynamic range can be reduced to half of the power supply voltage by differential operation, and analog signal processing using a normal operational amplifier becomes possible, improving noise resistance. That is, good S / N
The characteristics can be realized. (3) By setting the ratio of the input resistance and the feedback resistance of the differential signal conversion circuit 6 to 1: 2, the circuit 2 has a double gain and the analog differential output signal amplitude is doubled with respect to the input. In addition, since the signal amplitude range handled in the LSI does not change centering on the analog signal ground, LS of low voltage operation is possible.
Even with I, the dynamic range of the analog signal can be increased and the deterioration of the S / N characteristic can be improved. (4) As shown in FIG. 3, the MOS transistor M of the current source is used as the common-mode feedback input stage of the fully differential operational amplifier circuit.
10 and one input are connected to the analog signal ground and the other input is a common-mode feedback input terminal.
MOS transistor pair M8, M9 in which
And a differential stage composed of load MOS transistors M6 and M7 whose gates and drains are connected, and the output node (ND6) on the in-phase feedback input terminal side is the load MO of the input differential stage.
By adopting the configuration in which the S-transistor (M2) is connected to the gate, the number of transistors constituting the fully differential amplification arithmetic circuit 4 can be reduced. (5) As shown in FIG. 3, the fully differential operational amplifier circuit 4
Has a symmetry in circuit configuration between the circuit configuration on the positive output terminal NOP side viewed from the negative input terminal NM and the circuit configuration on the negative output terminal NOM side viewed from the positive input terminal NP. The noise component on the output can be regarded as common noise. (6) With respect to the MOS transistors forming the pair of differential stages included in the fully differential operational amplifier circuit 4, a plurality of MOS transistors each having a unit size are arranged in parallel to ensure a required transistor size. , Unit-size MOS that constitutes each pair of MOS transistors
The transistors are laid out in close proximity to each other and regularly distributed. As a result, the input offset in the fully differential operational amplifier circuit 4 can be reduced. This further increases the symmetry of the circuit. (7) Fully differential operational amplifier circuit 4 as shown in FIG.
Is used as an analog integrator circuit to form a pair of A / D conversion circuits 4
By configuring 0, it is possible to improve the resistance to external noise even in this portion. (8) Due to the above, it is possible to realize a differential A / D conversion circuit capable of minimizing deterioration of S / N characteristics even when it is mounted on an LSI that is mixed with a large-scale digital circuit even for low voltage operation. You can

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes. For example, the gain of the fully differential operational amplifier circuit is not limited to 1 and 2 and can be determined as appropriate. INDUSTRIAL APPLICABILITY The present invention is applicable to a microcomputer including an A / D conversion circuit whose signal dynamic range matches a power supply voltage, an A / D conversion circuit mounted in a large-scale digital circuit such as a digital signal processor, and the like. It can be widely applied.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by using the fully differential operational amplifier circuit, a differential signal conversion circuit with small distortion can be realized. That is, it is possible to use common noise as a noise component that rides on each of the in-phase output signal and the anti-phase output signal of the analog input signal. When A / D converting this differential analog signal,
Substrate noise and the like due to large-scale digital circuits in the vicinity are regarded as common-mode noise. Therefore, when the A / D-converted differential digital signal is digitally subtracted, the common-mode noise and common noise are canceled. This allows S /
It is possible to realize an A / D converter having good N characteristics.
Further, since the gain of the differential signal conversion circuit can be freely selected, the gain can be increased (the amplitude of the differential analog signal can be increased) at the time of low voltage operation to minimize the deterioration of the S / N characteristic. it can. Further, when the dynamic range of the input analog signal is such that the power supply voltage is full, the signal amplitude is compressed in reverse, so that a normal analog circuit such as an operational amplifier circuit can be used as a buffer amplifier.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an A / D converter according to the present invention.

FIG. 2 is a circuit diagram of another embodiment of the A / D converter according to the present invention.

3 is a circuit diagram of an embodiment of a fully differential operational amplifier circuit used in the differential signal conversion circuit of FIG.

FIG. 4 is a frequency characteristic diagram of the fully differential operational amplifier circuit of FIG.

5 is an output waveform diagram when the gain is 1 in the differential signal conversion circuit of FIG. 1. FIG.

6 is a PSRR characteristic diagram of the differential signal conversion circuit of FIG.

FIG. 7 is an explanatory diagram of a differential signal conversion circuit using a pseudo-differential operational amplifier circuit using a single-ended operational amplifier.

FIG. 8 is a PSRR characteristic diagram of the differential signal conversion circuit of FIG.

FIG. 9 is a circuit diagram showing an example in which a differential signal conversion circuit equivalent to that in FIG. 1 is realized by using two single-ended operational amplifiers as a non-inverting amplifier circuit and an inverting amplifier circuit.

10 is a PSRR of a differential output terminal in the circuit of FIG.
5 is an explanatory diagram of the result of phase simulation of FIG.

FIG. 11 is an explanatory diagram showing a result of PSRR characteristic simulation in the circuit of FIG. 9;

FIG. 12 is an output waveform diagram when the gain is doubled in the differential signal conversion circuit of FIG. 1.

FIG. 13 is a circuit diagram of an embodiment of a differential signal conversion circuit with variable gain.

FIG. 14 is an explanatory diagram of an embodiment of a single end output conversion circuit.

15 is an output waveform diagram of the single-ended output circuit of FIG.

FIG. 16 is a block diagram showing an example of an analog-digital mixed LSI using the A / D converter of the present invention.

FIG. 17 is a system block diagram of an example of digital cellular.

FIG. 18 is a circuit diagram of an embodiment of an A / D conversion circuit using a fully differential operational amplifier circuit.

FIG. 19 is an explanatory diagram showing an example of the layout of paired MOS transistors at the differential input stage in the fully differential operational amplifier circuit.

[Explanation of symbols]

 1 A / D converter 4 Fully differential operational amplifier circuit NM Negative input terminal NP Positive input terminal NOP Positive output terminal NOM Negative output terminal CMF Common mode feedback input terminal VB Analog signal ground 5 Subtraction circuit ADM, ADP A / D converter 6 Differential signal conversion circuit R1M, R1P Input resistance R2M, R2P Feedback resistance 8A, 8B Buffer amplifier 44 Analog integration circuit

Claims (8)

[Claims] 1. A differential signal conversion circuit having a fully differential amplifier circuit, wherein the fully differential operational amplifier circuit has a negative input terminal to which a single-ended analog signal is supplied via a first input resistance means. , A positive input terminal to which the analog ground potential is supplied via the second input resistance means, a positive output terminal connected to the negative input terminal via the first feedback resistance means, and the above-mentioned via the second feedback resistance means. A negative output terminal connected to the positive input terminal,
A positive output terminal and a positive output terminal, which are provided with a common-mode feedback input terminal to which a voltage formed based on the common-mode voltage of the negative output terminal is supplied, and which bring the input voltage of the common-mode feedback input terminal close to the analog signal ground. The voltage of the same phase between the negative output terminals is controlled to be constant, the signal of the same phase as the analog input signal is output to the negative output terminal, and the signal of the opposite phase of the analog signal is output to the positive output. Further, a pair of A / D conversion circuits that respectively input and analog-convert the differential analog signals output from the fully differential operational amplifier circuit included in the differential signal conversion circuit, and the pair of A An A / D converter comprising: a subtraction circuit that subtracts an output digital signal of the / D conversion circuit. 2. The ratio of the resistance values of the first input resistance means and the first feedback resistance means of the differential signal conversion circuit is 1: 1 and the resistance of the second input resistance means and the second feedback resistance means. A / D according to claim 1, characterized in that the ratio of the values is 1: 1.
converter. 3. The ratio of the resistance values of the first input resistance means and the first feedback resistance means of the differential signal conversion circuit is 1: 2, and the resistance of the second input resistance means and the second feedback resistance means. A / D according to claim 1, characterized in that the ratio of the values is 1: 2.
converter. 4. A local D / A conversion circuit for converting a digital signal into an analog signal by charge redistribution according to the state of a capacitance array, and the local D / A conversion circuit. An analog integrator circuit that integrates the difference between the output signal and the input analog input signal, and a comparator circuit that compares the value based on the integration result with a predetermined threshold value,
A digital circuit that forms the digital signal based on the comparison result, wherein the analog integrator circuits of the pair of A / D conversion circuits share a fully differential operational amplifier circuit, and the operational amplifier circuit includes:
Via the positive and negative input terminals for inputting the differential analog signal output from the differential signal conversion circuit, the negative output terminal which is feedback-connected to the positive input terminal via the first integrating capacitor, and the second integrating capacitor. A positive output terminal that is feedback-connected to the negative input terminal and a common-mode feedback input terminal that is supplied with a voltage that is formed based on the common-mode voltage of the positive output terminal and the negative output terminal. The voltage of the in-phase between the positive output terminal and the negative output terminal is controlled to be constant so that the voltage approaches the analog signal ground, the analog input signal and the signal of the same phase are output to the negative output terminal, and the positive output 2. A signal which is out of phase with the analog signal is output.
4. The A / D converter according to any one of items 1 to 3. 5. A single-ended signal converting circuit to which a fully differential amplifier circuit is applied, wherein the fully differential operational amplifier circuit has a negative input terminal to which an analog signal is supplied via a first input resistance means, and A positive input terminal to which an analog signal opposite in phase to the analog signal is supplied via the two-input resistance means, a positive output terminal connected to the negative input terminal via the first feedback resistance means, and a second feedback resistance. A negative output terminal connected to the positive input terminal via means, and a common-mode feedback input terminal supplied with the voltage of the positive output terminal, so that the input voltage of the common-mode feedback input terminal approaches the analog signal ground. Controlling the voltage of the positive output terminal such that the analog signal ground is output to the positive output terminal and the signal in phase with the analog signal is output to the negative output terminal. And an A / D conversion circuit for A / D converting by inputting a signal in phase with the analog signal output from the fully differential operational amplifier circuit included in the signal conversion circuit. And an A / D converter. 6. The fully differential operational amplifier circuit includes a MOS transistor of a current source, a pair of MOS transistors corresponding to positive and negative input terminals and having sources connected to each other, and a load MOS of the pair of MOS transistors. An input differential stage consisting of a transistor, a source ground amplifier circuit for amplifying the output of the input differential stage to form positive and negative outputs, an output of the source ground amplifier circuit and the input A phase compensation circuit connected in series with the output of the differential stage; and an in-phase feedback input differential stage, the in-phase feedback input differential stage including a current source MOS transistor and one of The input is connected to the analog signal ground,
It has a differential stage composed of a pair of MOS transistors whose sources are coupled to each other, the other input being a common mode feedback input terminal, and a load MOS transistor whose gate and drain are connected. 6. The A / D converter according to claim 1, wherein the output on the terminal side is connected to the gate of the load MOS transistor of the input differential stage. 7. A MOS transistor forming a pair of differential stages included in a fully differential operational amplifier circuit has a required transistor size secured by arranging a plurality of unit size MOS transistors side by side. Pair MO
7. The A / D converter according to claim 6, wherein the unit size MOS transistors forming the S-transistors are arranged close to each other in distance and regularly distributed. 8. An input differential stage comprising a MOS transistor of a current source, a pair of MOS transistors corresponding to positive and negative input terminals and having sources connected to each other, and a load MOS transistor of the pair of MOS transistors. A source ground amplifier circuit that amplifies the output of the input differential stage to form positive and negative outputs, and between the output of the source ground amplifier circuit and the output of the input differential stage. A phase compensation circuit including a capacitor and a MOS transistor resistance connected in series, and an in-phase feedback input differential stage are provided. The in-phase feedback input differential stage has a current source MOS transistor and one input. Connected to analog signal ground,
It has a differential stage composed of a pair of MOS transistors whose sources are coupled to each other, the other input being a common mode feedback input terminal, and a load MOS transistor whose gate and drain are connected. A fully differential operational amplifier circuit characterized in that the output on the terminal side is connected to the gate of a load MOS transistor in the input differential stage.