JPH06216327A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, where two semiconductor elements different in property are provided on the same semiconductor base, simply and in a small number of processes. CONSTITUTION:First, the lower part of the electrode 78b of the first semiconductor element 78b is formed. Next, a mask 87 (upper-layer mask) is formed, which has the first opening 82 which exposes an area wider than the topside of the lower part of this electrode 78, including this topside, and the second opening 84 which exposes the area where the electrode of the second semiconductor element is to be formed. Moreover, a film 88a for formation of the upper electrode of the first semiconductor element and a film 88b for formation of the electrode of the second semiconductor element are formed all over a semiconductor base where a mask having the first and second openings is already formed. Next, the masks 87 and 80b are removed, and also the film part 88c made on the mask is also removed. By such a process obviates the necessity to manufacture the first and second semiconductor element separately, and it can remarkably simplify the manufacture process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a field effect transistor (so-called FET) constituting an ultra high speed digital IC using a compound semiconductor or the like.

[0002]

2. Description of the Related Art Usually, a digital IC of this type is a DC
FL (Direct Coupled Field Ef)
It is known under the name of “Fact Transistor Logic”, and has a simple circuit configuration and low power consumption characteristics, and thus is a circuit configuration most suitable for an LSI of a GaAs integrated circuit (Reference I: “Super LSI”). Comprehensive Encyclopedia, "Science Forum, 1988, p31).

The circuit configuration and driving method of the DCFL will be briefly described below with reference to FIG.

The circuit diagram of FIG. 7 typically shows a part of a large number of arranged semiconductor devices.

In the figure, 10 is a depletion mode FET
(Also referred to as D-FET), 12 is an enhancement mode FET (also referred to as E-FET), 14 is a power supply voltage terminal, 16 is an input voltage terminal, 18 is an output voltage terminal, 20
Represents a wiring connection point.

The input terminal 16 is a gate of the E-FET.
Connected to the electrode. Also, the source of E-FET 12
The ground electrode is grounded 22. On the other hand, the drain electrode is connected to the source electrode of the D-FET 10, and
The drain electrode of the FET 10 is connected to the power supply voltage terminal 14.

The gate electrode of the D-FET 10 is connected to the output voltage terminal 18.

A wiring connecting the source / drain of the E / D type FET and a wiring connecting the gate electrode / output voltage on the D-FET 10 side are connected at a wiring connection point 20.

Next, a method of driving the DCFL circuit will be described.

When the input voltage V _in applied from the input voltage terminal 16 is at a level (L level) lower than the theoretical threshold value of the DCFL inverter, the E-FET which is a switching transistor is cut off (OFF state). Then, the D-FET 10 as the constant current source is turned on, but no current flows from the power supply voltage terminal 14 to the ground. At this time, the terminal 18
The output voltage V _{out at} is the negation of V _in , that is, a high level (H level).

[0011] On the other hand, when the input voltage V _in becomes the H level,
The E-FET becomes conductive (ON state), and the D-FET
Current passes through the E-FET and flows into the ground. At this time, the output voltage V _out at the terminal 18 becomes L level.

As an example of a conventional manufacturing method in which the upper part of the gate electrode of an E-FET is made larger than the lower part, reference I
I (“Enhancement-Node Pseudo
morphological Inverted HEMT fo
r Low Noise Amplifier ", Ka
zuhiko, Ohmura, al. IEEE, TRA
NSACTIONS ON MICROWAVE TH
EORY AND TECHNIQUES, Vol,
39, NO. 12, DECEMBER 1991).

8 and 9 are views for explaining steps of the E-FET having a mashroom type gate electrode disclosed in Document II.

First, the insulating film 32 is formed on the GaAs substrate 30.
After stacking the (SIN film), first and second resist patterns 34 and 36 are formed ((A) of FIG. 8). The film thickness of the second resist pattern 36 at this time is about 0.
It is about 5 μm.

Next, vapor deposition is performed at an inclination angle of 20 degrees with respect to the vertical axis to deposit a thin film of aluminum on the exposed surface of the SIN film 32. Due to such oblique deposition,
Aluminum (Al) with 2 μm wide slits
A film is obtained on the silicon nitride film 32 ((B) of FIG. 8).

Next, RIE (Re
A groove is formed in the SIN film 32 by using the active ion etching method or the like to partially expose the surface of the GaAs substrate 30 ((C) of FIG. 8).

Next, in order to change the FET to be formed into an E-FET, chlorine gas is used to ECR (Electron).
The first and second recesses 44 and 46 are formed by dry or wet etching using the Cyclotron Resonance method or the like ((A) of FIG. 9).

Next, using the second resist pattern 36 as a mask, metal deposition is performed using a deposition method or the like to form gate metal layers 48a and 48b (FIG. 9B).

After that, the gate metal layer 48b on the first and second resist patterns 34 and 36 and the second resist pattern is removed by the lift-off method to obtain the structure of FIG. 9C. The gate metal layer portion 49 remaining at this time becomes a gate electrode. In Document II, E-FE
Although the method of manufacturing T is described, there is no description of the method of forming the other D-FET. Therefore, in the conventional method, the DCFL is constructed by the two-step method of first forming the E-FET and then forming the D-FET.

[0020]

However, in the conventional DCFL manufacturing method, as described above, the E-FET (or D-FE) is first formed on the same GaAs substrate.
T) and then D-FET (or E-FE)
T) is formed. Therefore, there is a problem in that the number of steps in the manufacturing process is increased or the manufacturing is complicated.

An object of the present invention is to provide a method for easily manufacturing a semiconductor device having two semiconductor elements having different characteristics on the same semiconductor substrate with a small number of steps.

[0022]

In order to achieve this object, according to a method of manufacturing a semiconductor device of the present invention, a first semiconductor device having electrodes having an upper electrode width larger than a lower electrode width is formed on the same semiconductor substrate. In manufacturing a semiconductor device including one semiconductor element and a second semiconductor element having an electrode,
(A) a step of forming a lower portion of the electrode of the first semiconductor element; and (b) a first opening exposing a region wider than the upper surface including the upper surface of the lower portion of the electrode, and an electrode of the second semiconductor element. A step of forming a mask having a second opening that exposes a region to be formed, and (c) forming an upper electrode of the first semiconductor element on the entire surface of the semiconductor base on which the mask has been formed
The method is characterized by including a step of forming a thin film which also serves as an electrode of a semiconductor element, and (d) a step of removing the mask and a portion of the thin film on the mask.

Preferably, the mask has a lower mask having an opening exposing a surface of a lower portion of an electrode of the first semiconductor element and an opening exposing an electrode formation planned region of the second semiconductor element, and the first mask. An upper layer mask having an opening and a second opening is preferable.

[0024]

According to the method for manufacturing a semiconductor device of the present invention described above, two semiconductor elements, that is, a first semiconductor element and a second semiconductor element, are provided on the same semiconductor base, and the first semiconductor element side has a lower electrode width greater than the lower electrode width. A wide upper electrode width is formed.

First, the lower portion of the electrode of the first semiconductor element is formed. Therefore, the electrode length of the lower electrode of the electrode can be reduced in advance. Here, the electrode length is
When viewed in a sectional view shape, it refers to the electrode width.

A first opening is formed on the lower electrode, which includes the upper surface of the lower portion of the electrode of the first semiconductor element and exposes a region wider than the upper surface. Further, a mask having a second opening is formed in order to expose the electrode formation planned region of the second semiconductor element. By such a method, an upper electrode having a width larger than that of the lower electrode can be formed on the lower electrode by being joined to the first semiconductor element side in the subsequent process.

Further, the entire surface of the semiconductor base on which the mask has been formed is
The upper electrode forming thin film of the first semiconductor element is formed, and the electrode thin film is formed in the electrode formation planned region of the second semiconductor element.
Therefore, conventionally, the electrodes of the respective E / D type FETs have been formed separately, but according to this step, the upper electrode larger than the lower electrode of the first semiconductor element and the electrode of the second semiconductor element are simultaneously formed. can do.

Further, the mask and the metal thin film formed on the mask are removed. With such a method, it is possible to reduce the number of steps without going through many steps as in the conventional case. Further, this mask includes a lower layer mask having an opening exposing the surface of the lower portion of the electrode of the first semiconductor element and an opening exposing the electrode formation planned region of the second semiconductor element, and the first opening and the second opening. And an upper layer mask having

By using such two masks, the upper electrode of the first semiconductor element can form a mashroom type electrode and the electrode of the second semiconductor element can be formed at the same time.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device of the present invention, particularly an E-FET (enhancement type FET) and a D will be described below with reference to the drawings.
A structure of a semiconductor device having a -FET (depletion type FET) element will be described. In the actual manufacturing, a plurality of E-FETs and DFs are formed on the same semiconductor.
Have an ET. However, the embodiments of the present invention show only a part of them.

FIG. 6 shows an E-FET formed according to the present invention.
FIG. 3 is a cross-sectional view of a main part of a semiconductor device including a D-FET (hereinafter referred to as an E / D-type FET) and a D-FET. Each figure schematically shows the structure obtained in the main steps of this process in a sectional view to the extent that the present invention can be understood. In addition, this cross-sectional view is shown by paying attention to a cross-section cut perpendicular to the upper surface of the base and parallel to the channel direction. Further, here, the region having the upper layer and lower layer electrodes on the E-FET side is first
A region having an electrode on the D-FET side is referred to as a semiconductor device and a second semiconductor device is referred to.

In the figure, S. I. G
An aAs substrate is used. The electrode 90 of the first semiconductor element (first
Also called a gate electrode. ) Is formed by the lower electrode 78 b and the upper electrode 89. The width of the upper electrode 89 of the first electrode 90 is formed larger than that of the lower electrode 78b.

On the other hand, the electrode on the D-FET side (this is also referred to as the second gate electrode) has the same S.P.S. I. It is formed on the GaAs substrate 50. At this time, the channel thickness H2 of the second gate electrode 91 is formed larger than the thickness H1 of the first gate electrode 90.

Further, 52 is an AND-type GaAs buffer layer, 54 is an n-type GaAs channel layer, 56 is a first stopper layer, 58 is an n-type GaAs channel layer, 60 is a second stopper layer, and 62 is an n-type GaAs channel. Layer, 64 is n ⁺ G
The aAs contact layer, 66 represents an ohmic electrode, and 68 represents a semi-insulating layer.

Next, a method of manufacturing the semiconductor device used in the embodiment of the present invention will be described with reference to FIGS.

First, a semi-insulating GaAs substrate (hereinafter referred to as an SI GaAs substrate) is used as the base 50.
MBE method (Molecular Beam Epita)
xy) is used to evaporate the crystal constituent elements in an ultrahigh vacuum,
S. I. On the GaAs substrate 50, the AND-type GaAs buffer layer 52, the n-type GaAs channel layer 54, the first stopper layer 56, the n-type GaAs channel layer 58, the second stopper layer 60, the n-type GaAs channel layer 62 and the n ⁺ GaA.
The s contact layer 64 is sequentially epitaxially grown.
The material of the first and second stopper layers is, for example, Al.
_0.3 Ga _0.7 As and RIE (Reactive I
on Etching) method or the like to form a thin film of about 50 A (angstrom). In addition, n-type GaAs
First and second stopper layers 56 and 60 for adjusting recess etching are provided in the channel layers 54, 58 and 62 in order to set the threshold voltage of the E / D type FET to a predetermined value. Further, the channel region is arbitrarily masked (not shown) on the surface of the substrate 50, and then oxygen (O) is ion-implanted to form the semi-insulating layer 68. In this way, each semiconductor element is separated.

Then, using any suitable method, n ⁺ GaA
The ohmic electrode 66 is formed at a predetermined position on the surfaces of the s contact layer 64 and the semiconductor layer 68. The material of the ohmic electrode 66 used at this time is, for example, AuGe / Ni / A.
u ((A) of FIG. 1).

Next, a first resist pattern 70 having an opening 72 is formed to provide a partially exposed surface in the channel region of the E-FET. At this time, the width B1 of the top of the opening 72 is set to be the same as the predetermined channel width.

Then, using the first resist pattern 70 as a mask, the n ⁺ GaAs contact layer 64 and the n-type GaAs channel layer 62 exposed below the opening 72 are formed into a second layer.
Etching is performed until the surface of the stopper layer 60 is exposed.
The etching method at this time may be anisotropic etching such as RIE using CCl ₂ F ₂ gas. Further, by over-etching, the grooves are widened in the direction of the respective semiconductor layers 68 by a predetermined amount. The etching amount at this time is determined in consideration of the predetermined withstand voltage and the value of the source resistance. Further, the groove formed at this time is referred to as a first upper recess 74 ((B) of FIG. 1).

Next, the second stopper layer 60 exposed on the bottom surface of the first upper recess 74 is removed by wet etching or the like. Further, using the first resist pattern 70 as a mask, the n-type G exposed under the second stopper layer 60 is exposed.
The aAs channel layer 58 is etched to form a first layer.
A lower recess 76 is formed. The etching at this time is
It is preferable to use anisotropic etching. The etching depth is the depth up to the surface of the first stopper layer 56 (see FIG. 2).
(A)).

Next, the first stopper layer 56 exposed on the lower surface of the first lower recess 76 is removed by wet etching under any appropriate conditions. Further, the gate metal vapor deposition layer 78c and the lower electrode vapor deposition layer 78 are formed by the vapor deposition method or the like.
a is formed ((B) of FIG. 2). At this time, the width L1 of the vapor deposition layer 78a for the lower electrode has the same dimension as the width B1 of the opening 72.

Next, the first resist pattern 70 and the gate metal vapor deposition layer 78c are removed by any suitable chemical treatment to obtain the structure shown in FIG. At this time the first
The vapor deposition layer 78a for the lower electrode of the semiconductor element is the lower electrode 78
It becomes b.

The above-described steps from FIG. 1 to FIG. 3A are the usual E-FET manufacturing methods.

Next, the manufacturing process showing the features of the present invention will be described with reference to FIG.

A resist is applied to the entire surface of the structure formed in the step (A) of FIG. 3 (not shown), dried and cured, and the lower layer mask 8 is formed by exposure lithography or the like.
0a (also referred to as a lower layer resist pattern) is formed.
At this time, the lower electrode 78b on the E-FET side is covered with the lower layer resist pattern 80a. At this time, the lower layer resist pattern 80a is connected to the first upper recess 74 and the gate.
The metal vapor deposition layer 78a is formed so as to fill the gap.
The lower resist pattern 80a is formed so as to cover the entire lower electrode 78b of the first semiconductor element ((B) of FIG. 3).

Next, in order to expose the top of the lower electrode 78b, the upper surface of the lower resist pattern 80a is etched by, for example, the RIE method using oxygen gas. The lower layer resist pattern thus formed is called a lower layer resist pattern 80b (FIG. 4).

Next, in order to form an E / D type FET, E
An upper layer mask 87 (also called an upper layer resist pattern) having a first opening 82 on the −FET side and a second opening 84 on the D-FET side is formed. At this time, the first opening 8
2 is formed to have a width larger than that of the lower electrode. Each mask is composed of an upper layer mask and a lower layer mask. The lower layer mask has an opening exposing the surface of the lower electrode 78b portion of the first semiconductor element, and the upper layer mask has an opening exposing the electrode formation planned regions of the first and second semiconductor elements. First opening 82
And the second opening 84.

Next, the lower electrode 78b exposed in the first opening 82 on the E-FET side is used as a mask (not shown),
And using the upper resist pattern 87 as a mask, D-FE
N ⁺ GaA exposed below the second opening 84 on the T side
s contact layer 64 and n-type GaAs channel layer 62
Is etched to form a second recess 86. At this time, the etching depth is the depth up to the second stopper layer 60 ((A) of FIG. 5).

Next, wet etching is performed to remove the second stopper layer 60 exposed in the second recess 86. After that, the lower electrode region and the second electrode portion exposed downward from above the first and second openings 82 and 84.
Metal is vapor-deposited on the bottom surface of the recess 86. The metal vapor deposition at this time may be performed using a vapor deposition method or the like.

Thus, the upper electrode forming thin film 88a and the electrode forming thin film 88b are simultaneously formed on the lower electrode 78b and the bottom surface of the second recess 86, respectively. A gate metal thin film 88c is formed on the upper resist pattern 87 (FIG. 5B).

Then, the upper layer resist pattern 87, the lower layer resist pattern 80b and the gate metal thin film 88c are removed by the lift-off method or the like to obtain the structure shown in FIG. The E-FET side electrode thus formed becomes the first gate electrode 90, and the DFET side electrode is the second gate electrode 90.
Becomes the electrode 91. The upper part and the lower part of the first gate electrode 90 become the upper electrode 89 and the lower electrode 78b.

As can be understood from the above, according to the present invention, the E-FET and the D-FET are conventionally used.
Since it is not necessary to separately manufacture the above, the manufacturing process can be significantly simplified. Therefore, the manufacturing process can be reduced and the cost can be reduced.

Since the stopper layer composed of two layers is used, the thickness of the channel layer can be easily controlled. Therefore, the threshold voltage of the E / D type FET can be controlled accurately. Further, the first gate electrode of the E-FET has the width of the upper electrode larger than that of the lower electrode. Such a shape is also referred to as a mashroom type electrode. Therefore, the gate resistance is reduced, and the delay of the delay time due to the DCFL circuit configuration can be improved.

Further, the density of the current flowing through the gate electrode can be reduced by making the electrode of the E-FET into a mushroom type. Therefore, electro-migration
Is less likely to occur and disconnection of the gate electrode is remarkably improved.

The embodiment of the present invention is an E / D type FE.
Although the example of T has been described, the present invention is not limited to this, and can be applied to an electric element such as a semiconductor device including a diode and an FET. Further, in this embodiment, two stopper layers are provided in the semiconductor, but if the same characteristics are obtained, there is no problem even if these stopper layers are not used.

[0056]

As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention, first, the lower portion of the electrode of the first semiconductor element is formed. The width of the lower electrode formed at this time can be made smaller than the width of the upper electrode formed in a subsequent process. Therefore, the electrical characteristics such as the cutoff frequency characteristic f _T and the mutual conductance g _m on the side of the first semiconductor element can be improved.

A first opening including the upper surface of the lower portion of the electrode and exposing a region wider than the upper surface,
A mask having a second opening that exposes the electrode formation planned region of the second semiconductor element is formed. Since the first and second openings are formed in this manner, an upper electrode having a larger cross-sectional area than the lower electrode width can be formed on the first semiconductor element side in the next step. In addition, a predetermined recess can be formed on the same semiconductor base on the second semiconductor element side. Moreover, the respective electrode forming thin films can be formed simultaneously.

Further, a thin film for forming an upper electrode of the first semiconductor element and a thin film for forming an electrode of the second semiconductor element are formed on the entire surface of the masked semiconductor base having the first and second openings. By such a process, it is not necessary to separately manufacture the electrodes of the first and second semiconductor elements as in the conventional case, so that the manufacturing process can be significantly simplified.

Further, each mask is removed, and the thin film portion formed on the mask is also removed.

Through these steps, an electrode having an upper electrode width larger than the lower electrode width can be formed on the first semiconductor element side, and a predetermined electrode can be formed on the second semiconductor element side.

Therefore, according to the present invention, since the electrodes can be formed on the first and second semiconductor elements at the same time, the number of manufacturing steps can be remarkably reduced. Therefore, cost reduction can be achieved. In addition, the gate resistance and the current density can be reduced by changing the electrode of the first semiconductor element (making the cross-sectional area of the upper electrode larger than that of the lower electrode). Therefore, delay time or electro-migration
It is possible to remarkably improve the disconnection failure of the gate electrode due to the ionization.

The lower layer mask is provided on the first semiconductor element side with the surface of the lower portion of the electrode exposed. Furthermore, the upper layer mask is provided in a shape having a first opening and a second opening in the electrode formation regions of the first and second semiconductor elements. Therefore, a mashroom type upper electrode can be formed on the first semiconductor element side. A second recess and a second gate electrode may be formed on the second semiconductor element side.

[Brief description of drawings]

FIG. 1 is a process drawing for explaining an embodiment of the present invention.

2A and 2B are process drawings for explaining the embodiment of the present invention following FIG.

3A and 3B are process diagrams for explaining the embodiment of the present invention following FIG.

FIG. 4 is a process chart for explaining the embodiment of the present invention following FIG.

5A and 5B are process diagrams for explaining the embodiment of the present invention following FIG.

FIG. 6 is a process chart for explaining the embodiment of the present invention subsequent to FIG. 5;

FIG. 7 is a drive circuit diagram of a DCFL.

FIG. 8 is a process drawing for explaining a conventional gate electrode forming method.

FIG. 9 is a process diagram for explaining the conventional gate electrode forming method, which is subsequent to FIG. 8;

[Explanation of symbols]

50: S. I. GaAs substrate 52: AND-type GaAs buffer layer 54: n-type GaAs channel layer 56: first stopper layer 58: n-type GaAs channel layer 60: second stopper layer 62: n-type GaAs channel layer 64: n ⁺ GaA
s contact layer 66: ohmic electrode 68: semi-insulating layer 70: first resist pattern 72: opening 74: first upper recess 76: first lower recess 78a: vapor deposition layer for lower electrode 78b: lower electrode 78c : Gate metal vapor deposition layer 80a, 80b: Lower layer mask (lower layer resist pattern) 82: First opening 84: Second opening 86: Second recess 87: Upper layer mask (upper layer resist pattern) 88a: Upper electrode Forming thin film 88b: Electrode forming thin film 88c: Gate metal thin film 89: Upper electrode 90: First gate electrode 91: Second gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/812 7376-4M H01L 29/80 H

Claims (2)

[Claims] 1. A first semiconductor element having an electrode having an upper electrode width larger than a lower electrode width on the same semiconductor substrate.
In manufacturing a semiconductor device including a second semiconductor element having an electrode, (a) a step of forming a lower portion of the electrode of the first semiconductor element, and (b) an upper surface including an upper surface of the lower portion of the electrode. Forming a mask having a first opening that exposes a wider area and a second opening that exposes an electrode formation-scheduled area of the second semiconductor element; (c) over the entire surface of the semiconductor base on which the mask has been formed. A step of forming a thin film that also serves as an upper electrode of the first semiconductor element and an electrode of the second semiconductor element; and (d) removing the mask and removing a portion of the thin film on the mask. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the mask exposes an opening exposing a surface of a lower portion of an electrode of the first semiconductor element and an electrode formation planned region of the second semiconductor element. A method of manufacturing a semiconductor device, comprising a lower layer mask having an opening and an upper layer mask having the first opening and the second opening.