JPH06216149A - Manufacture for mos-type transistor - Google Patents

Abstract

PURPOSE:To make the manufacturing method easy and to facilitate the control of the lateral expansion of an impurity layer by implanting impurity atoms for forming a drain and a source after the formation of a gate, thereafter, etching the sidewall of the gate, and thereafter implanting impurity atoms for forming an impurity layer having the low concentration. CONSTITUTION:After the formation of a gate 23, impurity atoms for forming a drain 2 and a source 2 are implanted. Then, the sidewall of the gate 23 is etched. Thereafter, impurity atoms for forming an impurity layer 15 having the low concentration are implanted. For example, after an oxide film 4 is formed on an N-type silicon substrate, the gate 23 is formed in the larger size. Then, with the gate 23 as the mask, the P-type impurity atoms of about 10<15> atoms/cm<2> are implanted with the energy of about 70-100keV, and the source 1 and the drain 2 are formed. Then, the gate sidewall undergoes isotropic etching. Thereafter, with a reduced gate 3 as a mask, the P-type impurity atoms of about 10<14>atoms/cm<2> are implanted with the energy of about 50keV, and the impurity layer 15 is formed.

Description

Detailed Description of the Invention

[0001]

This invention relates to a gate, a drain,
The present invention relates to a method for manufacturing a MOS transistor having a source structure, particularly a MOS transistor having a structure intended to relax the electric field strength near the drain.

[0002]

2. Description of the Related Art FIG. 3 is a schematic sectional view of a conventional MOS transistor structure. 1 is a source, 2 is a drain, 3 is a gate, and 4 is an oxide film.
Is formed by implanting a gate 3 into a mask with a P-type or N-type impurity atom of about 10 ¹⁵ atoms / cm ² at an energy of about 70 to 100 KeV.
The oxide film 4 is made of polysilicon having a thickness of 0 to 6000 angstroms, a refractory metal or the like, and the silicon oxide film having a thickness of 100 to 300 angstroms. The lateral length of the gate 3, that is, the channel length l is usually several microns, but as the length l becomes shorter due to miniaturization, it becomes impossible to withstand the voltage applied between the drain 2 and the source 1. Due to the so-called punch-through phenomenon, insufficient withstand voltage occurs. This phenomenon is shown in FIG. In FIG. 4, the horizontal axis represents the channel length 1 and the vertical axis represents the maximum voltage value (BV _DS ) applied between the drain 2 and the source 1, which is usually B.
The l value at which the V _DS value decreases is 1 micron or less.

Currently, there are two types of methods for preventing a decrease in BV _DS value due to miniaturization of a MOS transistor by microfabrication. The first method is shown in FIG. In FIG. 5, the same symbols as those in FIG. The difference is that the length l ₁ of the gate 13 is made slightly larger than the length l of the gate 3 in FIG. 3, and the impurity layer 5 having a large diffusion coefficient, different from the source 1 and the drain 2, is implanted.

Explaining the N-channel MOS type transistor, for example, to form the source 1 and the drain 2,
Using the gate 13 as a mask, As of 10 ¹⁵ atoms / cm ²
(Arsenic) atoms are implanted with an energy of 70 KeV, while 10 ¹⁴ atoms / cm ² of P (phosphorus) atoms are deposited to 40 K with the same gate 13 as a mask to form the impurity layer 5.
Drive with eV energy. That is, in forming the impurity layer 5, the amount of impurity atoms is reduced as compared with the formation of the source 1 and the drain 2, and atoms having a large diffusion coefficient are used. The MOS type transistor using this method is a D.I. D. D (Do
uble Diffused Drain) called transistors, the thin layer of concentration diffuses laterally, forms a channel length l substantially equal to that of FIG. 3, the electric field strength of the drain 2 vicinity is relaxed, BV _DS value The drop is prevented.

Next, the second method is shown in FIG. In FIG. 6, the same symbols as those in FIG. 3 represent the same items, and the description thereof will be omitted. 6 is
It is called a sidewall and is made of oxide. Gate 3
Are formed to have the same dimensions as in FIG. 3, for example, and then atoms for forming the impurity layer 15 are implanted. Atoms may have a small diffusion coefficient.

Next, after forming the side wall 6, atoms for forming the source 1 and the drain 2 are implanted. These implantation amount and implantation energy are in accordance with the above-mentioned first method. The MOS type transistor using this method is described in
D. D. (Lightly Doped Drain)
It is called a transistor and has the same principle as the first method described above.
It is possible to prevent the V _DS value from decreasing.

[0007]

The first method D. D.
D. The transistor is the second method L.L. D. D. Compared with a transistor, the number of manufacturing steps is small and the manufacturing method is easy, but on the other hand, since the lateral spread length of the impurity layer 5 depends on the diffusion coefficient, there is a disadvantage that heating control is difficult. Second method L. D. D. The transistor is the same as the first method D.I. D. D. As compared with the transistor, the lateral spread length of the impurity layer 5 depends on the length of the sidewall 6,
Although it has the advantage of being easy to control, it has the problem that the number of manufacturing steps is large and the manufacturing method is complicated.

[0008]

The present invention has been proposed in view of the problem that the above manufacturing method is complicated. In the method of manufacturing a MOS transistor having a gate, drain and source structure, the drain is formed after the gate is formed. The impurity atoms for forming the source are implanted, the side wall of the gate is then etched, and then an impurity layer having a low concentration is formed.

[0009]

According to the present invention, it is possible to realize the manufacture of a transistor whose manufacturing method is simple and whose lateral spread of the impurity layer can be easily controlled.

[0010]

Embodiment An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, the same symbols as those in FIG. 3 represent the same items, and their explanations are omitted. As an order of steps, an oxide film 4 is first formed on an N-type (or P-type) silicon substrate, and then a gate 23 is formed. The gate 23 is made to have a gate length and a thickness that are larger than the finally required dimensions (FIG. 1-). Using the gate 23 as a mask, P-type (or N-type) impurity atoms of about 10 ¹⁵ atoms / cm ² are implanted at an energy of about 70 to 100 KeV to form a source 1 and a drain 2 (FIG. 1-).

Next, the gate sidewall is isotropically etched (see FIG. 1).
The gate 3 which has become smaller after setting to −) is used as a mask for about 1
The aforementioned atoms of 0 ¹⁴ atoms / cm ² are implanted with an energy of about 50 KeV to form the impurity layer 15 (FIG. 1-
). The impurity atoms used here may have a large diffusion coefficient.

[0013]

Second Embodiment FIG. 2 shows a second embodiment of the present invention. In FIG. 2, the same symbols as those in FIG. The difference from the first embodiment lies in the method of etching the gate sidewall. In the second embodiment, the gate length is formed to be larger than a desired size (FIG. 2-) After forming the source 1 and the drain 2 using the gate 33 as a mask (FIG. 2-), the resist 7 is applied to the gate 33 in a desired size. After (Fig. 2-), RIE (Re
Anisotropic etching is carried out by means of active Ion Etching) or the like, and the side wall of the gate 33 is etched to a desired size to form the gate 3 (FIG. 2). After that, the impurity layer 15 having a low concentration is formed using the gate as a mask.

[0014]

As described above, according to the present invention, the lateral spread length of the impurity layer 5 is determined by the length of the gate 3.
A transistor that is easy to control and easy to manufacture can be realized.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a conventional MOS transistor structure.

FIG. 4 is a relationship diagram between channel length 1 and BV _DS value.

FIG. 5 is a schematic sectional view of a first example of a conventional BV _DS value reduction prevention type.

FIG. 6 is a schematic cross-sectional view of a second example of a conventional BV _DS value reduction prevention type.

[Explanation of symbols]

 1 Source 2 Drain 3, 23, 33 Gate 4 Oxide film 7 Resist 15 Impurity layer with low concentration

Claims (3)

[Claims] 1. An M having a gate, a drain and a source structure.
In a method for manufacturing an OS transistor, a MOS transistor characterized by injecting impurity atoms for forming a drain and a source after forming a gate and then etching a side wall of the gate and then injecting impurity atoms for forming an impurity layer having a low concentration. Manufacturing method. 2. A method of etching the gate sidewall comprises:
The method for manufacturing a MOS transistor according to claim 1, wherein isotropic etching is performed. 3. The method of manufacturing a MOS transistor according to claim 1, wherein the method of etching the gate sidewall is anisotropic etching after forming a desired mask.