JPH06203579A - Output circuit and memory device - Google Patents

Abstract

PURPOSE:To recover a potential level of a signal input section at high speed by connecting a second auxiliary transistor for charging and a differentiating circuit to an input section of an inversion amplifier beside a first auxiliary transistor for charging. CONSTITUTION:When a potential variation state of an input section (in) of an inversion amplifier is detected by a differentiating circuit 11, a low potential level having a constant pulse width can be outputted to a (p) type FET TP1 (second auxiliary transistor for charging) for an instant. Thereby, a holding function of a potential level at the input section (in) is reduced in the (p) type FET TP1 (first auxiliary transistor for charging), and for potential recovery from an output 'L' level to a 'H' level, by sharing it to the differentiating circuit 11 and the FET TP2, even when the output 'L' level is read out, the output 'L' level can be read out at high speed.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field of the Prior Art (FIG. 6) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Action Example (1) Description of First Example (FIG. 2) (2) Description of second embodiment (FIG. 3) (3) Description of third embodiment (FIG. 4) (4) Description of application example (FIG. 5) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit and a memory device, and more particularly to an improvement of a sense amplifier circuit for outputting read data and a multiport RAM.

In recent years, various types of storage devices have been developed that statically read data from semiconductor integrated circuit (hereinafter referred to as LSI) devices, which are highly integrated and have a high density and are used by a user. For example, in a multi-port RAM having a large number of write / read ports, it becomes difficult to use a dynamic differential sense amplifier or the like of the conventional example, and a device for increasing the degree of integration by reducing the number of wirings and a device for the circuit of the RAM cell itself. Will be needed. In particular, when the differential sense amplifier cannot be used, it is necessary to devise to increase the access speed.

According to this, a sense amplifier circuit including a pre-stage amplifier circuit connected to a bit line, a charge assisting transistor, and an inverting amplifier circuit is devised, and the potential of the bit line is returned from low level to high level. , The input high level of which is turned on by the charge assisting transistor which is turned on based on the output low level of the inverting amplifier circuit.
I am at CC level.

However, when the method of adding the charge assisting transistor is adopted and the access speed of the output high level is to be increased, the driving ability of the charge assisting transistor must be increased. Therefore, this time, conversely, when reading the output low level, the drive capability of the output transistor of the pre-stage amplifier circuit must be designed to be sufficiently larger than the drive capability of the charging auxiliary transistor, and the output low level can be set at high speed. It becomes impossible to read.

Therefore, the function of holding the potential level of the bit line and returning the potential from the output low level to the high level is shared without depending on one charging auxiliary transistor, and the potential level of the bit line is maintained. There is a demand for a circuit and a device capable of achieving high speed recovery and improving the access speed.

[0007]

2. Description of the Related Art FIG. 6 is an explanatory diagram of a conventional sense amplifier circuit. 6A is its configuration diagram, FIG. 6B is an operation waveform diagram at the time of output high level, and FIG. 6C shows an operation waveform diagram at the time of output low level. There is.

For example, the RAM data DAT is applied to a multiport RAM (a memory that can be written / read at any time).
In FIG. 6A, the sense amplifier circuit for statically reading A (hereinafter simply referred to as data) comprises a pre-stage amplifier circuit 1, a charge assisting transistor (hereinafter simply referred to as p-type transistor) TP1, and an inverting amplifier circuit 2.

The front-stage amplifier circuit 1 is composed of a CMOS transistor circuit and a gate transistor TG, and Co is a stray capacitance of the bit line between the front-stage amplifier circuit 1 and the inverting amplifier circuit 2. The p-type transistor TP1 is connected to the power line V
It is connected between CC and the input section (bit line) in of the inverting amplifier circuit 2, and its gate is connected to the output section out of the inverting amplifier circuit 2.

With respect to the function of the sense amplifier circuit, first, the data supplied to the pre-stage amplifier circuit 1 is amplified by the CMOS transistor circuit and output to the inverting amplifier circuit 2 based on the reference clock CLK. As a result, the data is amplified and output by the inverting amplifier circuit 2. At this time,
In FIG. 6B, the potential of the bit line is due to a spontaneous charge state that depends on the stray capacitance Co parasitic on the bit line and the wiring resistance.

[0011]

By the way, according to the conventional sense amplifier circuit, as shown in FIG. 6A, the pre-stage amplifier circuit 1 and the p-type transistor TP connected to the bit line are connected.
1. The inverting amplifier circuit 2 is used to reset the potential of the bit line from the “L” level to the “H” level based on the output “L” (low) level of the inverting amplifier circuit 2.
The input "H" (high) level is set to the power supply line VCC level by the p-type transistor TP1 which performs N operation.

This is because when the output "H" level is read when the potential of the bit line is used as a reference, FIG.
As shown in (b), the potential drops by the threshold value Vth of the transistor T with respect to the level of the power supply line Vcc, and when it approaches that level, the transistor T becomes the OFF state, and the rising waveform of the signal becomes dull. come. As a result, the read access speed becomes slow because the level does not rise sufficiently and the rising waveform is slowed down.

In order to improve this, the p-type transistor TP1
The ON operation is performed based on the output “L” (low) level of the inverting amplification circuit 2 and the input “H” of the inverting amplification circuit 2 is turned on.
The (high) level is raised to the power supply line VCC level. In addition, when reading the output "L" level, FIG.
As shown in (c), no problem occurs. Also, FIG. 6 (b)
In the figure, the broken line shows the charging waveform when the p-type transistor TP1 is not provided.

However, when the method of adding the p-type transistor TP1 is adopted and the access speed of the output "H" level is to be increased, the driving ability of the p-type transistor TP1 must be increased. . Therefore, this time, conversely, a problem occurs when reading the output "L" level. That is, the driving capability of the n-type electric field transistor TN of the pre-stage amplifier circuit 1 for driving the potential of the bit line (hereinafter also referred to as a signal input section) to the output “L” level is a p-type transistor (hereinafter also referred to as a charging assist transistor). T
If it is not designed to be sufficiently larger than the drive capacity of P1, its output "L" level cannot be read at high speed.

Thus, in order to improve the access speed of the multiport RAM, the p-type transistor T
There is a conflicting problem that the drive capability of P1 cannot be designed too large.

The present invention was made in view of the problems of the conventional example, and holds the potential level of the signal input section and restores the potential from the output "L" level to "H" level by one. Provided is an output circuit and a storage device, which can share the function of the charge assisting transistor without depending on the charge assisting transistor, restore the potential level of the signal input portion at high speed, and improve the access speed. With the goal.

[0017]

[Means for Solving the Problems] FIGS. 1 (a) and 1 (b) are
3A and 3B respectively show principle diagrams of an output circuit and a storage device according to the present invention.

The first output circuit of the present invention, as shown in FIG. 1 (a), includes first and second charge assisting transistors TP1,
TP2, a differentiating circuit 11 and an inverting amplifier circuit 12 are provided, the first charge assisting transistor TP1 is connected between the power supply line Vcc and the input part in of the inverting amplifier circuit 12, and
The gate of the first charge assisting transistor TP1 is connected to the output section out of the inverting amplifier circuit 12, and the second charge assisting transistor TP2 is connected between the power supply line VCC and the input section in of the inverting amplifier circuit 12. And the gate of the second charge assisting transistor TP2 is connected to the output section out of the differentiating circuit 11.
And the input part in of the differentiating circuit 11 is connected to the input part in of the inverting amplifier circuit 12.

In the first output circuit of the present invention,
The differentiating circuit 11 comprises an inverter and a logic circuit,
The differentiating circuit 11 detects the potential change state of the input part in of the inverting amplifier circuit 12 to detect the second charge assisting transistor T.
It is characterized by outputting a low potential level with a constant pulse width to P2.

The second output circuit of the present invention is the first output circuit, wherein a signal delayed by an odd number of inverters connected in series with the differentiating circuit 11 and an input in of the inverting amplifier circuit 12 are provided. A logic output signal based on the supplied input signal is supplied to the gate of the second charge assisting transistor TP2.

Furthermore, the third output circuit of the present invention is the first output circuit, wherein the differentiating circuit 11 is delayed by the odd number of inverters connected in series and the signal delayed by the even number of inverters connected in series. And a logic output signal based on the generated signal is supplied to the gate of the second charge assisting transistor TP2.

In the first to third output circuits of the present invention, the reference clock CLK is provided in the preceding stage of the inverting amplifier circuit 12.
Is connected to a pre-stage amplifier circuit 13 for amplifying a signal based on

In the first to third output circuits of the present invention, the first and second charge assisting transistors TP1,
TP2 is a p-type field effect transistor,
Is characterized in that the driving ability of the charging assisting transistor TP1 is smaller than the driving ability of the second charging assisting transistor TP2.

Further, the storage device of the present invention comprises a storage element 14 for holding data D and a sense amplifier circuit 15 for reading and outputting the data D as shown in FIG. The above read control signal Rn [n =
1 to n], the sense amplifier circuit 15 is formed of the first to third output circuits of the present invention to achieve the above object.

[0025]

[Operation] According to the first output circuit of the present invention, FIG.
As shown in (a), the second charge assisting transistor TP2 and the differentiating circuit 11 are connected to the input part in of the inverting amplifier circuit 12 in addition to the first charge assisting transistor TP1.

Therefore, when the potential change state of the input part in of the inverting amplifier circuit 12 is detected by the differentiating circuit 11 including the inverter and the logic circuit, the second charge assisting transistor TP2 has a low potential with a constant pulse width. The level can be output for a moment.

That is, the input section in
Is detected, the first charge assisting transistor TP1 including a p-type field effect transistor is detected.
The "L" level is output to the second charge assisting transistor TP2, which has a larger drive capacity than the above, for a certain period of time, and the transistor TP2 turns on. That is, by designing the driving capability of the transistor TP2 to be large, it is possible to raise the potential to the level of the power supply line VCC sufficiently quickly even in the input section in with a heavy load.

When reading the "L" level,
Since the transistor TP2 performs the OFF operation, the driving of the "L" level by the output transistor of the pre-stage amplifier circuit 13 is not obstructed as in the conventional example, and the driving ability of the first charge assisting transistor TP1 is reduced. Can be designed.

As a result, the first charge assisting transistor TP1 is reduced to the function of holding the potential level of the input section in, and the potential of the output "L" level to "H" level is returned to the differentiation circuit. 11 and the second charge assisting transistor TP2 share the output "L".
Even when reading the level, the output “L” level can be read at high speed without forcing a design change of the driving capability of the output transistor of the pre-stage amplifier circuit 13 as in the conventional example.

According to the second output circuit of the present invention,
A logic output signal based on a signal delayed by an odd number of inverters connected in series with the differentiating circuit 11 and an input signal supplied to the input part in of the inverting amplifier circuit 12 is supplied to the gate of the second charge assisting transistor TP2. Supply.

Therefore, when the potential change state of the input section in of the inverting amplifier circuit 12 is detected by the differentiating circuit 11 similarly to the first output circuit, the second charge assisting transistor T is generated.
A low potential level with a constant pulse width can be momentarily output to P2.

For example, a two-input NAND is taken between the signal delayed by a circuit in which three inverters are connected in series and the input signal supplied to the input section in of the inverting amplifier circuit 12, and the output signal is obtained. Second charge assisting transistor T
Supplied to the gate of P2. As a result, as in the case of the first output circuit, the second charge assisting transistor TP2 is turned on, whereby the potential level of the input part in can be raised to the power supply line VCC level sufficiently quickly.

As a result, the function of holding the potential level of the input part in and returning the potential of the output from the "L" level to the "H" level without depending on the first charge assisting transistor TP1 is the second function. By sharing the charge assisting transistor TP2 with the charge assisting transistor TP2, it is possible to restore the potential level of the input portion at a high speed and to speed up the transistor operation.

Further, according to the third output circuit of the present invention, the differentiating circuit 11 outputs the signal delayed by the odd number of inverters connected in series and the signal delayed by the even number of inverters connected in series. A logic output signal based on the above is supplied to the gate of the second charge assisting transistor TP2.
For example, the threshold value of the first-stage inverter in which an odd number is connected in series and the threshold value of the first-stage inverter in which an even number are connected in series are made different, and the operation of the differentiating circuit 11 is set by the two types of threshold values.

Therefore, the input section in of the inverting amplifier circuit 12
The low potential level with a constant pulse width can be momentarily output to the second charge assisting transistor TP2 by the time difference when the rising signal of 1 reaches both thresholds.

As a result, similarly to the first and second output circuits, the first charge assisting transistor TP1 holds the potential level of the input section in and restores the potential from the output "L" level to "H" level. By sharing the function of the second charge assisting transistor TP2 without depending on, it is possible to restore the potential level of the input portion at a high speed and speed up the transistor operation. .

Further, according to the storage device of the present invention, FIG.
As shown in (b), the memory device 14 and the sense amplifier circuit 15 are provided, and the sense amplifier circuit 15 is the first embodiment of the present invention.
~ It comprises a third output circuit.

Therefore, the data D held in the storage element 14 is stored in one or more read control signals Rn [n = 1 to 1].
n], the read signal is output by the sense amplifier circuit 15 including the first to third output circuits of the present invention.

That is, the pre-stage amplifying circuit 13 connected to the preceding stage of the inverting amplifying circuit 12 outputs the data D held in the memory element 14 based on the read control signal Rn (reference clock CLK) to the first to third aspects of the present invention. Inversion amplifier circuit 1 of the output circuit
Output to 2. Here, when the differentiating circuit 11 detects the change state of the data D supplied to the input part in of the inverting amplifier circuit 12, a low potential level having a constant pulse width is momentarily output to the second charge assisting transistor TP2. can do.

As a result, the input section in is connected to the power supply line VCC.
The potential can be raised to the level, and the access speed of the multiport RAM or the like can be improved.

[0041]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 5 are diagrams illustrating an output circuit and a storage device according to an embodiment of the present invention.

(1) Description of First Embodiment FIG. 2 is a configuration diagram of a sense amplifier circuit according to the first embodiment of the present invention, and FIG. 2 (a) is a configuration diagram thereof. 2B is an operation waveform diagram of the differentiating circuit, and FIG. 2C is an operation waveform diagram of the sense amplifier circuit.

For example, a sense amplifier circuit which can be applied to a multi-port RAM and statically reads out data (DATA) is shown in FIG. 2A, in which first and second charge assisting transistors TP1 and TP2, a differentiating circuit 11, It comprises an inverting amplifier circuit 12 and a preceding amplifier circuit 13.

That is, the first charge assisting transistor (hereinafter referred to as p-type transistor) TP1 is composed of a p-type field effect transistor, the source of which is connected to the power supply line Vcc and the drain of which is the input portion of the inverting amplifier circuit 12. connected to in. The gate of the transistor TP1 is connected to the output section out of the inverting amplifier circuit 12. The driving capability of the p-type transistor TP1 may be designed smaller than that of the p-type transistor TP2. This is the output "L" of the inverting amplifier circuit 12 for the transistor TP1.
This is because the function of performing the ON operation based on the (“L”) level and holding the input “H” (high) level at the power supply line VCC level is relaxed.

Further, the second charge assisting transistor (hereinafter referred to as p-type transistor) TP2 is composed of a p-type field effect transistor, its source is connected to the power supply line Vcc, and its drain is the input part of the inverting amplifier circuit 12. connected to in. The gate of the transistor TP2 is connected to the output section out of the differentiating circuit 11.

The differentiating circuit 11 includes three inverters IN1 to IN1.
It is composed of N3 and one 2-input NAND circuit (hereinafter referred to as NAND circuit) 11A. The three inverters IN1 to IN3 are connected in series, and the input part in of the first-stage inverter IN1 is connected to the input part in of the inverting amplifier circuit 12. The output part of the final stage inverter IN3 is connected to one terminal of the NAND circuit, and the other terminal of the NAND circuit is connected to the input part in of the inverting amplifier circuit 12. As a result, by detecting the potential change state of the input section in of the inverting amplifier circuit 12, a low potential level with a constant pulse width can be output to the p-type transistor TP2.

The inverting amplifier circuit 12 is for inverting and amplifying and outputting data, and is, for example, a CMOS including a p-type field effect transistor and an n-type field effect transistor.
It consists of a transistor circuit. In addition, the pre-stage amplifier circuit 13
Is a CMOS transistor circuit including a p-type field effect transistor TP and an n-type field effect transistor TN, and a gate transistor T including an n-type field effect transistor. The data is inverted and amplified based on the reference clock CLK. To do. The inverting amplifier circuit 12 is connected to the latter stage of the front stage amplifier circuit 13.

As described above, according to the sense amplifier circuit of the first embodiment of the present invention, as shown in FIG. 2A, the input portion in of the inverting amplifier circuit 12 is provided with the other p-type transistor TP1. Is connected to the p-type transistor TP2 and the differentiating circuit 11.

Therefore, the inverters IN1 to IN3 and NA
When the potential change state of the input part in of the inverting amplifier circuit 12 is detected by the differentiating circuit 11 including the ND circuit 11A, a low potential level having a constant pulse width can be momentarily output to the p-type transistor TP2.

That is, in FIG. 2B, when the differentiating circuit 11 detects the rising of the input section in, p
The "L" level is output to the p-type transistor TP2, which is larger than the driving capability of the type transistor TP1, only for a certain period.
The transistor TP2 is turned on. That is, by designing the driving capability of the transistor TP2 to be large, the potential can be raised to the power supply line VCC level sufficiently quickly even in the input part in of the inverting amplifier circuit 12 having a heavy load as shown in FIG. It is possible (see FIG. 2 (c)).

Further, when the "L" level is read, the transistor TP2 performs an OFF operation, so that the n-type transistor TN of the preamplifier circuit 13 as in the conventional example.
No longer interferes with the driving of the “L” level by
The drive capability of the type transistor TP1 can be designed small.

As a result, the p-type transistor TP1 is reduced to the function of holding the potential level of the input section in,
The potential recovery from the output “L” level to the “H” level is shared by the differentiating circuit 11 and the p-type transistor TP2, so that even when the output “L” level is read out, the pre-stage amplification as in the conventional example. The output “L” level can be read at high speed without forcing a design change of the driving capability of the n-type transistor TN of the circuit 13.

(2) Description of Second Embodiment FIG. 3A is a block diagram of a differential circuit of a sense amplifier circuit according to a second embodiment of the present invention, and FIG. 3B shows its operation. Waveform diagrams are shown respectively.

The difference from the first embodiment is that in the second embodiment, the signal delayed by the two inverters IN1 and IN2 in which the differentiating circuit 21 is connected in series and the signal delayed by the three inverters IN3 to IN5 are delayed. The logic output signal based on the generated signal is supplied to the gate of the p-type transistor TP2.

That is, the differentiating circuit 21 comprises five inverters IN1 to IN5 and one two-input NAND circuit 11B. The two inverters IN1 and IN2 are connected in series, and the threshold value of the first-stage inverter IN1 is controlled to Vth1. The input part in of the inverter IN1 is connected to the input part in of the inverting amplifier circuit 12, and the final stage inverter I
The output part of N2 is connected to one terminal of the NAND circuit.

Further, the three inverters IN3 to IN5 are connected in series, and the threshold value of the first-stage inverter IN3 is controlled to Vth2. The input part in of the inverter IN3 is connected to the input part in of the inverting amplifier circuit 12, and the output part of the final stage inverter IN3 is connected to the other terminal of the NAND circuit. As a result, the potential change state of the input section in of the inverting amplifier circuit 12 is detected, that is, the low potential level having a constant pulse width corresponding to the time difference between the threshold values Vth1 and Vth2 of the first-stage inverters IN1 and IN3 is set to the p-type transistor TP2.
Can be output to.

As described above, according to the sense amplifier circuit of the embodiment of the present invention, as shown in FIG. 3A, the input signal supplied to the input section in of the inverting amplifier circuit 12 is applied to the differentiating circuit 21. Of the signals delayed by the two inverters IN1 and IN2 and the signals delayed by the three inverters IN1 to IN3 are p-type transistors TP2.
Is supplied to the gate.

Therefore, when the potential change state of the input section in of the inverting amplifier circuit 12 is detected by the differentiating circuit 21 like the first sense amplifier circuit, the p-type transistor TP2 has a low potential level with a constant pulse width. Can be output for a moment. That is, in FIG. 3B, when the rising edge of the input portion in is detected by the differential circuit 21 by both the first-stage inverters IN1 and IN3 having the threshold values Vth1 and Vth2, the p-type transistor TP2 having a larger driving capacity than that of the p-type transistor TP1 is detected. The low potential level (OUT) having a constant pulse width corresponding to the time difference between the threshold values Vth1 and Vth2 is set to the p-type transistor T.
It can be output to P2, and the transistor TP2 is turned on only for the certain period. From this, the inverting amplifier circuit 1
It is possible to raise the potential level of the second input portion in sufficiently quickly to the power supply line VCC level.

As a result, the function of the p-type transistor TP2 is shared by the p-type transistor TP1 without depending on the p-type transistor TP1 for holding the potential level of the input section in and for restoring the output potential from the "L" level to the "H" level. By doing so, the potential level of the input portion can be restored at high speed, and the speed of transistor operation can be increased.

(3) Description of Third Embodiment FIG. 4A is a block diagram of a differential circuit of a sense amplifier circuit according to a third embodiment of the present invention, and FIG. The operation waveform diagrams are respectively shown.

The third embodiment differs from the first and second embodiments in that the differentiating circuit 31 is composed of one inverter IN1 and one two-input NAND circuit 11C, and signal processing is performed there. The logic output signal is supplied to the gate of the p-type transistor TP2.

That is, the two-input NAND circuit 11C is composed of p-type field effect transistors TP11, TP12 and n-type field effect transistors TN11, TN12. The source / drain of the transistors TP11, TN11, TN12 are connected to the power supply line VCC. And ground line GND. Also,
The gate of the p-type transistor TP12 is connected to the ground line GND, its source is connected to the power supply line VCC, and its drain is connected to the common drain of the transistors TP11 and TN11 and connected to the gate of the p-type transistor TP2. The p-type transistor TP12 constitutes a pull-up resistor, and its resistance value R is set to a high resistance.

Further, the signal waveform of the input section in of the inverting amplifier circuit 12 is supplied to the common gate of the transistors TP11 and TN11, and the signal waveform is supplied to the gate G of the transistor TN12 via the inverter IN1. As a result, the potential change state of the input section in of the inverting amplifier circuit 12 can be detected by the differentiating circuit 31 including a small number of transistors.

In this way, according to the sense amplifier circuit of the third embodiment of the present invention, as shown in FIG. 4A, the differentiating circuit 31 has one inverter IN1 and one two-input. A NAND circuit 11C is provided, and a logic output signal based on the signal inverted by the inverter IN1 and the signal supplied to the input section in of the inverting amplifier circuit 12 is supplied to the gate of the p-type transistor TP2.

Therefore, the differentiating circuit 31 is connected to the inverter IN1.
And four transistors TP11, TP12, TN11, TN1
It is possible to achieve high integration of the sense amplifier circuit because it can be configured from 2. When the differentiating circuit 31 detects the potential change state of the input part in of the inverting amplifier circuit 12, the low potential level having a constant pulse width can be momentarily output to the p-type transistor TP2.

That is, in FIG. 4B, when the differentiation circuit 31 detects the rising of the input section in, the output level thereof becomes "L" level, but the output section of the differentiation circuit 31 is normally ON. The p-type transistor TP12 is connected, and due to its high resistance state, the output level gradually rises. Therefore, the rising signal is sufficiently "H"
The "L" level period until reaching the level is supplied to the gate of the p-type transistor TP1.

As a result, similarly to the first and second sense amplifier circuits, the p-type transistor TP1 depends on the holding of the potential level of the input section in and the return of the potential from the output "L" level to "H" level. By sharing the function of the transistor with the p-type transistor TP2, it is possible to restore the potential level of the input portion at high speed and to speed up the transistor operation.

(4) Description of Application Example FIG. 5 is a block diagram of a multiport RAM to which the sense amplifier circuit according to the embodiment of the present invention is applied.

For example, three read control signals RA to RC
A multi-port RAM that outputs RAM data (hereinafter simply referred to as "data") D on the basis of FIG.
25B to 25D and a word line selection transistor TW.

That is, the flip-flop circuit 24 is an embodiment of the storage element 14 and holds 1-bit data D. For example, the flip-flop circuit 24 is composed of two inverter elements.

The front stage amplifier section 25A and the rear stage amplifier section 25B constitute the sense amplifier circuit 15, and are composed of the sense amplifier circuits according to the first to third embodiments of the present invention.
The pre-stage amplifier section 25A comprises one inverter IN0 and three gate transistors TG1 to TG3. The source of the transistor TG1 is connected to the bit line BL1 (the upper bar is omitted) and the read control signal RA is used. And outputs the data D to the latter stage amplifier section 25B. The source of the transistor TG2 is connected to the bit line BL2, and outputs the data D to the post-stage amplifier section 25C based on the read control signal RB. Similarly, the transistor TG3 has its source connected to the bit line BL3, and outputs the data D to the post-stage amplifier section 25D based on the read control signal RC.

The word line selection transistor TW is
It consists of an n-type field effect transistor, the gate of which is connected to the word line and the source of which is connected to the bit line BL.

As described above, according to the multiport RAM according to the embodiment of the present invention, as shown in FIG. 5, the flip-flop circuit 24, the pre-stage amplifier section 25A, the post-stage amplifier sections 25B to 25D and the word line selection are selected. It includes a transistor TW, and the front stage amplifier section 25A and the rear stage amplifier sections 25B to 25D are the sense amplifier circuits according to the first to third embodiments of the present invention.

Therefore, the data D held by the flip-flop circuit 24 is transferred to the three read control signals R.
Based on A, RB and RC, the sense amplifier circuits according to the first to third embodiments of the present invention read out and output.

That is, when the read control signals (reference clocks CLK) RA, RB, RC are supplied to the front stage amplifier section 25A connected to the front stage of the inverting amplifier circuit 12, the flip-flops are flipped.
The data D held in the flop circuit 24 is output to, for example, the inverting amplifier circuit 12 of the sense amplifier circuit according to the first embodiment of the present invention. Here, in FIG.
When the differentiating circuit 11 detects the rising edge of the data D at the input part in, the p-type transistor TP2 having a larger driving capacity than the p-type transistor TP1 is output with the "L" level only for a certain period, and the transistor TP2 is turned on. do.

As a result, the input section i of the inverting amplifier circuit 12 is
It is possible to raise the potential of n to the level of the power supply line VCC, and it is possible to improve the access speed of the multi-port RAM or the like.

[0077]

As described above, according to the output circuit of the present invention, in addition to the first charge assisting transistor, the second charge assisting transistor and the differentiating circuit are connected to the input portion of the inverting amplifier circuit. To be done.

Therefore, when the potential change state of the input part of the inverting amplifier circuit is detected by the differentiating circuit composed of the inverter and the logic circuit, the second potential for charge assisting transistor is momentarily output a low potential level with a constant pulse width. You can
It is possible to raise the potential to the power supply line level sufficiently quickly even in an input section with a heavy load. Further, when the "L" level is read out, the transistor performs an OFF operation, so that the drive of the "L" level by the output transistor of the pre-stage amplifier circuit is not disturbed unlike the conventional example, and the first The driving capability of the charge assisting transistor can be designed small.

As a result, the holding of the potential level of the input portion of the inverting amplifier circuit and the return of the potential from its output "L" level to "H" level do not depend on the first charge assisting transistor, and its function is eliminated. Can be shared by the second charge assisting transistor, and the potential level of the input portion of the second charge assisting transistor can be quickly restored.

Further, according to the memory device of the present invention, it is provided with a memory element and a sense amplifier circuit, and the sense amplifier circuit comprises the output circuit of the present invention. Therefore, when the data held by the storage element is read out and output by the output circuit of the present invention based on one or more read control signals, the change state of the data supplied to the input section of the inverting amplifier circuit by the differentiating circuit is changed. When detected, a low potential level with a constant pulse width can be momentarily output to the second charge assisting transistor.

As a result, it is possible to speed up the transistor operation of the output circuit, and the multiport RAM
It greatly contributes to the improvement of access speed.

[Brief description of drawings]

FIG. 1 is a principle diagram of an output circuit and a storage device according to the present invention.

FIG. 2 is a configuration diagram and an operation waveform diagram of a sense amplifier circuit according to a first embodiment of the present invention.

FIG. 3 is a configuration diagram and an operation waveform diagram of a differentiating circuit of a sense amplifier circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram and an operation waveform diagram of a differentiating circuit of a sense amplifier circuit according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of a multiport RAM to which the sense amplifier circuit according to the embodiment of the present invention is applied.

FIG. 6 is an explanatory diagram of a sense amplifier circuit according to a conventional example.

[Explanation of symbols]

 11 ... Differentiation circuit, 12 ... Inversion amplification circuit, 13 ... Pre-stage amplification circuit, 14 ... Storage element, 15 ... Sense amplifier circuit, TP1, TP2 ... First and second charge assisting transistors, D ... Data, Rn [n = 1 to n] ... Read control signal.

Claims (5)

[Claims] 1. A first and second charge assisting transistor (TP1, TP2), a differentiating circuit (11) and an inverting amplifier circuit (12) are provided, and the first charge assisting transistor (TP1) is a power source. Is connected between the line (Vcc) and the input section (in) of the inverting amplifier circuit (12), and the gate of the first charge assisting transistor (TP1) is the inverting amplifier circuit (1).
2) is connected to the output section (out), the second charge assisting transistor (TP2) is connected between the power supply line (VCC) and the input section (in) of the inverting amplifier circuit (12), and ,
The gate of the second charge assisting transistor (TP2) is connected to the output section (out) of the differentiating circuit (11), and the input section (in) of the differentiating circuit (11) is the input section of the inverting amplifier circuit (12). An output circuit connected to (in). 2. The output circuit according to claim 1, wherein the differentiating circuit (11) comprises an inverter and a logic circuit,
The differentiating circuit (11) detects a potential change state of the input section (in) of the inverting amplifier circuit (12) and outputs a low potential level with a constant pulse width to the second charge assisting transistor (TP2). Output circuit characterized by. 3. The output circuit according to claim 1, wherein a pre-stage amplification circuit (13) for amplifying a signal based on a reference clock (CLK) is connected to a stage preceding the inverting amplification circuit (12). Output circuit. 4. The output circuit according to claim 1, wherein the first and second charge assisting transistors (TP1, TP2) are p-type field effect transistors, and the first charge assisting transistor (TP1). 2) is smaller than that of the second charge assisting transistor (TP2), the output circuit. 5. A storage element (1) for holding data (D)
4) and a sense amplifier circuit (15) for reading and outputting the data (D), and outputs the data (D) based on one or more read control signals (Rn [n = 1 to n]). In the memory device, the sense amplifier circuit (1
5) A memory device comprising the output circuit according to any one of claims 1 to 4.