JPH06202904A - Development support device - Google Patents

Abstract

PURPOSE:To detect in real time the local variable access action of a program produced in a C language. CONSTITUTION:An execution range detector 102 inputs each value of the memory address received in a memory access start, and the status, and the strobe showing the timing and decides whether the memory address under execution is kept or not in the range of a designated memory address. A memory access detector 103 inputs each value of the memory address, the status and the memory access data and the strobe and detects a memory access corresponding to the designated address. Then a register access detector 104 inputs the value of the memory address and each value of the register address, the status and the register access data which are received in a register access state and the strobe and holds the register access data to detect the coincidence with the memory address value when a writing action is carried out to a relevant general-purpose register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a development support device, and more particularly to a development support device for detecting a memory access to an address of a data area represented by an arithmetic expression of a base register and an offset value in a specific instruction.

[0002]

2. Description of the Related Art Conventionally, in a memory access detector in a development support apparatus, an address on a memory to be detected (hereinafter referred to as a comparison memory address) and data (hereinafter referred to as a comparison memory data) before executing a program. ) And a read or write status (hereinafter referred to as a comparison status, the above three are collectively referred to as a comparison parameter) are written in a memory access detector, and in the memory access detector, an address is sent from the E-CPU. Each time the data and status are output, a match with the previously written comparison parameter is detected. With this memory access detector, it is possible to detect a memory access to an address (hereinafter referred to as a static data address) of a data area known before the program is executed.
Global variables of programs written in C are
It is represented by a static data address and is used when debugging a program written in C language at the assembly language level.

FIG. 6 is a block diagram of an event detector of a conventional development support device for detecting a memory access to a static data address that occurs during execution of a specific range of a program. In FIG. 6, the E-CPU 30
1 is MA (15: 0), MSTS (n: 0), MDSTB (0: 0) and MD
It is a conventional emulation CPU with (7: 0) and also MA (15: 0), MSTS (ni0), MDSTB (0: 0) and MD above.
(7: 0) is an address bus for outputting an address at the time of memory access, a strobe for indicating a status at the time of memory access, a memory data access timing, and a data bus for outputting data at the time of memory access.

In the execution range detector 102, E-C
MA (15: 0), MSTS (n: 0) and MDSTB (0: from PU301
The value of (0) is input, and it is detected whether or not the currently executed address is within the specified address range, and the detection signal DTC1 (0: 0) is output. Here, the detection signal DTC1 (0:
0) becomes "H" level when the execution within the designated range is detected, and becomes "L" level when the execution is not detected. In the memory access detector 103, the E-CPU 30
Input MA (15: 0), MSTS (n: 0) and MD (7: 0) from 1 to detect memory access to the specified address and output detection signal DTC2 (0: 0). It The detection signal DTC2 (0: 0) becomes "H" level when the memory access is detected and becomes "L" level when the memory access is not detected. Further, in the AND operator 305, the logical product of the outputs of the execution range detector 102 and the memory access detector 103 is taken, and it is detected whether or not both outputs become "H" level at the same time. Output EVEN of AND operator 305
T OUT (0: 0) is the E-CPU 301 to be debugged
It is used as a trigger for stopping the execution of the program (hereinafter, referred to as a break) and acquiring an execution history (hereinafter, referred to as a trace). FIG. 7 is a block diagram showing an internal configuration of the execution range detector 102. In FIG. 7, a comparison upper limit address register 401 is a register for holding the upper limit address of the execution range to be detected, and its value is output to C-MA1 (15: 0) and the upper limit address comparator 40
Entered in 2. In the upper limit address comparator 402, the value of C-MA1 (15: 0) is compared with the value of MA (15: 0) output from the E-CPU 301, and MA (15: 0) ≤C. -MA
When it is 1 (15: 0), the output LEMA (0: 0) is at "H" level. Comparison lower limit address register 403
Is a register for holding the lower limit address of the execution range to be detected, and its value is output to C-MA2 (15: 0) and input to the lower limit address comparator 404. In the lower limit address comparator 404, the value of C-MA2 (15: 0) is compared with the value of MA (15: 0) output from the E-CPU 301, and MA (15: 0) ≧ C -If it is MA2 (15: 0),
The output GEMA (0: 0) becomes "H" level. In the AND operator 405, the LEMA (0: 0) and GEMA (0:
0) is ANDed with these LEMA (0: 0) and GEMA (0:
It is detected whether (0) has become "H" level at the same time (whether execution is within the specified range), and the logical product operation result is LD
It is output as (0: 0). Comparison status register 40
Reference numeral 6 is a register for storing the status to be compared with MSTS (n: 0). In this case, the fetch status Fetch is used to detect execution.
The status value corresponding to is written. The value is output to C-MSTS1 (n: 0). The status comparator 407 is a comparator for detecting a match between C-MSTS1 (n: 0) and M-STS (n: 0). When the status comparator 407 detects a match, it outputs an output. EQSTS1 (0: 0) is set to "H" level. In the AND operator 408,
This EQTSS1 (0: 0) is output from the E-CPU 301.
The logical product is obtained with MDSTB (0: 0) to detect whether or not the fetch operation is performed. And EQTSS1 (0: 0) is “H”
During the level, only when MDSTB (0: 0) is output from the E-CPU 301, LSTB1 (0: 0) output from the AND operator 406 becomes the “H” level. The execution range comparison result holder 409 uses the edge when the LSTB1 (0: 0) transitions from the “L” level to the “H” level as a latch strobe, and outputs LD (0:
This circuit holds the value of (0) and outputs it as DTC1 (0: 0) via LSTB1 (0: 0).

Next, a timing chart of the operation of the execution range detector 102 is shown in FIGS. 9 (a), (b), (c), (d), and FIG.
(E), (f), (g), (h), (i), (j),
Shown in (k), (l) and (m). This timing chart is a timing chart showing an example of the operation when detecting a memory fetch in the range of addresses 4000 to 4FFFh. In FIG. 9, C-MA1 (15: 0), C-MA2 (15: 0) and C-MSTS (n: 0) are values to be compared, and therefore do not change in the entire section. In the interval from T _{1 to} T ₂ , MA (15: 0) outputs address 31F0h and MS
Fetch is output from TS (n: 0). This T ₁ ~ T
_In section ₂ , MA (15: 0) <C-MA1 (15: 0),
Since MA (15: 0) <C-MA2 (15: 0), LEMA (0: 0) is at "H" level and GEMA (0: 0) is at "L" level. Since MSTS (n: 0) is Fetch, EQMSTS1 (0: 0) is at "H" level. MDSTB (0: 0) is “H” at T ₂
Since it is at the level, LSTB (0: 0) becomes the “H” level at T ₂ . At that point, LD (0: 0)
Is at "L" level, DTC1 (0: 0) is held at "L" level. In the section from T _{3 to} T ₄ , MA (15: 0) outputs address 4020h and MSTS.
Fetch is output from (n: 0). This T ₃ ~ T ₄
In the section of, MA (15: 0) <C-MA1 (15: 0) and MA (15: 0)> C-MA2 (15: 0), so LEMA (0: 0) and Both GEMA (0: 0) become "H" level, and LD (0: 0) 0 also becomes "H" level. Further, since MSTS (n: 0) is Fetch, EQMSTS1 (0: 0) is at "H" level. MDSTB (0: 0)
Is at "H" level at T ₄ , so LSTB
(0: 0) becomes "H" level at T _4. At that time, LD (0: 0) is at "H" level, so DTC1
(0: 0) is held in the "H" level state.

In the section of T _{5 to} T ₆ , address 5030h is output from MA (15: 0), and Fe from MSTS (n: 0).
tch is output. In the section from T _{5 to} T ₆ , MA (15: 0)> C-MA1 (15: 0) and MA (15: 0)> C-
Since it is MA2 (15: 0), LEMA (0: 0) is “L” level, GE
MA (0: 0) becomes "H" level, and LD (0: 0) 0 becomes "L" level. Also, since MSTS (n: 0) is Fetch, EQMS
TS1 (0: 0) is at "H" level. MDSTB (0: 0) is at “H” level at T ₄ , so LSTB (0: 0) is T
It becomes "H" level at ₄ . At that time, LD (0: 0) is at “L” level, so DTC1 (0: 0) is
The "L" level is newly retained from the "H" level retained until then.

FIG. 8 is a block diagram showing an internal structure of the memory access detector 103 shown in FIG. In FIG. 8, the comparison data register 501 is a register for holding the memory access data to be detected, and its value is output to C-MD (7: 0). Data comparator 50
Reference numeral 2 is a comparator for detecting a match between MD (7: 0) and C-MD (7: 0). A match between MD (7: 0) and C-MD (7: 0) is detected. In this case, the output EQMD (0: 0) becomes "H" level. The comparison status register 503 is a register for holding a memory access status to be detected, and a status value corresponding to read or write is written. The value is output to C-MSTS2 (n: 0). The status comparator 504 uses MSTS (n: 0) and C-MSTS.
This is a comparator for detecting a match of 2 (n: 0). When a match is detected, EQMSTS2 (0: 0) that is output becomes the “H” level. The comparison address register 505 is a register for holding a memory access address to be detected, and its value is output to C-MA3 (15: 0). The address comparator 506 is a comparator for detecting a match between MA (15: 0) and C-MA3 (15: 0), and a match between MA (15: 0) and C-MA3 (15: 0). When is detected, the output EQMA (0: 0) becomes the “H” level. The mask data register 507 is
This is a register for storing data for masking the comparison result of the bits compared by the address comparator 506 in bit units, and the value is output to MSKD (15: 0). By setting the bit of the mask data register 507, the comparison result of the corresponding bit is
It can always be a match. In the AND operator 508, EDMD (0: 0), EQMSTS2 (0: 0), EQMA (0: 0) and MDSTB (0 are output from the data comparator 502, the status comparator 504 and the address comparator 506, respectively. : 0) is ANDed and the "H" level is output as DTC2 (0: 0) only when all of these values are "H" level.

10 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
(K), (l) and (m) are timing charts showing the operation of the conventional memory access detector 103 when MSKD (15: 0) is 000h (no mask). Here, an example of detection when data FFh is written at address 8040h is shown. Figure 9
, C-MD (7: 0), C-MSTS2 (n: 0) and C-MAS3 (n:
0) is a value to be compared with each other and does not change in all sections. Since MSKD (15: 0) is also a fixed value, it does not change in all sections. MA in the section from T _{1 to} T ₂
Address 8040h is output from (15: 0), and MSTS
Write is output from (n: 0). In the T ₂ section, the data FFh is output from MD (7: 0). Since all the comparison results match only in this T ₂ section, EQMD (0: 0), EQMSTS2 (0: 0), EQMA (0: 0) are all at “H” level, and at the same time, the memory access detector 10
DTC2 (0: 0) output from 3 also becomes "H" level. T
_In the section from _{3 to} T ₄ , address 91 from MA (15: 0)
00h is output, and Write is output from MSTS (n: 0). In the T ₄ section, the data FFh is output from MD (7: 0). EQ in this T ₄ section
MD (0: 0), EQMSTS2 (0: 0), EQMA (0: 0) and EQMSTS2 (0:
0) is at "H" level, but EQMA (0: 0) is at "L" level, so DTC2 (0: 0) output from the memory access detector 103 remains at "L" level. .

11 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
In (k), (l) and (m), MSKD (15: 0) is FFFh.
FIG. 11 is a timing diagram showing an operation of the conventional memory access detector 103 at the time of (all bit mask). The difference from the case where MSKD (15: 0) shown in FIG. 10 is 000h is that the values of C-MA3 (15: 0) and MA (15: 0) are different in the T ₄ section. Regardless, DTC2 (0: 0) is “H”
This is the point that is output at the level. This is because the mask register is set as FFFh, so C-MA3 (1
This is because EQMA (0: 0) is always at "H" level regardless of the value of 5: 0).

Next, the execution range detector 10 shown in FIG.
2 and the memory access detector 103 are combined to detect a memory access to a static data address that occurs during execution of a specific range of the program, as shown in the program example of FIG. 12 and FIGS. 13 (a) and 13 (b). (C), (d),
(E), (f), (g), (h), (i), (j),
This will be described with reference to the timing diagrams of (k), (l), (m) and (n). FIG. 12 shows an example of a program in the Intel 8086 assembly language, which consists of two subroutines sub1 and sub2 and one data area data1. For simplicity, all instructions are 1-byte instructions here.

In FIG. 12, 1000 represents the address 1000h, which is an instruction to write 11h in the address 2000h (data1). Reference numeral 1001 represents address 1001h, which is an instruction to call address 1500h (sub2).
1002 represents address 1002h, and 2000h
This is an instruction to write FFh to the address (data1). Reference numeral 1003 represents address 1003h, which is a return instruction for returning to the calling source of the subroutine sub1. 1500 is 15
It represents address 00h and is the same as the instruction at address 1002h. 1501 represents the address 1501h,
This is a return instruction that returns to the calling source of the subroutine sub2. Reference numeral 2000 represents an address 2000h, which is a pseudo instruction for securing a data area. The detection condition is that FFh writing to address 2000h is detected during execution of the range from address 1000h to address 1003h. When the above conditions are set in each register,
C-MA1 (15: 0) is 1003h and C-MA2 (15: 0) is 1
000h, C-MSTS2 (n: 0) is Fetch, C-MA3 (15: 0) is 20
00h, C-MD (7: 0) becomes FFh, C-MSTS2 (n: 0) becomes Wite, and as shown in the timing chart of FIG. 13, all of these values are fixed values and their values do not change. .

In FIG. 13, the instruction at address 1000h is fetched in the section from T _{1 to} T ₂ . Here, since the condition of the execution range detector 102 is satisfied, the DTC1 (0: 0) output from the memory access detector 103 becomes T ₂ when MDTSB (0: 0) becomes “H” level.
After the section, it is held at "H" level. T ₃ ~
In the section of T ₄ , writing is performed to the address 2000h, but since the data becomes a condition, the output DTC2 (0: 0) of the memory access detector 103 remains in the “L” level. . In T ₅ through T ₆ intervals, 1
Since the instruction at address 001h has been fetched and the condition of the execution range detector 102 is satisfied also in this section, the output DTC1 (0: 0) of the memory access detector 103
Becomes "H" level. In the section of the T ₇ ~T _8,
150 because the instruction at address 1001h is a call instruction
0 address instructions are fetched, the output DTC1 memory access detector 103 in the section of the T _8: The value of (0 0) is held at "L" level. In the section from T _{9 to} T ₁₀ , writing is performed to the address 2000h and the data matches the condition of the memory access detector 103. Therefore, the output DT of the memory access detector 103 is
C2 (0: 0) becomes “H” level in the T ₁₀ section. T
In ₁₁ through T ₁₂ interval, instructions 1501h address are fetched, even in this period, the output of the memory access detector 103 DTC1 (0: 0) The value of the remains at "L" level. In the section of the T ₁₃ ~T _14, 1002h
Since the instruction of the address is being fetched and the condition of the execution range detector 102 is satisfied here, the output DTC1 (0: 0) of the memory access detector 103 is in the "H" level state. Held in. Further, in the section of the T ₁₅ through T _16, which is performed write to 2000h address, because the data is also consistent with the conditions for memory access detector 103, the output of the memory access detector 103 DTC2 (0: 0) becomes the “H” level in the T ₁₄ section, and the instruction at the address 1501h is fetched here, and the value of the output DTC1 (0: 0) of the memory access detector 103 is also “1” in this section. EVET OUT output from the AND operator 305 to reach the H "level
The level of (0: 0) becomes "H" level and the detection is completed.

[0013]

In the above-mentioned conventional development support device, although it is possible to detect a memory access to a static data address, since the comparison address register is static, the contents of the base register are programmed. It has a drawback that it changes during execution, and memory access detection cannot be set for dynamic data addresses.

[0014]

A development support apparatus of the present invention is a development support apparatus having a memory access detection function for program development, and an emulation CPU functioning as program development support and a memory from the emulation CPU. Input each value of the memory address and status output at the time of access, and the strobe indicating the timing of the memory access,
An execution range detector that detects whether or not the memory address that is currently being executed is within a specified memory address range, and a memory address, status, and memory access data output from the emulation CPU during memory access. A memory access detector that inputs each value and a strobe indicating the timing of the memory access to detect a memory access corresponding to a specified memory address, and a memory output from the emulation CPU at the time of memory access. When the address value, the register address output during register access, the status and register access data values, and the strobe indicating the timing of the register access are input and the target general-purpose register is written. To A register access detector holds the register access data detects a coincidence between the value of the memory address, configured with a least an event detecting means.

The register access detector outputs a comparison register address register for holding an address of a general-purpose register for which access detection is desired, a register address held in the comparison register address register, and the emulation CPU. From the emulation CPU, the register address comparator that compares the register address to detect a match, the comparison register status register that holds the register status to be compared, the comparison register status that is held in the comparison register status register, and the emulation CPU A register status comparator that compares the output register status with each other to detect a match, an output of the register address comparator, an output of the register status comparator, and the emulation CP An AND operator that takes a logical product of three outputs including a strobe indicating the timing of register access that is output from the emulation CPU, and a register that holds the register data output from the emulation CPU using the output of the AND operator as a latch strobe. A data holder, an offset data register for holding predetermined offset data, an offset data / register data adder for adding the value of the register holding latch of the register data holder and the value of the offset register, and An address comparator that compares the addition operation result of the offset data / register data adder with the memory address output from the emulation CPU to detect a match may be provided.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, RA (15: indicating the address of the register output from the E-CPU 101 at the time of register access from the E-CPU 301 shown in FIG.
0), RD (15: 0) indicating the register access data, RSTS (n: 0) indicating the read or write status, and RDSTB (0: 0) outputting the strobe of the register access timing are extracted. For signal lines other than the above, refer to E in FIG.
-Similar to the case of the CPU 301.

The execution range detector 102 and the memory access detector 103 are exactly the same as in the conventional example of FIG. The number of inputs to the AND operator 105 is three.
The function of the ND calculator 305 is exactly the same. In the register access detector 104, when the target general-purpose register is written, the register access data is held and compared with the address output from MA (15: 0) to match. To be detected. The match detection signal is output to DTC3 (0: 0).

FIG. 2 is a block diagram showing an internal configuration of the register access detector 104 shown in FIG. Figure 2
In, the comparison register address register 201 is a register that holds the register address of the register to be detected, and the value of the register address is output to C-RA (15: 0). In the register address comparator 202,
When C-RA (15: 0) and RA (15: 0) values are compared, a match is detected and the detection signal is output to EQRA (0: 0). In, the "H" level is output, and in the non-detection state, the "L" level is output. The comparison register status register 203 holds the access status for the general-purpose register to be detected. In this embodiment, since register access data is held by a change in the value of a general-purpose register (writing of a value), a status value corresponding to Write is always held. Then, this status value is output to C-RSTS (n: 0).

In the register status comparator 204, the values of C-RSTS (n: 0) and RSTS (n: 0) are compared and the coincidence detection is performed. The detection signal is output to EQRSTS (0: 0). When the register status coincidence is detected, "H" level is output, and when it is not detected, "L" level is output. In the AND operator 205, EQRA (0: 0) and EQRS
The logical product of TS (0: 0) and RDSTB (0: 0) is calculated, and the register set in the comparison register address register 201 is accessed with the status set in the comparison register status register 203. Timing (RDSTB
(0: 0)) is detected. As a result, only when the above three signals become "H" level at the same time, LSTB
"H" level is output to (0: 0). Further, the register data holder 206 holds the register access data from RD (15: 0), and latches the edge when LSTB (0: 0) transits from the “L” level to the “H” level. It is a stroop. And the register data holder 20
The value held in 6 is output to LRD (15: 0).

Offset data is held in the offset data register 207, and its value is OFSD.
It is output at (15: 0). In the offset data / register data adder 208, the values of LRD (15: 0) and OFSD (15: 0) are input and added, and the operation result is output to ADD (15: 0). In the address comparator 209, ADD (1
5: 0) and MA (15: 0) are compared and the detection signal is DTC.
It is output at 3 (0: 0). This DTC3 (0: 0) is output at "H" level when a match is detected, and is output at "L" level when no match is detected.

3 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
(K), (l), (m), (n) and (o) are timing charts showing the operation of the register access detector 104. In FIG. 3, in the section from T _{1 to} T ₂ , RA
0000h is output to (15: 0) and Write is output to RSTS (n: 0). At this point, EQRA (0: 0) and EQ
Both RSTS (0: 0) are at “H” level because the comparison conditions are satisfied. In the period of T ₂ , 8000h is output to RD (15: 0), and RDSTB (0: 0) becomes "H" level at the same time. Here, LSTB (0: 0) also becomes "H" level, RD (15: 0) at that time is held in the register data holder 206, and is also output to LRD (15: 0). At this point, the result of addition with the offset data is ADD.
It is output at (15: 0). MA (15: 0) in section T ₃
8040h is output to the DTC3 (0: 0), the DTC3 (0: 0) becomes the "H" level and the detection is completed.

Next, regarding the memory access detection for the address represented by the base register + offset during execution within the specified range, the program example shown in FIG. 5 and FIGS. 6 (a), 6 (b), and 6 (c) are shown. ), (D), (e),
(F), (g), (h), (i), (j), (k),
(L), (m), (n), (o), (p), (q),
It will be described with reference to the timing charts showing the operations of (r), (s), (t), (u), (v), (w) and (x).

In FIG. 4, 1000 represents the address 1000h, which is an instruction for writing the value of the sp (stack pointer) register into the bp register. 1001 represents the address 1001h, and data FFh is stored in the address represented by the value of the bp register and the offset value 10h.
Is a command to write. Reference numeral 1002 represents address 100h, which is an instruction for writing data FFh at address F010h. Reference numeral 1003 represents the address 1003h, which is a return instruction for returning to the calling source of the subroutine sub3. The detection condition is 1 from 1000h
It is assumed that FFh writing to the address represented by bp + 10h is detected during execution of the range of 100h.

When the above conditions are set in each register,
C-MA1 (15: 0) is 1100h and C-MA2 (15: 0) is 1 respectively.
000h, C-MSTS1 (n: 0) is Fetch, C-MD (7: 0) is FF
h, C-MSTS2 (n: 0) is Write, C-RA (15: 0) is the register address of bp register, C-RSTS (h: 0) is Write, OFSD (15: 0)
Is 0010h and MSKD (15: 0) is FFFFh. Here, C-MA3 (15: 0) may have any value because all bits are masked. In this case, FFFF
It is assumed to be h. In the timing chart of FIG. 5, since all the above values are fixed values, the values do not change in all sections.

In the section from T _{1 to} T ₂ , 10 in FIG.
The instruction at address 00 is fetched. In the section of T ₂
Since MDSTB (0: 0) becomes “H” level, the condition of the execution range detector 102 is satisfied here, and DTC1 (0: 0)
Becomes "H" level and its value is held. T ₃ ~ T
_In the section of ₄ , the value of the sp (stack pointer) register is read. In the T ₄ section where RDSTB (0: 0) becomes “H” level, actual reading is performed.
In T ₅ through T ₆ section, the value of the sp register read out earlier, is written to the bp register. Actual writing is performed in the T ₆ section where RDSTB (0: 0) is at “H” level. Here, the register access detector 1
Data written in register data holder 206 of 04
RD (15: 0) is held in the register data holder 206, and at the same time, is output as LRD (14: 0), and the offset data output from the offset data register 207 in the offset data / register data adder 208.
This is added to OFSD (15: 0) and ADD (15: 0) is output as the addition result.

In the section from T _{7 to} T ₈ , the instruction at address 100h is fetched. In this case, DTC1 (0: 0)
State remains at the "H" level. In the section from T _{9 to} T ₁₀ , the value of the bp register used in the calculation of bp + 10h of the instruction at address 1001 is read. T ₁₁ ~
In the section of T ₁₂ , the actual operation (writing to the memory) of the instruction at address 1001h is performed. At this time, bp
The register value is F000h, and the offset data in the program is 10h. Therefore, at this time point, data writing to the address F010h is being performed. Also, the MA output from the E-CPU 101 at this time
Since the value of (15: 0) matches the condition of the comparator 209 of the register address detector 104, the DTC3 (0: 0) output from the address comparator 209 becomes "H" level.

In the period of T ₁₂ , MDSTB (0: 0) becomes “H” level, so the memory access detector 10
3 output DTC2 (0: 0) becomes "H" level. At this time, DTC1 (0: 0), DTC2 (0: 0) and DTC3 (0: 0) are all "H" level. EVOUT (0: 0) output from the AND calculator 105 of 1 is output as “H” level, which indicates that the detection condition is satisfied. T ₁₃ ~
In the section of T ₁₄ , the instruction at address 1002h is fetched. In this section, the state of DTC1 (0: 0) remains at "H" level. In the section of the T ₁₅ through T _16, the actual operation of the instruction of 1002h address (writing to the memory) is carried out. In this case, the memory access address is written directly in the program, but bp + 1
Since it is equal to the address represented by 0h, the EVCUT (0: is similar to that at the time of executing the instruction at address 1001h (T _{11 to} T ₁₂ ).
0) becomes “H” level, which indicates that the detection condition is satisfied.

[0029]

As described above, according to the present invention, a real-time memory access to a dynamic data address represented by an arithmetic expression of a base register and an offset value such as a local variable of a program written in C language is performed. This has the effect of enabling detection.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a register access detector of the embodiment.

FIG. 3 is a timing diagram showing an operation of the register access detector.

FIG. 4 is a diagram showing an example of a program including a memory access instruction for a dynamic data address.

FIG. 5 is a timing diagram showing an operation when the register access detector is combined with the conventional execution range detector and memory access detector.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a block diagram showing an execution range detector of the conventional example.

FIG. 8 is a block diagram showing a memory access detector of the conventional example.

FIG. 9 is a timing chart showing an operation of the execution range detector of the conventional example.

FIG. 10 is a timing chart showing an operation of the conventional memory access detector.

FIG. 11 is a timing diagram showing an operation of the conventional memory access detector.

FIG. 12 is a diagram showing a program example including a memory access instruction for a static data address.

FIG. 13 is a timing chart showing an operation when the execution range detector and the memory access detector of the conventional example are combined.

[Explanation of symbols]

101, 301 E-CPU 102 execution range detector 103 memory access detector 104 register access detector 105, 205, 305, 405, 408, 508
AND operator 201 Comparison register address register 202 Register address comparator 203 Comparison register status register 204 Register status comparator 206 Register data holder 207 Offset data register 208 Offset data register data adder 209, 506 Address comparator 401 Comparison upper limit address Register 402 Upper limit address comparator 403 Comparison lower limit address register 404 Lower limit address comparator 406 Comparison status register 407, 504 Status comparator 409 Execution range comparison result holder 501 Comparison data register 502 Data comparator 503 Comparison status register 505 Comparison address register 507 Mask data register

Claims (2)

[Claims] 1. In a development support device having a memory access detection function for program development, an emulation CPU that functions as program development support, and memory address and status values output from the emulation CPU during memory access. When,
An execution range detector for inputting a strobe indicating the timing of the memory access and detecting whether or not the memory address currently being executed is within a specified memory address range; A memory access detector that detects the memory access corresponding to the specified memory address by inputting each value of the memory address, status, and memory access data output at the time of access and a strobe indicating the timing of the memory access. From the emulation CPU, a memory address value output at memory access, register address, status and register access data values output at register access, and a strobe indicating the timing of the register access are input. A register access detector that holds the register access data and detects a match with the value of the memory address when writing is performed to the target general-purpose register, and at least as a event detecting means. Characteristic development support device. 2. The register access detector, a comparison register address register holding an address of a general-purpose register for which access detection is desired, a register address held in the comparison register address register, and output from the emulation CPU. A register address comparator that compares a register address to detect a match, a comparison register status register that holds a register status to be compared, a comparison register status that is held in the comparison register status register, and the emulation CPU
Output from the register address comparator, output from the register status comparator, and the emulation CPU
AND operation unit for taking a logical product of three outputs including a strobe indicating the timing of register access outputted by the AND unit, and a register for holding the register data output from the emulation CPU using the output of the AND operation unit as a latch strobe. A data holder, an offset data register for holding predetermined offset data, an offset data / register data adder for adding the value of the register holding latch of the register data holder and the value of the offset register, 2. The development support apparatus according to claim 1, further comprising: an address comparator that compares the addition operation result of the offset data / register data adder with a memory address output from the emulation CPU to detect a match. .