JPH06202895A - Logic operation circuit - Google Patents

Abstract

PURPOSE:To provide a highly reliable logic operation circuit with high fail safety performance capable of judging both decision by majority and the fault of circuit by letting a binary input signal be a binary signal which is not mistaken as a logic value '1', adding it and converting it into a multilevel signal which is not mistaken on the side with the higher addition value. CONSTITUTION:The output end of a voltage doubler rectifier circuit 23 is connected to the earth terminal of a voltage doubler rectifier circuit 22. The output end of the circuit 22 is successively stacked up and connected toward the earth terminal of the circuit 21. The output voltages Va, Vb, and Vc of diodes D21-D23 for clamp use of the respective circuits 21 to 23 are added and obtained on an output terminal (a). A majority decision circuit 5 produces the output of decision by majority when two inputs or more are at the high level from among inputs given from A to C systems. A monitoring circuit 6, if one of logic operation oscillators 11-13 and rectifier circuits 21-23 has a fault in circuit, the level of the output end (a) can not keep Vc+Vb+Va, resulting in losing the monitoring output. In short, the fail safety performance can be secured for the fault of circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical operation circuit for performing arithmetic processing of each system in a multiple processing system.

[0002]

2. Description of the Related Art In a system in which a huge amount of damage or a serious accident is expected due to a system down, such as a railway, traffic control, plant, power plant, or telephone system,
A multiple processing system such as a triple system is used, and by taking a majority decision of this multiple processing system, even if one system fails, it is usual to prevent the system from going down by the principle of majority decision. In this case, the majority circuit must be configured as a fail-safe circuit that stops on the safe side when a failure occurs in itself. Known examples of such fail-safe logic operation circuits include, for example, the Institute of Electrical Engineers of Japan
There is "Development of a fail-safe computer system with an internal triple system" announced in 57-C11 (April 1982). FIG. 6 shows an outline of this known technique.
The outputs of the three asymmetric error logic operation oscillators 11 to 13 provided corresponding to the triple processing system of A to C are rectified by the voltage doubler rectifier circuits 21 to 23, and the majority output (2 out of 3).

When the system becomes a multiplex system of n units, logical operation oscillators 11 to 13 and voltage doubler rectifier circuits 21 to 23 are added correspondingly, and (n / 2) <m.
It is configured to produce a majority output when there are more than one input. The voltage doubler rectifier circuits 21 to 23 are diodes D
It is a general voltage doubler rectifier circuit including 11 to D13, D21 to D23 and capacitors C21 to C23. C11 ~ C
13 is a coupling capacitor.

FIG. 7 shows a concrete circuit example of the logical operation oscillators 11 to 13. In the figure, Q1 and Q3 are NPN
Type transistor, Q2 is PNP type transistor, R1 to R7
Is resistance. In this oscillator circuit, an input voltage Vin1 of Vin1> (R1 + R2 + R3) V / R3 is applied to the input terminal a, and V <Vin2 <(R6 + R7) V / R7 is satisfied at the input terminal b. It functions as an AND gate that oscillates when the input voltage Vin2 is applied. Logical operation oscillator 11-13
Is rectified by the voltage doubler rectifier circuits 21 to 23,
It is taken out as a rectified output. A window that oscillates at an input voltage Vin between (R1 + R2 + R3) V / R3 <Vin <(R6 + R7) V / R7 when the input voltage Vin is applied with the input terminals a and b in common. It becomes a comparator.

When the input terminals a and b are used independently, either the input voltage Vin1 or Vin2 is used, and when the input terminals a and b are used in common, the input voltage Vin is the above conditional expression. When not satisfied, and the operational oscillator 11
If any of the constituent elements (1) to (13) has a failure such as a disconnection or a short circuit, the oscillating operation of the logical operation oscillators (11 to 13) is stopped and a rectified output cannot be obtained. Double voltage rectifier circuit 21
The same applies to the case where a wire breakage failure occurs in Nos. 23 to 23. Therefore,
It is a fail-safe against A-C system circuit failure connected to the input terminals a and b and self circuit failure.

In the circuit shown in FIG. 7, when transistors Q1 to Q3 of NPN type and PNP type are exchanged with each other, a logical operation oscillator or window. A comparator can be configured. FIG. 8 shows a specific example thereof, which oscillates when an input voltage lower than the ground level is applied to the input terminals a and b.

In FIG. 6, binary input signals of the A to C systems are represented by Aε {1,0}, Bε {1,0}, Cε.
Let {1, 0}. Here, the logic value 1 is a logic level at which the logic operation oscillator can oscillate, and the logic value 0 is a logic level at which the logic operation oscillator cannot oscillate. In the logical processing shown in FIG. 6, when the output of the circuit is OUT1 ∈ {1, 0},
It is expressed by the following equation.

OUT1 = A · B∨B · C∨C · A (1) Here, the symbol · represents a logical product, and the symbol ∨ represents a logical sum.

Next, in the logic processing of FIG. 9, the output signal
OUT1 is expressed by the above formula (1), but when the output signals of the three logical operation transmitters match, that is, A, B, C =
1 and all output signals, ie, ¬A
The output signal OUT2 is as follows, assuming that the time when ¬B and ¬C = 1 is normal (logical value 1).

OUT2 = A · B · C ∨¬A · ¬B · ¬C (2) Here, the symbol · represents a logical product, and the symbol ¬ represents negation.

[0011]

By the way, this kind of logical operation circuit judges and outputs the coincident output of more than half of the information given from the n multi-systems without mistake, and outputs the incorrect operation. No output, match,
Accurately detect the mismatch, including the majority circuit itself,
It is necessary to have a function that can reliably detect a circuit failure and promptly report it. However, in the above-described known technique, even if the wired-OR input side fails, the failure cannot be recognized on the output side. As an example of detecting a failure on the output side, for example, as shown in FIG.
23 to a logical operation oscillator 3 that takes the logical product of the outputs of
A means for detecting a failure is also conceivable by providing a logical operation oscillator 4 that takes the logical product of the respective input signals given from the ~ C system, and detecting the match / mismatch of the outputs of the logical operation oscillators 3 and 4. For example, the logical expression of the expression (2)) cannot be detected even in this case when the voltage doubler rectifier circuits 21 to 23 on the majority output OUT1 side have a failure.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and to perform the multivalued arithmetic logic processing based on the difference of the addition levels, the state of information given from n multiplex systems, the majority decision, It is an object of the present invention to provide a highly reliable logic operation circuit having a high fail-safe property, which can execute a circuit failure judgment and the like.

[0013]

In order to solve the above problems, the present invention is a logical operation circuit having a plurality of input terminals to which a binary input signal is supplied, wherein the input signal is set to a logical value of 1. The error-free binary signal is added, and the binary signals are added and converted into an error-free multi-valued signal on the side where the added value is large, and then output.

[0014]

[Function] The input signal is a binary signal which is not mistaken for the logical value 1,
Since this binary signal is converted into a multi-valued signal by addition and is output, the state of the input signal, the majority decision, the circuit failure decision, etc. can be executed by the threshold value arithmetic logic processing based on the difference in the addition level. This is a multi-valued arithmetic process which is completely different from the conventional logic process represented by the above-mentioned equations (1) and (2).

Moreover, the input signal is not mistaken for the logical value 1 2
Since it is converted into a value signal and a binary signal is converted into a signal that does not err on the side of increasing the added value, in other words, a signal that only err on the side of decreasing the added value, the signal is fail-safe against circuit failure.

The logical operation circuit according to the present invention preferably has a circuit for converting a multi-valued signal into a binary signal which is not erroneously converted into a logical value 1 and outputting the binary signal. When such a circuit configuration is adopted, fail-safe multi-value operation can be performed again based on the output signal obtained by converting the multi-value signal into a binary signal that does not erroneously change to the logical value 1.

[0017]

1 is an electric circuit diagram of a logical operation circuit according to the present invention. The figure shows an example of a logical operation circuit embodied as a majority circuit. In the figure, the same reference numerals as those in FIGS. 6 to 9 denote the same components. In this embodiment, the voltage doubler rectifier circuits 21 to 23 connected to the asymmetrical error logical operation oscillators 11 to 13 described in FIGS. 7 and 8 are sequentially added with the voltage doubler rectified outputs Va to Vc. Connected to. That is, when the voltage doubler rectification output Vc of the voltage doubler rectifier circuit 23 is used as a reference, the voltage doubler rectification output terminal of the voltage doubler rectifier circuit 23 is connected to the ground terminal of the voltage doubler rectifier circuit 22, and the voltage doubler rectifier circuit 22 is doubled. The voltage rectification output terminal is sequentially stacked and connected to the ground terminal of the voltage doubler rectification circuit 21, and an addition output is obtained from the voltage doubler rectification output terminal (a) of the voltage doubler rectification circuit 21.

The circuit operation of a voltage doubler rectifier circuit is well known to those skilled in the art, and its basic function is to superimpose an AC input voltage on the anode potential of a clamping diode.

Next, the circuit operation of the voltage doubler rectifier circuit will be described with reference to FIGS. First, in FIG. 2, C1n
Is a coupling capacitor, D1n is a clamping diode, D2n is a rectifying diode, and C2n is a smoothing capacitor. When an AC voltage having a positive / negative peak value of Vn / 2 is input (see FIG. 3 (a)), the diode D1n becomes conductive in the negative cycle and the coupling capacitor C is connected.
1n is charged with the polarity shown. The charging voltage of the capacitor C1n is (Vn / 2), and the cathode terminal b of the clamping diode D1n becomes the ground potential.

Next, in the positive cycle, the voltage Vn obtained by adding the voltage (amplitude Vn) in the positive cycle to the charging potential (ground potential) of the coupling capacitor C1n is on the cathode side of the clamping diode D1n. Appears (Fig. 3
(See (b)). Then, at this time, the rectifying diode D2n becomes conductive, and the capacitor C2n is charged by the voltage Vn (see FIG. 3C). Therefore, the voltage doubler rectifier circuit superimposes the AC input voltage on the potential on the anode side of the clamping diode D1n.

In the embodiment, the voltage doubler rectifier circuits 21 to 23 having the circuit functions shown in FIGS. 2 and 3 are provided, and the voltage doubler rectifier output terminal of the voltage doubler rectifier circuit 23 is connected to the ground terminal of the voltage doubler rectifier circuit 22. However, since the voltage doubler rectification output terminal of the voltage doubler rectifier circuit 22 is sequentially stacked and connected to the ground terminal of the voltage doubler rectifier circuit 21, the cathode potentials of the clamping diodes 21 to 23 of each voltage doubler rectifier circuit 21 to 23 are connected. Are added to the output voltages of the other voltage doubler rectifier circuits 23 to 21, and the added output is obtained from the output terminal (a).

The capacitors C21 to C23 forming the voltage doubler rectifier circuits 21 to 23 act only as smoothing capacitors of the voltage doubler rectifier circuit to which they belong and are not charged via other voltage doubler rectifier circuits. Absent. For example, considering the A system as shown in FIG. 8, when the AC input voltage is in a negative cycle, the B system and C system voltage doubler rectifier circuits 2
Since the diodes D22, D12, D23 and D13 included in Nos. 2 and 23 become conductive and short-circuit the capacitors C22 and C23, the capacitors C22 and C23 can be ignored. A system is diode D22,
If the voltage drop due to D12, D23 and D13 is ignored, the anode side of the clamping diode D11 is kept at the ground potential. Ignoring the voltage drop of the diode D11, the cathode side potential becomes the ground potential. Then, as described with reference to FIGS. 2 and 3, the coupling capacitor C11 is charged to (Va / 2) with a predetermined polarity, and in the next positive cycle,
A voltage Va obtained by adding the voltage (Va / 2) in the positive cycle to the charging voltage (Va / 2) of the capacitor C11 appears on the cathode side of the clamping diode D11. Then, the rectifying diode D21 becomes conductive, the capacitor C21 is charged with the voltage Va, and the voltage Va appears at the output terminal (a).

Similar circuit operations are performed in the B system and the C system. That is, the voltage Vb appears at the output terminal (a) when the B system is alone, and the voltage Vc appears at the C system alone.

The voltage doubler rectification output terminal of the voltage doubler rectifier circuit 23 is connected to the ground terminal of the voltage doubler rectifier circuit 22, and the voltage doubler rectification output terminal of the voltage doubler rectifier circuit 22 is sequentially connected to the ground terminal of the voltage doubler rectifier circuit 21. Since they are stacked and connected, the output voltages Va, Vb, and Vc of the other voltage doubler rectifier circuits 23 to 21 are added to the cathode potentials of the clamping diodes 21 to 23 of the voltage doubler rectifier circuits 21 to 23, and the output terminals The addition output is obtained from (a). Therefore, Va <Vb + Vc <Va + Vb + Vc Vb <Va + Vc <Va + Vb + Vc Vc <Va + Vb <Va + Vb + Vc.

When all of the inputs given from the A to C systems are at a high level, the voltage doubler rectified outputs of the voltage doubler rectifier circuits 21 to 23 are at a high level V unless a circuit failure occurs.
c, Vb, and Va, and the added output at the output terminal (a) becomes a high level (Vc + Vb + Va), but A to C
When the input of a part or all of the system is lost, the voltage doubler rectification output Vc, V of the voltage doubler rectifier circuit corresponding to the system is lost.
Since b and Va become low level, the addition output at the output terminal (a) is reduced accordingly. For example, if the input of the A system is lost, the output of the voltage doubler rectifier circuit 21 becomes low level, and the added output level at the output end (a) is substantially lowered to (Vc + Vb).

The majority circuit 5 and the monitoring circuit 6 are connected to the output terminal (a). The majority decision circuit 5 and the monitoring circuit 6 operate as a level detector and are constituted by a logical operation oscillator. Especially the windows mentioned above. A comparator is suitable.

The majority circuit 5 produces a majority output OUT1 when two or more of the three inputs given from the A to C systems are at a high level. That is, the voltage doubler rectifier circuit 2
Oscillation occurs when the added output at the output terminal (1) of 1 is at a high level obtained by adding two or more doubled voltage rectified outputs among the three doubled voltage rectified outputs Vc, Vb and Va, and the majority output OUT1 is generated. . When the inputs of two of the A to C systems go to a low level, oscillation cannot be performed and the majority output OUT1 disappears.

Further, even if the inputs of two or more of the A to C systems are at a high level, due to a circuit failure of the logical operation oscillators 11 to 13 or the voltage doubler rectifier circuits 21 to 23, the output terminals (i.e. When the added output seen in) is below the level of one voltage doubler rectified output, the majority output OUT1 does not occur. Further, when the majority decision circuit 5 itself has a circuit failure, the logical operation oscillation operation stops and the majority decision output OUT1 disappears. Therefore, it is fail-safe against circuit failure.

The monitoring circuit 6 verifies whether or not the output level at the output end (a) is the addition output at the time of the high level of the AC systems. That is, in the monitoring circuit 6, the output level of the output terminal (a) is the high level output V of the voltage doubler rectifier circuits 21 to 23.
Level obtained by adding c, Vb, and Va (Vc + Vb + Va)
When it is at, it oscillates and generates monitoring output OUT2.
Logical operation oscillators 11-13 and voltage doubler rectifier circuits 21-2
If even one of the three causes a circuit failure, the level at the output end (a) cannot maintain (Vc + Vb + Va), and the monitoring output OUT2 disappears. In other words, the monitoring circuit 6 causes the logical operation oscillators 11 to 13 at the same time as the high-level mismatch.
And the failure of the voltage doubler rectifier circuits 21 to 23 is detected. In addition, monitoring output even when self-circuit failure occurs
Since OUT2 disappears, fail-safe property can be secured against circuit failure.

The logical processing of the logical operation circuit according to the present invention is as follows.
This is significantly different from the conventional logic processing represented by the equations (1) and (2). That is, the added value of the input signals of 1 is set to the logical value 1,
If the addition value of two input signals is set to a logical value 2 and the addition value of three input signals is set to a logical value 3 and is represented by a multivalued logical value,
The output signals OUT1 and OUT2 are expressed by the following equations.

When OUT1 = 1, when A + B + C> 10, when A + B + C = 1 or 0 (3) When OUT2 = 1, A + B + C = 3 When OUT2 = 0, A + B + C <3 (4) where the symbol + Means addition, and the result of the addition operation, that is, the output signal of the terminal (a) is a multi-valued signal having logical values of 0, 1, 2, 3.

The majority circuit 5 and the monitoring circuit 6 output the output signals OUT1 and OUT2 which are binary signals which are not mistaken for "1". Therefore, based on these output signals OUT1 and OUT2, both fail-safe output signals OUT1 and OUT2 are not present again (logical value 0), and only one of them is present (logical value 1). In some cases (logical value 2), a multivalued operation can be performed. For example, output signal OUT
The addition output signals of 1 and OUT2 are three values, and the logical expression OUT1 + OUT2 = 2 means that there is no circuit failure due to the output signal of 2 out of 3, and the logical expression OUT1 + OUT2 <2 is 2 out of 3 Means that there is no output signal of or there is an arithmetic circuit failure.

FIG. 5 shows another embodiment of the logical operation circuit according to the present invention. In this embodiment, the inputs from the A to C systems are branched in parallel at the input terminals of the logical operation oscillators 11 to 13 and input to the monitoring circuit 7, and the output of the monitoring circuit 7 and the output of the monitoring circuit 6 are wired. The OR output is used as the monitoring output OUT2.

The monitoring circuit 7 is a logical operation oscillator 71 which oscillates when all the inputs of the systems A to C are at a low level, that is, FIG.
It is configured by including the logical operation oscillator having the circuit configuration shown in FIG. The Zener diode Vz is connected to the ground point of FIG. 8 to give a ground potential, and the logical operation oscillator 71 is
It oscillates with a negative input (-V + Ez) lower than the Zener voltage Ez of the Zener diode Vz. 72 is a voltage doubler rectifier circuit. Therefore, the monitoring circuit 7 operates as a circuit that detects an input disagreement at a low level while the monitoring circuit 6 detects an input disagreement at a high level. Reference numeral 61 is a logical operation oscillator constituting the monitoring circuit 6, 62 is a voltage doubler rectifier circuit, and 81 to 83 are processing circuits for each of the A to C systems.

In the above embodiment, the triple system of A to C has been described as an example, but it goes without saying that the same can be applied to a multiple n system.

[0036]

As described above, according to the present invention, the following effects can be obtained. (A) Since the input signal is a binary signal that does not mistakenly have a logical value of 1, and this binary signal is converted into a multilevel signal and output, a multilevel based on a difference in addition level that is remarkably different from the conventional logic processing. It is possible to provide a logical operation circuit capable of executing the state of the input signal, the majority decision, the circuit failure decision and the like by the arithmetic logic processing. (B) The input signal is a binary signal that is not mistaken for a logical value of 1 and 2
Since the value signal is converted into a signal that is not erroneous on the side where the added value is large and is output, a fail-safe logic operation circuit can be provided against a circuit failure.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a logical operation circuit according to the present invention.

FIG. 2 is a diagram illustrating a circuit operation of a voltage doubler rectifier circuit.

3 is a waveform diagram of each part of the voltage doubler rectifier circuit shown in FIG.

FIG. 4 is a circuit diagram illustrating an operation of a logical operation circuit according to the present invention.

FIG. 5 is an electric circuit diagram of another embodiment of the logical operation circuit according to the present invention.

FIG. 6 is an electric circuit diagram of a conventional majority circuit.

FIG. 7 is an electric circuit diagram of an asymmetric error logic operation oscillator.

FIG. 8 is an electric circuit diagram of an asymmetric error logic operation oscillator.

FIG. 9 is an electric circuit diagram in another conventional example of a majority circuit.

[Explanation of symbols]

 11-13 Asymmetric error logic operation oscillator 21-23 Double voltage rectifier circuit 5 Majority decision circuit 6 Monitoring circuit

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[Procedure amendment]

[Submission date] July 15, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

FIG. 7 shows a concrete circuit example of the logical operation oscillators 11 to 13. In the figure, Q1 and Q3 are NPN
Type transistor, Q2 is PNP type transistor, R1 to R7
Is resistance. In this oscillator circuit, an input voltage Vin1 of Vin1> (R1 + R2 + R3) V / R3 is applied to the input terminal a, and V <Vin2 <(R6 + R7) V / R7 is satisfied at the input terminal b. It functions as an AND gate that oscillates when the input voltage Vin2 is applied (however, V is the power supply potential) . Outputs of the logical operation oscillators 11 to 13 are voltage doubler rectifier circuits 21 to 21.
It is rectified by 23 and taken out as a rectified output. A window that oscillates at an input voltage Vin between (R1 + R2 + R3) V / R3 <Vin <(R6 + R7) V / R7 when the input voltage Vin is applied with the input terminals a and b in common. It becomes a comparator.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

Next, regarding the conventional logic processing of FIG. 9,
When the logical expression is shown, the output signal OUT1 is expressed by the above expression (1) . When the output signals of the three logical operation oscillators match, that is, when A · B · C = 1, When all the output signals are 0, that is, when ¬A, ¬B and ¬C = 1, the output signal OUT2 is as follows, assuming normal (logical value 1).

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

By the way, this kind of logical operation circuit judges and outputs the coincident output of more than half of the information given from the n multi-systems without mistake, and outputs the incorrect operation. No output, match,
Accurately detect the mismatch, including the majority circuit itself,
It is necessary to have a function that can reliably detect a circuit failure and promptly report it. However, the above logical expression
In the known technology based on (1) and (2), even if the wired-OR input side fails, the failure cannot be recognized on the output side. As an example of detecting a failure on the output side, as shown in FIG. 9, for example, a logical operation oscillator 3 that takes the logical product of the outputs of the voltage doubler rectifier circuits 21 to 23 and the input signals of the A to C systems. A means for detecting a failure is also conceivable by providing a logical operation oscillator 4 that takes a logical product and detecting whether the outputs of the logical operation oscillators 3 and 4 are the same or not (the detection is, for example, the logical expression of equation (2)). .) But in this case,
When the voltage doubler rectifier circuits 21 to 23 on the side of the majority output OUT1 fail, this cannot be detected.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

Next, the circuit operation of the voltage doubler rectifier circuit will be described with reference to FIGS. First, in FIG. 2, C1n
Is a coupling capacitor, D1n is a clamping diode, D2n is a rectifying diode, and C2n is a smoothing capacitor. When an AC voltage having a positive / negative peak value of Vn / 2 is input (see FIG. 3 (a)), the diode D1n becomes conductive in the negative cycle and the coupling capacitor C is connected.
1n is charged with the polarity shown in FIG. The charging voltage of the capacitor C1n is (Vn / 2), and the clamping diode D
The cathode terminal b of 1n has a ground potential.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

Next, in the positive cycle, the voltage Vn obtained by adding the voltage (amplitude Vn) in the positive cycle to the charging potential ( point b; earth potential) of the coupling capacitor C1n is on the cathode side of the clamping diode D1n. It appears at a certain point b (see FIG. 3 (b)). Then, at this time, the rectifying diode D2n becomes conductive, and the capacitor C2n is charged by the voltage Vn (see FIG. 3C). Therefore, the voltage doubler rectifier circuit superimposes the AC input voltage on the potential on the anode side of the clamping diode D1n.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

In the embodiment, the voltage doubler rectifier circuits 21 to 23 having the circuit functions shown in FIGS. 2 and 3 are provided, and the voltage doubler rectifier output terminal of the voltage doubler rectifier circuit 23 is connected to the ground terminal of the voltage doubler rectifier circuit 22. However, since the voltage doubler rectification output terminal of the voltage doubler rectifier circuit 22 is sequentially stacked and connected to the ground terminal of the voltage doubler rectifier circuit 21, the output signal of the voltage doubler rectifier circuit 22 is doubled.
Clamping diode D is added to the output signal of the voltage rectifier circuit 23.
Output signal of the voltage doubler rectifier circuit 21
Is a clamp diode for the output signal of the voltage doubler rectifier circuit 22.
Add using D11 and add from the output terminal (a)
A force terminal is obtained. No output signal is output to the voltage doubler rectifier circuit 22.
If not, clamp diode D11 and rectifier diode
Doubled via the diode D22 and the clamp diode D12
It is added to the output signal of the pressure rectification circuit 23.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

The capacitors C21 to C23 forming the voltage doubler rectifier circuits 21 to 23 act only as smoothing capacitors of the voltage doubler rectifier circuit to which they belong and are not charged via other voltage doubler rectifier circuits. Absent. For example, considering the A system as shown in FIG. 4 , when the AC input voltage has a negative cycle, the B system and C system voltage doubler rectifier circuits 2
Since the diodes D22, D12, D23 and D13 included in Nos. 2 and 23 become conductive and short-circuit the capacitors C22 and C23, the capacitors C22 and C23 can be ignored. A system is diode D22,
If the voltage drop due to D12, D23 and D13 is ignored, the anode side of the clamping diode D11 is kept at the ground potential. Ignoring the voltage drop of the diode D11, the cathode side potential becomes the ground potential. Then, as described with reference to FIGS. 2 and 3, the coupling capacitor C11 is charged to (Va / 2) with a predetermined polarity, and in the next positive cycle,
A voltage Va obtained by adding the voltage (amplitude Vn ) in the positive cycle to the charging voltage (ground potential) of the capacitor C11 appears on the cathode side of the clamping diode D11. Then, the rectifying diode D21 becomes conductive, the capacitor C21 is charged with the voltage Va, and the voltage Va appears at the output terminal (a).

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

The voltage doubler rectification output terminal of the voltage doubler rectifier circuit 23 is connected to the ground terminal of the voltage doubler rectifier circuit 22, and the voltage doubler rectification output terminal of the voltage doubler rectifier circuit 22 is sequentially connected to the ground terminal of the voltage doubler rectifier circuit 21. Since they are stacked and connected, the clamping diodes D11 to D1 of the voltage doubler rectifier circuits 21 to 23, respectively.
3 is used to output the output voltages Va and V of the higher voltage doubler rectifier circuit.
b is a logical level of Vc, Vc + Vb, Vc + Vb + Va
And output as an addition output signal from the output terminal (a). Therefore , the logic level is Va <Vb + Vc <Va + Vb + Vc Vb <Va + Vc <Va + Vb + Vc Vc <Va + Vb <Va + Vb + Vc.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

The majority circuit 5 and the monitoring circuit 6 output the output signals OUT1 and OUT2 which are binary signals which are not mistaken for "1". Therefore, based on these output signals OUT1 and OUT2, both fail-safe output signals OUT1 and OUT2 are not present again (logical value 0), and only one of them is present (logical value 1). In some cases (logical value 2), it has the feature of being able to perform multivalued operations. For example, the summed output signal of output signals OUT1 and OUT2 has three values, and the logical expression OUT1 + OUT2 = 2 means that there is no circuit failure in the output signal of 2out of 3, and the logical expression OUT1 + OUT2 <2 is It means that there is no output signal of 2 out of 3 or that an arithmetic circuit failure has occurred.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

The monitoring circuit 7 is a logical operation oscillator 71 which oscillates when all the inputs of the systems A to C are at a low level, that is, FIG.
It is configured by including the logical operation oscillator having the circuit configuration shown in FIG. The Zener diode Vz is connected to the ground point of FIG. 8 to give a ground potential, and the logical operation oscillator 71 is
It oscillates with a negative input (-V + Vz ) lower than the Zener voltage (Vz) of the Zener diode Vz. 72 is a voltage doubler rectifier circuit. Therefore, the monitoring circuit 7 operates as a circuit that detects an input disagreement at a low level while the monitoring circuit 6 detects an input disagreement at a high level. Reference numeral 61 is a logical operation oscillator constituting the monitoring circuit 6, 62 is a voltage doubler rectifier circuit, and 81 to 83 are processing circuits for each of the A to C systems.

[Procedure Amendment 11]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

Claims (2)

[Claims] 1. A logical operation circuit having a plurality of input terminals to which a binary input signal is supplied, wherein the input signal is a binary signal in which a logical value of 1 is not mistaken, and the binary signals are added and added. A logical operation circuit that converts to a multi-value signal and outputs it without error on the side of increasing values. 2. A logical operation circuit having a circuit for converting the multi-valued signal into a binary signal that does not erroneously have a logical value of 1 and outputting the binary signal.