JPH06202856A - Random sequence generation processing system for parallel computer system - Google Patents

Abstract

PURPOSE:To generate a long-cycle random sequence having different arrangement at high speed by generating the random number sequence at each processor element according to M series of random sequence generating methods. CONSTITUTION:S random number initial value generating means 10 of a master processor element 1 generates (pxvxk) pieces of initial values of random numbers, and a random number initial value distributing means 11 distributes the (pxv) pieces of random number initial values to a slave processor element 2-i so as not to overlap them. On the other hand, a random number initial value receiving means 20-i of the slave processor element 2-i receives the random number initial values addressed to that element itself, and a random number generating means 21-i generates a random number value An (n>= pxv+1) by using the received random number initial values preferably according to the logic arithmetic of bit correspondence between a random number value An-pv and a random umber value An-qv when a parameter (v) satisfying the condition of 'qxv>alpha' is used or according to the logic arithmetic of bit correspondence between the random number value An-pv and a random number value An-pv+qv when a parameter (v) satisfying the condition of ' (p-q) xv>alpha' is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random number sequence generation processing method in a parallel computer system, and more particularly, to enable each processor element constituting the parallel computer system to generate a long period random number sequence having different sequences at high speed. The present invention relates to a random number sequence generation processing method in a parallel computer system.

A data processing device is required to generate a random number sequence having a long period at high speed, centering on a computer simulation by a Monte Carlo method. On the other hand, in recent years, in order to expand the data processing capacity,
Data processing systems composed of parallel computer systems are becoming popular. From this, it has become necessary for each processor element of the parallel computer system to generate a random number sequence having a different sequence and a long period at high speed.

[0003]

2. Description of the Related Art Up to now, although improvements have been made in which a random number sequence is generated at high speed on a single vector processor, almost no proposal has been made regarding a method for generating a random number sequence in a parallel computer system. Is the reality.

Against this background, recently P.Fr.
edrickson et al. proposed one way of thinking about the method of generating a random number sequence in a parallel computer system (Fredrickso
n, P., et al., "Pseudo-random trees in Monte Carl
o, "Parallel Computing, Vol.1, No.2, 1984, 175-180.). This proposal introduces the concept of Pseudo-random trees, and the parent processor uses these Pseudo-random trees. The seeds of random number generation are generated according to the mixed multiplication method and distributed to the child processors, and each child processor generates a random number sequence according to the mixed multiplication method based on the distributed seeds. It is a method of realizing generation.

That is, if X is an arbitrary element of Pseudo-random trees, then two elements L (X), R
(X) is defined by L (X) = (a _L X + c _L ) mod m R (X) = (a _R X + c _R ) mod m. Here, “x mod y” represents the remainder when the integer x is divided by the integer y. According to this definition
Given an initial value X ₀ , tree as shown in FIG.
Can be generated. The successor on the right side taken from any node in this tree is called the right series in that tree. As shown in FIG. 13B, the left branch of a particular node is taken up when a new right series is created with the left branch as a starting point.

[0006] P. Fredrickson et al.
According to the dom trees, the parent processor creates an element that becomes a left branch, and distributes this created element to the child processors,
We have proposed a method in which each processor generates a random number sequence by generating a right sequence from the distributed elements.

[0007]

[Problems to be Solved by the Invention] However, P. Fred
Although the random number sequence generation method proposed by rickson et al. can certainly generate a random number sequence in each processor of a parallel computer system, it can generate only a random number sequence with a short period because it follows the mixed multiplication method. There is a problem. For example, a 32-bit computer can only obtain a random number sequence with a period of (2 ³² -1) at most.

It is extremely important for random number sequence generation to prevent the random number sequences generated by the respective processors from colliding. However, P. Fredrickson et a
According to the method of generating random number sequence proposed by l., in order to prevent this collision, there is a complicated limitation on the coefficient value used for generating pseudo-random trees, which makes it difficult to determine the coefficient value. was there.

The present invention has been made in view of the above circumstances, and is a new parallel computer which enables each processor element constituting the parallel computer system to generate a random number sequence having a long sequence and a different sequence at a high speed. The purpose is to provide a random number sequence generation processing method in the system.

[0010]

1 to 3 show the principle configuration of the present invention. The present invention whose principle configuration is shown in FIG. 1 is a principle configuration when applied to a distributed memory type parallel computer system.

In the figure, 1 is a parent processor element, 2-i
(1 ≦ i ≦ k) is a child processor element, and 4 is a communication network. Here, one of the child processor elements 2
It is also possible to adopt a configuration in which -i functions as the parent processor element 1.

The parent processor element 1 comprises a random number initial value generating means 10 and a random number initial value distributing means 11. The random number initial value generating means 10 generates initial values of p × v × k random numbers. This random number initial value generation method is
It is possible to use the mixed multiplication method or the M sequence generation method described below.
It is also possible to use the two methods in combination. The generated random number initial value may be basically any value as long as it is not all zero. The random number initial value distribution unit 11 is p × v so that the random number initial value generated by the random number initial value generation unit 10 does not overlap with the child processor element 2-i via the communication network 4.
Distribute each one.

Here, p is a primitive irreducible polynomial "X ^p + X ^q +" that defines the generation of a random number sequence of an M sequence (Tausworthe number sequence).
1 ", v is defined as a power of 2, and the vector length of the vector operation mechanism of the child processor element 2-i is represented by α and q by the above primitive irreducible polynomial parameters. Is “q × v> α” or “(p
−q) × v> α ”, and k is the number of child processor elements 2-i that generate random numbers. If the child processor element 2-i does not have a vector operation mechanism, the value of v will be set to 1. Also,
It is preferable that v is the smallest value satisfying the above conditions in order to increase the generation efficiency of the random number initial value.

On the other hand, the child processor element 2-i comprises a random number initial value receiving means 20-i and a random number generating means 21-i. The random number initial value receiving means 20-i receives the random number initial value addressed to its own element distributed from the parent processor element 1. The random number generating means 21-i uses the random number initial value received by the random number initial value receiving means 20-i, preferably when the parameter v satisfying the condition of “q × v> α” is used, the random number value A _When a parameter v that satisfies the condition of “(p−q) × v> α”, which is a logical operation corresponding to a bit between _n-pv and the random number A _n-qv , is used, the random number A _n-pv and the random number A _According to the bitwise logical operation with _{n-pv + q v} ,
A new random number value A _n (n ≧ p × v + 1) is generated.

Here, it is preferable that "q>(p-q)".
Is satisfied, the condition satisfaction of “q × v> α” is required, and when “q <(p−q)” is satisfied, “(p−
q) × v> α ”is satisfied. Then, the random number generation means 21-i preferably uses an exclusive OR operation as the bit-based logical operation.

In the present invention whose principle configuration is shown in FIG. 2, instead of the communication network 4 used in the principle configuration of FIG. 1, a shared memory 5 that can be accessed by both the parent processor element 1 and the child processor element 2-i is communicated. It is used as a mechanism.

In accordance with this principle configuration, the parent processor element 1 comprises the random number initial value generating means 10 and the new random number initial value writing means 12 described in FIG. 1, while the child processor element 2- i is the random number generating means 21-i described in FIG. 1 and the new random number initial value reading means 22-i.
With.

In the present invention whose principle configuration is shown in FIGS. 1 and 2, the parent processor element 1 generates a random number initial value, whereas the present invention whose principle configuration is shown in FIG. Each processor element required to generate a random number initial value is configured to generate a random number initial value. In the figure, 3-i (1≤i≤k) is a processor element for which random number generation is required.

When adopting this configuration, each processor element 3-i has the random number initial value generating means 1 described in FIG.
Random number initial value generation means 30-i exhibiting the same function as 0
And a new random number initial value extraction means 31-i and a random number generation means 32-i that exhibits the same function as the random number generation means 21-i described in FIG.

[0020]

First, the operation of the present invention whose principle configuration is shown in FIG. 1 will be described. In the present invention whose principle configuration is shown in FIG. 1, random number initial value generating means 1 of the parent processor element 1
0 generates p × v × k random number initial values, and the random number initial value distribution unit 11 generates p × v random number initial values for each child processor element 2-i. Distribute so that they do not overlap. That is, according to a predetermined regularity such as the order, the distribution is performed so as not to overlap. Then, each child processor element 2-i
The random number initial value receiving means 20-i receives the random number initial value addressed to the self element distributed from the parent processor element 1, and the random number generating means 21-i uses the received random number initial value to generate a random number sequence. To generate.

The random number generation processing of the random number generation means 21-i is executed according to the method of generating the M-sequence random number sequence. In the M-sequence random number sequence generation method, _p of A _{1 to} A _p is used.
If exclusive OR operations are used as the bit-corresponding logical operations when the random number initial values are given, the following graduation derived from the primitive irreducible polynomial “X ^p + X ^q +1” modulo 2 is used. Formula A _n = EOR (A _np , A _nq ) ... The random number sequence after the (p + 1) term is generated according to the formula.
Then, this primitive irreducible polynomial "X ^p + X ^q +1" becomes "X
^p + X ^(pq) +1 ”, or because this primitive irreducible polynomial“ X ^p + X
^(pq) +1 ”, the following recurrence formula A _n = EOR (A _np , A _{n-p + q} ) ... The random number sequence after the (p + 1) term is generated according to the formula.

Here, if the above equation is followed, A _k and A
_Since A _{p + k} is generated from _{p + kq} , the number of random numbers that can be generated at one time using p random number initial values of A _{1 to} A _p is “p + k−q = p”. k = q ”. On the other hand, when following the above formula, since A _{p + k} is generated from A _k and A _{k + q} , the number of random numbers that can be generated at one time using p random number initial values of A _{1 to} A _p is , "K + q
= P ”holds, there are“ k = (p−q) ”pieces. That is, “q> (p−q)” from the viewpoint of random number generation efficiency.
When is satisfied, it is preferable to generate random numbers according to the formula, and when “(p−q) <q” is satisfied, it is preferable to generate random numbers according to the formula.

As described above, the random number generation means 21-i can generate only q random numbers at a time when the recurrence formula is followed. Further, when the recurrence formula of the formula is followed, only (p−q) random numbers can be generated at one time. With this, when the value of q or (p−q) is smaller than the vector length α of the vector operation mechanism of the child processor element 2-i, the vector operation mechanism has the ability to generate α random numbers at a time. There is a problem in that it does not use it even though it has it. Therefore, there is a problem that random numbers cannot be generated at high speed.

Therefore, the random number generating means 21-i uses the primitive irreducible polynomial "X ^p + X ^q +1" ^modulo 2 as "(X ^p + X
Corresponding to the fact that it is proved to be equivalent to “ ^q +1) ^v ” and “(X ^p + X ^(pq) +1) ^v ”, A _{1 to} A _pv
The following recurrence formula A _n = EOR (A _n-pv , A _n-rv ) derived from these primitive irreducible polynomials when p × v random initial values of However, it should be noted that r = q or (p−q) EOR operation can generate random number sequence after (p × v + 1) terms according to other logical operations. The configuration is such that a random number is generated at high speed while following the sequence random number sequence generation method.

That is, the random number generation means 21-i uses the value of r.
Using the recurrence of this equation using q as
As can be seen from the description related to the above equation, A₁
~ A _pvQ × v random numbers at a time from p × v random initial values of
A number can be generated, and thereafter, q × v units can be efficiently used as a unit.
Can generate random numbers. On the other hand, (p-q) is used as the value of r.
Using the recurrence formula of this formula,
As you can see from the related explanation, A₁~ A_pvP ×
(p−q) × v random numbers at once from v random initial values
Can be generated, and thereafter, the efficiency in units of (p−q) × v
Can randomly generate random numbers.

From this, the random number generating means 21-i preferably uses v such that q × v is larger than the vector length α.
Is selected, and a random number sequence of (p × v + 1) terms or later is generated with the vector length α as a generation unit according to the recurrence formula of “r = q”, or (p−q) × By selecting v such that v is larger than the vector length α, “r = (p−
q) ”according to a recurrence formula of a vector length α and a random number sequence of (p × v + 1) and subsequent terms is generated, thereby generating a high-speed random number sequence according to the M-sequence random number sequence generation method. Is processed.

Here, q is selected as r or (p
Basically, it is possible to select -q), but it is necessary that the random number initial value generating means 10 of the parent processor element 1 generates the initial values of p × v × k random numbers. Therefore, a smaller value of v is more suitable. From this, when "q>(p-q)" holds, it is preferable to select q as r, and "(p-
When “q)> q” holds, it is preferable to select (p−q) as r.

When the condition of "r × v>α" is satisfied, any power of 2 may be used as v, but the random number initial value generating means 10 of the parent processor element 1 uses Since it is necessary to generate initial values of p × v × k random numbers, it is appropriate to use the value of v that shows the smallest value among the numerical values that satisfy this condition. is there.

Further, to put it further, "r × v>α"
Even if the condition of is not satisfied, when v shows a value larger than 1, it means that the vector operation mechanism of the child processor element 2-i is effectively used as compared with the case where v shows 1. Random number generation. When the condition of “r> α” is satisfied from the beginning, 1 is set as the value of v.

In this way, according to the present invention, each child processor element 2-i of the parallel computer system has a configuration for generating a random number sequence in accordance with the M-sequence random number sequence generation method.

Next, the operation of the present invention whose principle configuration is shown in FIG. 2 will be described. In the present invention whose principle configuration is shown in FIG. 2, the random number initial value generating means 1 of the parent processor element 1
0 generates p × v × k random number initial values, and the random number initial value writing means 12 writes the generated p × v × k random number initial values in the shared memory 5. Then, the random number initial value reading means 22-i of the child processor element 2-i sets p × v × k random number initial values written in the shared memory 5 to p.
The random number generation means 21-i reads x × each so that it does not overlap with the other child processor element 2-i, and the random number generation means 21-i uses the read p × v random number initial values according to the M-sequence random number sequence generation method. Generate a column.

In this way, each child processor element 2-i of the parallel computer system generates a random number sequence in accordance with the M-sequence random number sequence generation method. Next, the operation of the present invention whose principle configuration is shown in FIG. 3 will be described.

In the present invention whose principle configuration is shown in FIG. 3, random number initial value generating means 30-i of each processor element 3-i is provided.
Is p × v × k similarly to the random number initial value generating means 10 of FIG.
Initial value of each random number is generated, and the random number initial value extraction means 31-i
Extracts p × v random number initial values assigned to its own element from the generated p × v × k random number initial values so as not to overlap with other processor elements 3-i,
The random number generation means 32-i uses the extracted random number initial value to generate a random number sequence according to the M-sequence random number sequence generation method.

In this way, each processor element 3-i of the parallel computer system generates a random number sequence in accordance with the M-sequence random number sequence generation method. According to this configuration, it is not necessary to execute the communication process for the random number generation process between the processor elements 3-i. Therefore, the processor of the present invention may be either a shared memory or a communication network.

[0035]

EXAMPLES The present invention will be described in detail below with reference to examples. Next, the present invention will be described in detail according to a more specific embodiment of the embodiment shown in FIG.

The present invention can be applied to all types of parallel computer systems as described with reference to FIGS. For example, the present invention is also applicable to a distributed memory type parallel computer system having a configuration connected through a communication network as shown in FIG. 4 (a), and FIG. 4 (b).
It is also possible for a shared memory type parallel computer system to adopt a configuration of sharing a memory as shown in FIG. 4 and is connected through a communication network while having a shared memory as shown in FIG. It can also be applied to a hybrid parallel computer system that adopts the above configuration. Here, PE in the figure represents a processor element.

FIG. 5 shows an overall flow of processing executed by the parent processor element 1 and the child processor element 2-i described in FIG. Here, the left part in the figure is the process executed by the parent processor element 1, and the right part is the process executed by the child processor element 2-i.

As shown in this figure, the parent processor element 1 first performs in step 1 a preprocessing for generating a random number initial value which is a seed of a random number sequence generated by the child processor element 2-i. Run, then in step 2,
This random number initial value is generated. And the following step 3
Then, the generated random number initial value is transferred to the child processor element 2-i via a communication network or the like, and finally, in step 4
Then, the post-processing is executed and the processing ends.

On the other hand, the child processor element 2-i first obtains the processor number information of its own element and the total number information of the child processor elements 2-i from the operating system in step 5. Next, in step 6, the process of the processing part that does not use random numbers is executed, and then in step 7, the random number initial value distributed to the own element from the random number initial value transferred from the parent processor element 1 is executed. Receive a value.

Then, in the following step 8, a random number sequence to be used in its own element is generated using this received random number initial value, and in step 9, the processing of the processing part using the generated random number sequence is executed. In step 10, it is determined whether or not there is a request to use a random number. If it is determined in step 10 that there is a request for using a random number, the process returns to step 8, and if there is no request for using a random number, the process proceeds to step 11 to execute the process of the process part that does not use the random number, and then the process ends. .

FIG. 6 shows a detailed processing flow of the random number initial value generation processing executed by the parent processor element 1. When generating the random number initial value, the parent processor element 1 first sets “p × v × k” in the variable l _p in step 20 as shown in the processing flow of FIG. The larger one of (p−q) is obtained and set as a new q (what has been described as r so far). Furthermore, according to this new _q , “q × v × k” is set to the variable l _q , and “49” is set to the variable A _1.
99 ". Here, as described above, p and q are primitive irreducible polynomials" X ^p "that define the generation of M-sequence random number values.
+ X ^q +1 ”, v is defined as a power of 2, and if the vector length of the vector operation mechanism of the child processor element 2-i is represented by α, then“ q × v> α ”
Is a numerical value that satisfies the condition of, and k is the number of child processor elements 2-i that generate random numbers.

Next, at step 21, the value of A _i (i = 2 to 2 × 1 _p ) is calculated according to A _i = A _i-1 × 137371.
From this calculation process and A ₁ set to “4999”, 2 × l _p values of A _i (i = 1 to 2 × l _p ) are determined.

Then, in step 22, one A _{i in} the range of i = 1 to l _p is selected and A _{i + lp} associated with this is selected. And this selected A _i
The process of replacing the selected A _i with a new one is performed by combining the upper 16 bits of A _{i + lp with} the lower 16 bits of the selected A _{i + lp} . In other words, to mix the A _i and A _{i + lp,} newly l _p pieces of A _{i (i} = 1~l _p)
Is generated. The random number generation method so far follows the mixed multiplication method.

Then, in step 23, a random number of M series is generated.
According to the method_i= EOR (A_i-lp, A_i-lq) However, EOR is the A generated in step 22 according to the bitwise exclusive OR operation._i(I = 1 to l
_p), A₁And A _{lp + 1-lq}Bitwise exclusion with
A according to logical OR operation_{lp + 1}And calculate A₂And A
_{lp + 2-lq}A according to the exclusive OR operation corresponding to
_{lp + 2}To calculate A_kAnd A_{lp + k-lq}With
According to the exclusive OR operation corresponding to_{lp + k}Calculate
A is newly defined by repeating the process_i(I
= L_p+1 to 1_p＋ 2 × l_q) Value is calculated.

This iterative calculation process is performed in step 22.
As the first stage of calculation by using A _i (i = 1 to l _p ) generated in step 22, A _i generated in step 22
Last number because it is A _lp of can be calculated from "k = l _q" which satisfies the _{l p + k-l q =} l p. That is, in the first stage, A _i generated in step 22
(I = 1 to l _p ) is used to newly create A _i (i = 1 _p +1
~ L _p + l _q ).

Next, this newly generated A _i (i = 1
_p +1 to l _p + l _q ) is also included in the second stage, and since the last number of A _i generated in this second stage is A _{lp + lq} , l _p + k−l _q It is possible to calculate up to “k = 2l _q ” at which = l _p + l _q holds. That is, as the second stage, A _i (i
_{= L p + 1~l p + l} q) be included, followed by those produced in the first stage, the new _{A i (i = l p +} l q + 1~l p
+ 2 × l _q ) is generated.

Thus, in this step 23,
From A _i (i = 1 to l _p ) generated in step 22,
Newly defined as _{A i (i = l p +} 1~l p + 2 ×
By calculating the value of l _q ), the further mixed A _i
Will be decided.

As will be described later, what is actually used as the random number initial value is the determined A _i (i = l _p +1).
~ L _p + 2 × l _q ) of l _p A _i (i =
2 × l _q +1 to l _p + 2 × l _q ).

In this way, the parent processor element 1 generates a random number initial value by executing the processing flow of FIG. The random number initial values thus generated are distributed to the k child processor elements 2-i by p × v so as not to overlap each other according to a certain rule. This distribution method can follow various methods. For example, p × v random number initial values are extracted from the beginning of the generated l _p (= p × v × k) random number initial values, As a method of sequentially distributing to each child processor element 2-i, or as shown in FIG. 7, the random number initial values are taken out one by one from the head of the generated l _p random number initial values,
It is possible to follow various distribution methods such as a method of sequentially distributing to each child processor element 2-i.

In this way, the parent processor element 1 distributes to the child processor element 2-i a combination of p × v random number initial values that does not overlap.

Each child processor element 2-i uses the p * v random number initial value addressed to this element notified from the parent processor element 1 according to the processing flow shown in FIG. Will generate a random number sequence.

That is, the child processor element 2-i
First, in step 30, the values of p, q, v, and ma are set. Here, as described in the processing flow of FIG. 6, p is a parameter of the primitive irreducible polynomial “X ^p + X ^q +1” assumed by the parent processor element 1, and q is q of this primitive irreducible polynomial and (p− The larger parameter of q), v, is defined as a power of 2, and if the vector length of the vector operation mechanism of the child processor element 2-i is represented by α, then “q × v> α”. Is a numerical value that satisfies the condition of, and k is the number of child processor elements 2-i that generate random numbers. Further, ma is a natural number that defines the amount of random numbers to be generated.

Next, at step 31, p × v random number initial values notified from the parent processor element 1 are received. Hereinafter, for the sake of convenience of explanation, the received p × v random number initial values will be described as B _i (i = 1 to p × v).

Then, in step 32, the recurrence formula is the same as the above formula derived by expanding the method for generating a random number sequence of M sequence. B _i = EOR (B _i-pv , B _i-qv ) ... The random number initial value B received in step 31 according to the equation
_i (i = 1 to p × v) is used to calculate B _{pv + 1} according to the bitwise exclusive OR operation of B ₁ and B _{pv + 1-qv,} and B ₂ and B _{pV + 2-} B _{pv + 2} is calculated according to the bitwise exclusive OR operation with _qv, and this calculation process is performed by B _{pv + maqv}
By repeating the above until a new random number sequence B _i
(I = p × v + 1 to p × v + ma × q × v) is generated.

Here, this random number sequence B _i (i = p × v + 1
Specifically, the calculation process of (p × v + ma × q × v) is
In accordance with the vector operation mechanism of the child processor element 2-i, at the first stage, B _i (i = p × v + 1 to p × v + q
Xv) is calculated, and in the second step, B _i (i = p × v + 1 +
q × v to p × v + 2 × q × v), and in the third stage,
B _i (i = p × v + 1 + 2 × q × v to p × v + 3 × q ×
This is performed by calculating v) and executing it up to the ma-th stage.

As described above, by using the recurrence formula of the formula, the child processor element 2-i can generate a random number sequence at high speed by fully utilizing the vector operation mechanism of its own element. This is the reason why, in the present invention, the random number sequence is generated using the recurrence formula of the expanded formula, not using the general formula or the recurrence formula of the formula that defines the method for generating the M-sequence random number sequence. is there. This point was explained in detail in the explanation of the reason for introducing the recurrence formula.

More precisely, in step 32 of the process flow of FIG. 8, the child processor element 2-i does not generate a random number sequence in q × v units at each stage in step 32. Then, as will be described later, the random number sequence is processed in units of the vector length α of the vector operation mechanism.

As described above, in the present invention, in each child processor element 2-i of the parallel computer system, a random number sequence is generated according to the extended M-sequence random number sequence generation method while fully utilizing the vector operation mechanism. By adopting such a configuration, it becomes possible to generate a random number sequence with a long cycle without collision at high speed.

9 to 12 show an example of a detailed program for realizing the processing flow described above. Here, FIG. 9 shows the parent processor element 1.
10 is a program example for realizing the random number initial value generation process executed by the above, FIG. 10 is a program example for realizing the random number initial value transfer process executed by the parent processor element 1,
FIG. 11 is a program example for realizing the random number initial value receiving process executed by the child processor element 2-i, FIG.
Is an example program for realizing the random number sequence generation process executed by the child processor element 2-i.

Next, the contents of these programs will be described. In the program of FIG. 9 that realizes the processing flow shown in FIG. 6, the portion is the program portion corresponding to step 20 of the processing flow of FIG.
This is a program part for instructing the setting of various parameter information. In this program part, the value of k is “2 ¹⁰ ”, that is, the number of child processor elements 2-i is 1024.
Is set to be a stand, and the value of p is "28
It is set that the values of 4 ”and q are“ 143 ”.

Since r = MAX (q, p-q) = q = 143 according to the value of q, this value of q is used as a new value of q. Furthermore, the child processor element 2-i
Assuming that the vector length α of the vector operation mechanism of is 512, the newly defined q needs to satisfy q × v> 512. ² =
4 "will be set.

Further, in this part, the definitions of l _p and l _q and the array “IRANSU” consist of 4-byte data items, and as described in step 23 of the processing flow of FIG. It is set to store l _p + 2 × l _q ) data values. And A ₁
The value of the variable "TANE" that defines the value of
Is set to 9 "and the top 16 of A _i
Data IX having a value of "FF00" used to extract bits and data IY having a value of "00FF" used to extract lower 16 bits of A _{i + lp} are set.

Further, in the program of FIG. 9, the portion is the program portion corresponding to step 21 of the processing flow of FIG. 6, and 2 × l _p A _i are obtained according to A _i = A _i-1 × 137371. calculates the value of the _{(i = 1~2 × l p)} , a program part to be stored in order from the beginning of the array IRANSU.

The portion is the program portion corresponding to step 22 of the processing flow of FIG.
X and A _i (i = 1 to 1) stored in the array IRANSU
The upper 16 bits of A _i are extracted by a logical AND operation corresponding to 1 _p ) and the data IY and array IR.
The lower 16 bits of A _{i + lp} are extracted by a logical AND operation corresponding to A _{i + lp} (i = 1 to l _p ) stored in ANSU, and the upper 16 bits of the extracted A _i are further extracted. And A
A program for calculating new l _p A _i (i = 1 to l _p ) values according to a logical OR operation corresponding to the lower 16 bits of _{i + lp} , and storing the values in order from the beginning of the array IRANSU It is a part.

The portion is a program portion corresponding to step 23 of the processing flow of FIG.
An array I is calculated by calculating A _{lp + 1} according to the bitwise exclusive OR operation of A ₁ and A _{lp + 1-} lq stored in ANSU.
Stored in the "l _p +1" th RANSU, array IRAN
The array IRA is calculated by calculating A _{lp + 2} according to the bitwise exclusive OR operation of A ₂ and A _{lp + 2-lq} stored in SU.
The process of storing "l _p +2" th of NSU is repeated, and finally, according to the bitwise exclusive OR operation of A _2lq and A _{lp + lq} stored in the array IRANSU, A _{lp + 2LQ} calculates the, by going to store the _{"l p + 2 × l q} " th sequence IRANSU, SEQ I
"L _p +1" to "l _p + 2 × l _q " of RANSU
Th, the new 2 × l _q pieces of _{A i (i = l p +} 1~l p
+ 2 × l _q ) is the program part that stores it.

As can be seen from the program contents of FIG. 9 explained above, the parent processor element 1 is
By executing the program (1), the random number initial value is generated while following the generation method based on the mixed multiplication method and the M series. The random number initial value generated by the parent processor element 1 is regularly distributed to the child processor elements 2-i by p × v in accordance with the programs shown in FIGS. Here, the distribution program of FIGS. 10 and 11 has a configuration in which the parent processor element 1 arranges and notifies the generated random number initial values to all the child processor elements 2-i. On the -i side, a method of selectively receiving the random number initial value distributed to its own element according to a certain rule is adopted.

The program of FIG. 10 is executed by the parent processor element 1, and transfers the designated random number initial value in the generated array IRANSU to all the child processor elements 2-i. It is an example of a program for instructing. S of the subroutine that executes the transfer process
The first argument of the END instruction displays the start address of the array to be transferred, and the second argument displays the number of bytes to transfer from this start address.

In this program, the "2 × l _q +1" th random number initial value of the array IRANSU is set as the head, and l _p random number initial values (data length of one random number initial value are 4 bytes) to all the child processor elements 2-i. That is,
According to this program, the parent processor element 1 generates the random number initial value A _i generated by the program of FIG.
_{(I = l p + 1~l p} + 2 × l q) of the, l from behind
Initialize _p random numbers to A _i for all child processor elements 2
-Transfer to i.

On the other hand, the program of FIG. 11 which realizes the processing of step 31 of the processing flow shown in FIG. 8 is executed by the child processor element 2-i and transferred from the parent processor element 1. This is an example of a program for instructing to selectively receive a random number initial value distributed to its own element from among the random number initial values that are received.

Here, the first argument of the RECV instruction of the subroutine of the part that executes the receiving process displays the starting address of the array where the received random number initial value is stored. The second argument indicates the number of bytes up to the reception start portion in the X direction (processor number direction in FIG. 7). The third argument displays the number of bytes from the previous received portion to the next received portion in the X direction. The fourth argument indicates the number of bytes of the reception partial unit in the X direction. For example, it indicates that 4 bytes are one unit of the reception part. The fifth argument indicates the total number of bytes of the reception part in the X direction.
For example, when the total number of units of the receiving part is one unit,
Display 4 bytes.

The sixth argument displays the number of lines of the reception start portion in the Y direction (the other direction in FIG. 7). The seventh argument displays the number of lines from the previous reception portion to the next reception portion in the Y direction. When it is 0, it indicates that the lines are continuous. The eighth argument displays the number of lines that the receiving partial unit has in the Y direction. When it is 1, it indicates that the received portion is on one line. The ninth variable indicates the total number of lines in the reception part in the Y direction. For example, when receiving p × v, p × v is displayed.

Here, the program of FIG. 11 is complicated because it has a general-purpose configuration.
If a dedicated configuration is adopted, it can be realized with a simpler one.

In this program, after defining the parameter information and the array IR that will store p × v random number initial values to be received in the part, the part obtains its own processor element number ncid, Then, the total number k of child processor elements is obtained. Then, in the RECV instruction of the part, the own processor element number ncid
An example is disclosed in which, from the initial random number initial value specified by, the random number initial values are sequentially received up to p × v by skipping k. By this program, each child processor element 2-i receives the random number initial value transferred from the parent processor element 1 according to the aspect shown in FIG.

In the program of FIG. 12 that realizes the process of step 32 of the process flow shown in FIG. 8, the part is a program part for instructing the setting of various parameter information. In this program part, ma
"3" is set as the value of p, and the value of p is "284" and the value of q is "1" corresponding to the program example of FIG.
It is set that the values of 43 "and v are" 4 ". Furthermore, the array IR storing the received p * v random number initial values and the 512 * ma random number sequence to be generated are stored. An array JR is defined as follows, where the maximum vector length that allows vector operation is q × v in this case,
That is, the number is 572, but the maximum storage number of the array JR is defined by 512 × ma, corresponding to the fact that the vector length α of the vector operation mechanism is optimized to 512.

The part of the program that realizes the process of step 32 of the process flow shown in FIG. 8 is the part. A random number sequence is generated by this program part.

Here, the calculation process of this random number sequence is "B _i
= EOR (B _i-pv , B _i-qv ) ”, specifically,
In accordance with the vector operation mechanism of the child processor element 2-i, at the first stage, “i = p × v + 1 to p × v + 51
2 ”are calculated, and in the second stage,“ i = p × v + 1 + 51
2−p × v + 2 × 512 ”is calculated, and“ i
= P × v + 1 + 2 × 5122−p × v + 3 × 512 ”, and this is executed up to the ma-th stage, and the vector length α (512 in this case) of the vector operation mechanism is used as a unit. Will be executed as.

Note that the program of the part always shifts the generated random number value to the right by 1 bit so that the value of the leading bit for displaying the code is always "0", that is, positive. It is provided to set like this. Further, when using a random number from "0" to "1", a process of dividing the element of the array JR that stores the generated random number sequence by 2 ³¹ is required.

In this way, the random number sequence generation processing of the present invention can be realized according to the program examples shown in FIGS.

[0079]

As described above, according to the present invention,
Since each processor element of the parallel computer system is configured to generate a random number sequence in accordance with the M-sequence random number sequence generation method, it becomes possible to generate a random number sequence with a long period, and it is difficult to perform a mixed multiplication method. It becomes possible to generate a random number sequence that does not collide with the character. Then, in applying this M-sequence random number sequence generation method, since the configuration that makes maximum use of the vector operation mechanism is adopted, each processor element can generate a random number sequence at high speed. Moreover, since the communication process between the processor elements is not required other than the data transfer of the random number initial value, and the configuration that does not require the data transfer of the random number initial value is adopted, the high speed can be ensured. Of.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is a principle configuration diagram of the present invention.

FIG. 4 is an explanatory diagram of a parallel computer system to which the present invention is applicable.

FIG. 5 is a processing flow for explaining the overall processing of the present invention.

FIG. 6 is an example of a processing flow of random number initial value generation processing.

FIG. 7 is an example of a method of distributing a random number initial value.

FIG. 8 is an example of a processing flow of random number sequence generation.

FIG. 9 is a coding example for generating a random number initial value executed by a parent processor element.

FIG. 10 is a coding example for random number initial value transfer executed by a parent processor element.

FIG. 11 is a coding example for receiving a random number initial value executed by a child processor element.

FIG. 12 is a coding example for generating a random number sequence executed by a child processor element.

FIG. 13 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 parent processor element 2 child processor element 3 processor element 10 random number initial value generating means 11 random number initial value distributing means 12 random number initial value writing means 20 random number initial value receiving means 21 random number generating means 22 random number initial value reading means 30 random number initial value Generating means 31 Random number initial value extracting means 32 Random number generating means

Claims (6)

[Claims] 1. In a parallel computer system composed of a plurality of processor elements, any one of the processor elements generates an initial value of a random number, and a processor element required to generate a random number is an initial value of the generated random number. A random number sequence generation processing method in a parallel computer system, characterized in that a random number sequence is generated according to an M-sequence random number generation method using a random number initial value addressed to its own element in the above. 2. In a parallel computer system composed of a plurality of processor elements, each processor element that is required to generate a random number generates an initial value of a random number according to the same algorithm, and among the generated random number initial values, A random number initial value for its own element is extracted from the element, and the extracted random number initial value is used to generate a new random number sequence according to the M-sequence random number generation method. A random number sequence generation processing method in a computer system. 3. A parallel computer system comprising a plurality of processor elements, wherein any one of the processor elements is p × v × k (p
Is a primitive irreducible polynomial parameter that defines random number generation, v
Is a predetermined numerical value indicating a value of 1 or more, k is the initial value of a random number of the number of processor elements generating a random number), and the processor element required to generate the random number is q Approximate polynomial parameter, r to q
And (p−q), one of the generated p × v × k random number initial values is assigned to its own element by p × v random number initial values, A parallel computer characterized by processing to generate a new random number value A _n (n ≧ p × v + 1) by a logical operation corresponding to a bit of the random number value A _n-pv and the random number value A _n-rv. A random number sequence generation processing method in the system. 4. In a parallel computer system composed of a plurality of processor elements, each processor element has p × v × k pieces (p is a parameter of a primitive irreducible polynomial that defines random number generation, v Is a predetermined number indicating a value of 1 or more,
(k is the number of processor elements that generate the random number), generates an initial value of the random number, extracts p × v of the own element from the generated initial value of the random number, and defines q as the random number generation. If r, which is a parameter of the primitive irreducible polynomial to be defined, is defined as one of q and (p−q), using the extracted p × v random number initial values,
A parallel computer characterized by processing to generate a new random number value A _n (n ≧ p × v + 1) by a logical operation corresponding to a bit of the random number value A _n-pv and the random number value A _n-rv. A random number sequence generation processing method in the system. 5. The random number sequence generation processing method in the parallel computer system according to claim 3 or 4, wherein r is defined as a value showing a large value of q and (p−q), Random Number Sequence Generation Method for Parallel Computer Systems. 6. A random number sequence generation processing method in a parallel computer system according to claim 3, 4 or 5, wherein v represents a vector length of a vector operation mechanism of a processor element required to generate a random number by α, r × v
A random number sequence generation processing method in a parallel computer system characterized in that is selected as showing the smallest value among those showing a value larger than α.