JPH06202602A - Display mode switching controller - Google Patents

Abstract

PURPOSE:To improve the operability of the controller by preventing an image from being disordered unnaturally at the time of display mode switching. CONSTITUTION:This controller is provided with a blanking control part 11 which can generates a blanking signal, used conventionally for non-display control in a horizontal blanking period and a vertical blanking period, for a certain time at the time of the display mode switching. When the output of a mode selection part 3 varies for the display mode switching, a blanking control part 11 generates a certain-time blanking signal and supplies it to an image signal processing part 6. Consequently, an image signal which is outputted to the display part 7 during the period is inhibited. Therefore, no disordered image is displayed at the display part 7 at the time of the mode switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display mode switching control device for controlling the display mode of a display device provided in a computer system or the like.

[0002]

2. Description of the Related Art In a computer system, a display device displays various images such as control screens, documents and figures for controlling the system. When performing graphic processing or the like, a higher resolution is required than when displaying characters. Therefore, conventionally, in this type of computer system, two or more kinds of display modes are prepared, and the display modes can be switched as needed. In addition, some have two or more types of display modes to suit the data structure and application software. Such a display device has an image signal,
An image is displayed by receiving the vertical synchronizing signal and the horizontal synchronizing signal. Then, when the horizontal and vertical synchronizing signal frequencies are switched, it is recognized that the display mode has been switched, and the image is displayed under preset conditions. A display device having such a function is called a multi-scan CRT.

FIG. 2 shows a block diagram of a conventional device having the above-mentioned functions. This device is a processor (CP
U) 1, the first CRTC2-1, and the second CRTC2-2
And the mode register 3 are connected to the system bus 4. The processor 1 is for controlling the operation of the entire apparatus. In addition, the first CRTC2-1 and the second CR
Each of the TCs 2-2 is composed of a CRT controller for outputting an image signal and a synchronizing signal in different display modes. The mode register 3 is composed of a register for selecting and instructing in what display mode this device displays an image. For example, when the data "0" is stored in this mode register 3,
When the first image display mode is selected and the data "1" is stored in the mode register 3, the second image display mode is selected.

The first CRTC 2-1 and the second CRTC2-
The output of 2 is connected to the multiplexer unit 5. The output of the multiplexer unit 5 is the image signal processing unit (R
AMDAC) 6 is connected. An image is displayed on the display unit 7 by the output of the image signal processing unit 6. 1st CR
The TC 2-1 is provided with an FRM (frame memory) 8-1 and a timing control section 9-1. Also, the second
The CRTC 2-2 has an FRM 8-2 and a timing control unit 9
-2 is provided. The FRMs 8-1 and 8-2 are image memories for holding and outputting the first display data or the second display data, respectively. Here, for example, multi-valued image data for each pixel that constitutes display data is stored.

The timing control units 9-1 and 9-2 are provided with a first VCLK signal, a second VCLK signal, and a first BLA, respectively.
NK signal, second BLANK signal, first HSYNC signal,
Second HSYNC signal, first VSYNC signal, second VSYNC
It is composed of a circuit that outputs an NC signal. Such a circuit is composed of a counter, a gate, and the like. VCL
The K signal is a dot clock signal. Also, BLANK
The signal is a blanking signal that controls non-display of the image during the horizontal blanking period and the vertical blanking period. The HSYNC signal is a horizontal sync signal, and the VSYNC signal is a vertical sync signal.

The multiplexer unit 5 includes a first CRTC2-
It is composed of a selection circuit for selecting either the output of the first CRTC 2-2 or the output of the second CRTC 2-2 for output to the image signal processing unit 6. The mode register 3 controls the selection of the multiplexer unit 5. The multiplexer unit 5 selects any of the input signals and outputs them as the third display data, the third VCLK signal, and the third BLANK signal. These are input to the image signal processing unit 6, the third display data is converted into a predetermined analog RGB signal, and output toward the display unit 7. The third HSYNC signal, which is the horizontal synchronizing signal and the vertical synchronizing signal, and the third VSYNC signal are directly supplied from the multiplexer unit 5 to the display unit 7.

The above device operates as follows. First,
The processor 1 uses the first CRTC 2-1 and the second CR in advance.
The timing control units 9-1 and 9-2 of the TC 2-2 are initialized to set predetermined display modes. Then, the display data is written in FRM8-1 or FRM8-2. Further, the processor 1 has the mode register 3
The display mode is set, and the multiplexer unit 5 outputs the MODE output from the mode register 3.
Depending on the SEL signal, the first CRTC 2-1 and the second CRT
It is determined which signal of C2-2 is selected.

The third display data output from the multiplexer unit 5 is input to the image signal processing unit 6 in synchronization with the third VCLK signal and converted into an analog RGB signal. Further, the third BLANK signal is supplied from the multiplexer unit 5 to the image signal processing unit 6, and non-display control is performed in the horizontal blanking period and the vertical blanking period. In this way, the analog RGB signal supplied to the display unit 7 is changed to the third HSYNC.
Controlled by the signal and the third VSYNC signal, a predetermined image display is performed. The third VCLK signal is used for conversion timing control.

[0009]

By the way, in the conventional apparatus having the above-mentioned configuration, for example, the first CRTC2-
It is assumed that the signal output by 1 is selected by the multiplexer unit 5 and is displayed on the display unit 7. At this time,
In order for the processor 1 to change the display mode, the second
It is assumed that after the necessary image signals have been supplied to the CRTC 2-2, the contents of the mode register 3 are switched to give a display mode selection instruction. In this case, the multiplexer unit 5 switches the selection operation according to the selection instruction of the mode register 3. Thereby, for example, the first CRT
The output of C is cut off, and the output of the second CRTC is output to the image signal processing unit 6.

However, when the display mode is switched, the display unit 7 displays the third HSYNC signal and the third VSYNC.
Accept the C signal, determine the mode to be displayed next,
Switch the necessary operating conditions. In this case, until the display of the screen on the display unit 7 becomes stable, it takes about 1 second conventionally. Therefore, the image displayed on the display unit 7 is distorted or flickers during that time. Such a display disorder gives the operator an unpleasant feeling.
In addition, the operator may mistakenly think that some kind of failure has occurred in the device due to such image disturbance.

The present invention has been made in view of the above points, and provides a display mode switching control device for preventing unnatural image disturbance when switching the display mode and improving the operability of the device. The purpose is to do.

[0012]

The first invention of the present invention is 2
A display unit capable of displaying an image in any one of two or more display modes, an image signal processing unit that outputs an image signal to the display unit, and one of the two or more display modes are selected. After the switching of the display mode selection instruction by the mode selection section and the mode selection section, a blanking signal is output and the image signal processing section outputs the image signal for a predetermined time. The present invention relates to a display mode switching control device, which is provided with a blanking control unit for suppressing the display mode.

A second aspect of the present invention is a display section capable of displaying an image in any of two or more display modes, an image signal processing section for outputting an image signal to the display section, and a display mode. The display mode switching is provided with an interrupt control unit for outputting an interrupt signal to a control processor so as to invalidate all the bits of the image signal for a certain period of time immediately before the selection is switched. Regarding the control device.

[0014]

This device has a blanking control unit that can generate a blanking signal, which has been conventionally used for non-display control in the horizontal blanking period and the vertical blanking period, for a certain time when the display mode is switched. It is provided. When the output of the mode selection unit changes to switch the display mode, the blanking control unit generates a blanking signal for a certain period of time,
It is supplied to the image signal processing unit. This suppresses the image signal output to the display unit during that time. Therefore, the disordered image at the time of mode switching is not displayed on the display unit. Also, when switching the display mode, an interrupt causes the processor to invalidate all the bits of the image signal stored in the image signal processing unit, and suppresses the display of the image for a certain period until the interrupt is released. You may This also prevents the display of disordered images.

[0015]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a display mode switching control device of the first invention of the present invention. This device is controlled by the processor 1 and includes a first CRTC 2-1.
And the second CRTC 2-2 are configured to generate and output image signals and timing control signals in different modes. Here, the processor 1 and the first CRTC 2-1
The second CRTC 2-2 and the mode register 3 are connected to the system bus 4. The mode register 3 is provided to select and instruct the image display mode displayed by this device.

The above-mentioned configuration is the same as that of the conventional device described in FIG. First CRTC2
The configuration of the multiplexer unit 5 that selects and outputs one of the output signals of -1 and the output signal of the second CRTC 2-2 is not different from that of the conventional device. Similarly, the image signal processing unit 6 for converting the display data into analog RGB signals and the display unit 7 are also provided in the conventional configuration.

Here, in the apparatus of the present invention, a blanking control section 11 is newly provided between the multiplexer section 5 and the image signal processing section 6. This circuit receives the third BLANK signal output from the multiplexer unit 5 and outputs it as the fourth BLANK signal to the image signal processing unit 6 as it is, while generating a blanking signal independently when switching the image display mode, 4BLANK
The signal can be combined with the signal and output to the image signal processing unit 6. This blanking control unit 11
The MODESEL signal output from the mode register 3 and the third VSYNC signal output from the multiplexer unit 5 are received to generate a blanking signal for switching the display mode.

FIG. 3 shows a block diagram of a blanking control section of the device of the first invention. A specific configuration of the blanking control unit 11 will be described with reference to this block diagram. As shown in the figure, the blanking control unit 11 is provided with an OR gate 12. One of the terminals is
Third BLAN output from the multiplexer unit 5 shown in FIG.
The K signal is input and directly output as the fourth BLANK signal to the image signal processing unit 6. The MASK signal generated by the edge detection unit 13 and the counter unit 14 is input to the other terminal of the OR gate 12. The MODES output from the mode register 3 shown in FIG.
EL signal is input. In the present invention, this mode register 3 is called a mode selection unit.

The edge detecting section 13 is composed of a differentiating circuit which detects an edge of the MODESEL signal and outputs a TRIG signal. When receiving the TRIG signal, the counter unit 14 starts counting the third VSYNC signal,
At the same time, the MASK signal is switched to the high level. Third V
If the SYNC signal is input at a period of 1/60 second, for example, after counting this signal 60 times, the MA
The SK signal is switched to the low level again. This MASK signal is output through the OR gate 12 and combined with the fourth BLANK signal.

FIG. 4 shows a concrete block diagram of the image signal processing section 6. In the figure, this image signal processing unit 6 is
It is composed of a latch 61, a data mask register 62, a color palette RAM 63, and DACs 64R, 64G, 64B. The latch 61 includes the third display data and the fourth BLA output from the multiplexer unit 5 shown in FIG.
It is composed of a register for temporarily holding the NK signal. The timing of this holding is controlled by the third VCLK signal. The data mask register 62 has a latch 61.
It accepts the third display data output from and outputs all or some of these bits to the color palette RAM.
This is a circuit for outputting to 63. This data mask register 62, for example, when the third display data is 8 bits,
Eight AND gates are provided, and a circuit for receiving the third display data at one terminal of each AND gate and receiving the output of a mask register (not shown) built in the other terminal is formed.

For example, when the gradation of the image signal is 16 gradations, the third display data consists of 4 bits, and this data mask is used to invalidate the output of 4 of the 8 signal lines. Register 62 is used. When the image signal has 256 gradations, the third display data is composed of 8 bits. Therefore, for example, all the 8-bit signals input to the data mask register 62 are validated and the color palette RAM 63 is activated.
The contents of the mask register are rewritten so as to be supplied to. The contents of this mask register are controlled and rewritten by the processor 1 shown in FIG. 1 via the system bus. The color palette RAM 63 has a data mask register 62.
It is composed of a look-up table for converting the third display data input from the latch 61 into a digital RGB signal through. Color palette RAM63
A fourth BLANK signal is input from the latch 61, and blanking signals are used for blanking and suppression of image signals.

In the device of the first invention, this latch 6
The third BLA output from the multiplexer unit 5 for 1
The fourth BLANK signal output from the blanking control unit 11 is input instead of the NK signal. by this,
The color palette RAM 63 suppresses conversion of image signals for a certain period of time after switching the instruction to select the image display mode. Three DACs are provided on the output side of the color palette RAM 63. These DAC64R, 64G, 64B
Are each composed of a digital-analog converter for converting a digital image signal into an analog image signal.

FIG. 5 is a time chart showing the operation of the above-mentioned first invention. The device shown in FIG. 1 operates according to this time chart. That is, first, it is assumed that the display unit 7 of the apparatus shown in FIG. 1 is displaying an image in the first display mode. In this case, for example, the first display data output from the first CRTC is selected by the multiplexer unit 5 and supplied to the image signal processing unit 6. A signal for the timing control is similarly supplied to the image signal processing unit 6 and the display unit 7.

Here, it is assumed that the processor 1 performs the operation of switching the display mode from the first display mode to the second display mode. In this case, a predetermined image signal or the like is supplied to the second CRTC 2-2, and the mode register 3
The contents of can be switched. As a result, the MODESEL signal output from the mode register 3 is switched to the time t1 as shown in FIG. This MODESE
When the L signal is input to the blanking control unit 11, the edge detection unit 13 shown in FIG.
The RIG signal is output and the counting operation of the counter unit 14 is started.

As shown in FIG. 5 (c), the third VSYNC signal is periodically input to the counter section 14. After time t1, the counter unit 14 counts this third VSYNC signal. Further, M output from the counter unit 14
As shown in FIG. 5D, the ASK signal switches from the low level to the high level after time t1 when the counting is started. As a result, the output signal of the OR gate 12 shown in FIG. 3 becomes high level. Third BLA shown in FIG. 5 (e)
The MASK signal shown in (d) is combined with the NK signal to form a signal shown in (f), and the fourth BLANK signal is generated. This fourth BLANK signal is input to the image signal processing unit shown in FIG. As shown in FIG. 5 (g),
After time t1, the display on the display unit is switched from the first display mode to the display inhibition state. In this state, no image is displayed on the display unit 7.

After that, the blanking control unit 1 shown in FIG.
The counter unit 14 of No. 1 is, for example, 60 times, the third VSYNC.
When the signals are counted, it means that about 1 minute has passed from the instruction to switch the display mode. At time t2, the counter unit 4 counts up and the MASK signal is switched from the high level to the low level as shown in FIG. 5 (d). As a result, the OR gate 12 shown in FIG.
The fourth BLANK signal output by the above switches to the normal content as shown in FIG. Thus, as shown in FIG. 5G, the screen of the second display mode is displayed on the display unit.

The apparatus of the first invention is different from the conventional apparatus in that
By newly providing the blanking control unit 11 that receives the output signal of the mode register 3 and generates the blanking signal, the image display on the display unit 7 is suppressed for a certain time when the display mode is switched. On the other hand, in the second aspect of the invention, the similar effect is achieved by changing the program control of the processor 1 without adding such special hardware. In this case, in the second invention, the data mask register 62 of the image signal processing unit 6 shown in FIG. 4 is used to make the image signal invalid for a certain period of time.

That is, as described above, the data mask register 62 operates so as to invalidate an unnecessary bit signal depending on how many bits the display data is composed of. Therefore, the operation condition is set at the start of the signal processing operation and thereafter the operation condition is not switched until the type of the signal is changed. However, in the present invention, the data mask register 62 is operated when the display mode is switched, and at that time, all the image signals input to the data mask register 62 are invalidated. This control is directly executed by the processor to the data mask register 62 via the system bus 4. As a result, image display can be suppressed in the same manner as supplying a blanking signal to the image signal processing unit 6.

FIG. 6 shows a block diagram of an embodiment of an apparatus for realizing the second invention. When carrying out the second invention,
As shown in the figure, the third V output from the multiplexer unit 5 is output.
An interrupt controller 15 is provided to supply the SYNC signal to the processor 1 as an interrupt signal, that is, an INT signal. The interrupt control unit 15 supplies a signal for mode setting to the mode register 3 and, when detecting that the mode selection has been switched, outputs the third VSYNC signal output from the multiplexer unit 5 to the processor 1. It is composed of such a gate circuit.

FIG. 7 shows an operation flowchart of the apparatus of the second invention. The operation of the second invention will be described more specifically with reference to this flowchart. First, when the processor 1 wants to change the display mode, it sets data and switches the contents of the mode register 3. This is done as usual. At this time, in step S1 of FIG. 7, all bits of the data mask register 62 are set to "0". That is, when the mask bit of the data mask register 62 is set to "0", all the input signals become invalid and the color palette RAM
No display data is supplied to 63. As a result, after the process of step S1, the display screen of the display unit 7 disappears and the screen display is suppressed.

In step S2, the subsequent display mode switching process is executed, and in step S3, the interrupt controller 15 inputs the third VSYNC signal to the processor 1. Then, in step S4, the processor 1 counts the number of interrupts by the third VSYNC signal. When this number reaches a fixed number, for example 60 times, it means that about 1 minute has elapsed from the start of switching the display mode. When this count is finished, the processor 1 sets all bits "1" in the data mask register 62. After that, the third display data held in the latch 61 passes through the data mask register 62 and is output to the color palette RAM 63. As a result, the screen display suppression is canceled and the display unit 7
The screen is displayed on. Therefore, the disturbed image at the time of switching the display mode is not displayed on the display unit 7.

If the device of the second aspect of the invention is used, the entire signal generation section 30 enclosed by the broken line shown in FIG. 6 is an integrated circuit, and it is possible to detect mode switching from the outside. Even when it is not possible, it is possible to suppress the screen display when switching the display mode.

The present invention is not limited to the above embodiments. In the above-mentioned embodiment, the device capable of switching between two kinds of display modes has been illustrated, but even if any of two or more kinds of display modes can be displayed, it is possible to suppress the screen display by the same control. it can. Further, the circuit block configurations of the image signal processing unit 6 and the blanking control unit 11 may be replaced with various circuit blocks having the same function.

[0034]

The display mode switching control device of the present invention described above, when selecting and displaying any one of the display units capable of displaying an image in any of two or more display modes, After the display mode selection instruction is switched, a blanking signal is output for a certain period of time, and a blanking control unit that suppresses the output of the image signal is provided. It is not displayed on the section, and does not give an operator an unpleasant feeling or be mistaken for a failure. Further, according to the second aspect of the present invention, since all the bits of the image signal are invalidated for a certain period of time immediately before the display mode selection is switched by the interrupt to the processor, a relatively small hardware configuration is required. The display control of the processor itself can prevent the display of a disturbed screen when the display mode is switched.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a display mode switching control device of a first invention of the present invention.

FIG. 2 is a block diagram of a conventional device.

FIG. 3 is a block diagram of a blanking controller of the device of the first invention.

FIG. 4 is a block diagram of an image signal processing unit (RAMDAC).

FIG. 5 is a time chart showing the operation of the device of the first invention.

FIG. 6 is a block diagram of an apparatus embodiment of the second invention.

FIG. 7 is an operation flowchart of the apparatus of the second invention.

[Explanation of symbols]

 1 Processor 2-1 1st CRTC 2-2 2nd CRTC 3 Mode register (mode selection part) 4 System bus 5 Multiplexer part 6 Image signal processing part 7 Display part 11 Blanking control part

Claims (2)

[Claims] 1. A display unit capable of displaying an image in any of two or more display modes, an image signal processing unit for outputting an image signal to the display unit, and a display unit of two or more display modes. After the mode selection unit for selecting and instructing any one of them and the instruction for selecting the display mode by the mode selection unit is switched, a blanking signal is output and the image signal processing unit of the image signal processing unit outputs the blanking signal for a predetermined time. A display mode switching control device, comprising: a blanking control unit for suppressing the output of the image signal. 2. A display section capable of displaying an image in any of two or more display modes, an image signal processing section for outputting an image signal to the display section, and immediately before switching of display mode selection. Therefore, for a certain period of time, all bits of the image signal are invalidated,
A display mode switching control device, comprising: an interrupt control unit that outputs an interrupt signal to a control processor.