JPH0620072A - Data driven information processor and data buffer used in this processor - Google Patents

Abstract

PURPOSE:To improve the data processing efficiency of the data driven information processor having a function which uses a degeneration memory space to detect a pair of data. CONSTITUTION:A buffer memory 1 which is provided in a cyclic path and is provided to absorb the fluctuation of the flow rate of packets of data in this cyclic path includes a re-arrangement control unit 10 which rearranges the output order in accordance with prescribed key data of stored data packets. This rearrangement control unit changes the arrangement order of output data packets in accordance with the same discrimination reference as the priority level discrimination reference used by a data pair detecting unit 562. Since a data packet of high probability of firing is quickly given to the data pair detecting unit by rearrangement of output data packets in the data buffer, the degradation of the processing efficiency due to hash collision data packets is prevented; and thus, the data driven information processor which executes a data flow program at a high speed is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data flow type information processing apparatus for executing processing in accordance with given data and a data buffer for temporarily storing the data, and more particularly, to a pair of data utilizing a degenerate memory space. The present invention relates to a data flow type information processing apparatus having a detection function and a data buffer having a data rearranging function suitable for use therein.

[0002]

2. Description of the Related Art Recently, it is required to process a large amount of data at high speed in various fields such as high definition image processing. One of the methods for processing information at high speed is parallel processing for processing a plurality of operations in parallel. There is a data flow type (data driven type) information processing device as one of the processing devices suitable for parallel processing. The data flow type information processing device executes processing according to a data flow program.

A data flow program is described by a directed graph composed of nodes (called actors) indicating operations and controls, and arcs connecting the nodes.

FIG. 13 is a diagram showing an example of a data flow program (data flow graph). In FIG. 13, the node ND1 calculates O for the input arcs a and b.
P1 is applied and output to the node ND3. Node ND2
Applies the operation OP2 to the input arc d and gives the operation result to the nodes ND3 and ND4. Node ND3
The operation OP3 is performed on the data from the node ND1, the input arc c and the data from the node ND2, and the processing result is output. The node ND4 performs the operation OP4 on the data from the node ND2 and outputs the processing result.
In each node, when data (called a token) is available in the input arc, the operation assigned to that node is executed. The execution of an operation is called that the node "fires". As a result of this firing, the input data (input token) is consumed and the output token is generated.

The node ND1 has two input arcs a and b. The node ND1 fires when the input data arrives at the two input arcs a and b, respectively, and the output arc is empty. That is, the operation OP1 is applied to the input data (input token), and the operation result becomes an output token. At this time, the input arc d of the node ND2
If the input data arrives at, the nodes ND1 and ND2 can fire at the same time. Node ND3
Must wait for the operations of the nodes ND1 and ND2 to be completed. The node ND4 can fire after the operation OP2 is executed in the node ND2.

In general, an n-input m-output node can be realized by a combination of basic nodes having a maximum of 2 inputs and 2 outputs. The basic nodes are a calculation node that performs a calculation on the data given to the input arc, a distribution node that copies the input token and outputs it to multiple output arcs, and the data given to the multiple input arcs to the output arc. There are a merging node for transmitting and a control node for controlling a data transmitting route.

In the data flow type processing, the processing is executed based on an execution principle called data driving. In the data driven principle, "all operations are executed when the operands (data) necessary for the execution are prepared". The data driven method includes a static data driven method that allows only one set of input data for a certain process and a dynamic data driven method that allows two or more sets of input data. In the dynamic data driving method, an identifier such as "generation number" is used to identify a plurality of sets of input data. The transmission data includes information identifying the destination node and the like, and is transmitted in the form of packets.

FIG. 14 is a diagram showing the structure of a data packet. In FIG. 14, the data packet includes a flag field F1 that stores a flag indicating a data state such as an unfired flag and a two-output instruction identification flag, and a destination node number field F2 that stores a destination node number that identifies the destination node. , A generation number field F3 for storing a generation number which is a generation identifier at the destination node, an instruction field F4 for storing an instruction specifying an operation to be executed, and operand data for storing data to be processed, that is, operand data It includes fields F5 and F6. The instruction field includes a binary / unary operation instruction identification flag that identifies whether the instruction is a binary operation instruction or a unary operation instruction. This command field F4
The binary / unary operation instruction identification flag included in (1) will be described later.

FIG. 15 is a diagram schematically showing the overall structure of the data driven type information processing apparatus. In FIG. 15, the data driven information processing apparatus 500 has an input port 502 for receiving input data given from the outside, and an input for designating the data driven information processing apparatus 500 among the input data from the input port 502. A branch unit 504 that separates data from input data that is not, a data driven engine 506 that receives input data from the branch unit 504, and performs processing according to an arithmetic instruction included in the input data, and processing from the data driven engine 506. It includes a merging unit 508 that merges the data and the input data from the branching unit 504, and an output port 510 that outputs the data from the merging unit 508.

Input port 502 receives input data provided from the outside. In a multi-processor system including a plurality of processing devices, the input port 502 merges data from different processing devices and then outputs the data. The branching unit 504 outputs the input data that does not refer to the processing device 500 to the merging unit 508, and inputs the input data that refers to the processing device 500 to the data driven engine 5.
It is transmitted to 06.

The data driven engine 506 executes processing according to the data supplied from the branching unit 504. The configuration of the data driven engine 506 will be described in detail later, but the function for updating the instruction code and the destination information (node number) necessary for the next instruction fetch and the data necessary for the processing are prepared. It has a firing control function for detecting (firing) and an arithmetic processing function for performing arithmetic / logical operations on an instruction for which waiting of necessary data has been completed.

This processor 5 from the branching unit 504
The input data that does not refer to 00 and the processing result data from the data driven engine 506 are merged by the merge unit 508. In merging unit 508, data exclusively provided from branching unit 504 and data driven engine 506 is transmitted to output port 510. The output port 510 performs predetermined routing (assignment to the processing device in the multiprocessor system) to the given data and transmits it to the corresponding processing device.

FIG. 16 is a block diagram schematically showing the structure of the data driven engine shown in FIG. In FIG. 16, a data driven engine 506 performs an instruction code update, a node number update, and an ignition detection on a merge unit 550 that outputs given data packets in the order of input and a data packet from the merge unit 550. An ignition control unit 552 with a program memory, an arithmetic processing unit 554 for performing an arithmetic operation on an ignition data packet from this program storage with an ignition control unit 552 according to an instruction included in the instruction field F4, and an arithmetic processing unit 554. A branch unit 556 that receives the processed data or the unfired data packet and distributes the destination to the outside or the inside of the data driving engine 506 according to the destination information (node number) included in the data packet, and the data packet from the branch unit 556 sequentially. It was paid, including data buffer 558 to provide the stored data sequentially to the merge unit 550 in the input order.

Ignition control unit 552 with program storage
Is a pair data detection unit 5 for waiting two operand data to be processed by a binary operation instruction or the like.
62, and a program storage unit 564 for storing a data flow program including a plurality of records storing destination information (node number etc.) and command information. Program storage unit 564 also reads the corresponding data record from this program memory according to the address generated based on the node number data contained in the given data packet, and determines the destination node number field F2 and the instruction of the given data packet. It has a function of updating the contents of the field F4 to the contents of the read data record and outputting the contents.

The pair data detection unit 562 waits for two operand data to be processed by a binary operation instruction or the like as described above. That is, paired data is detected. Here, the paired data is a data packet having the same destination node number and the same generation number. The pair data detection unit 562 includes a queuing memory for queuing this data.

In the structure shown in FIG. 16, the arithmetic processing unit 554 executes the processing only on the data in which the ignition control unit 552 with the program memory detects the ignition. The unfired data packet is not processed by the arithmetic processing unit 554. This unfired data packet is stored in the data buffer 558 by the branching unit 556. The branching unit 556 also sends a data packet to the outside of the device or the data buffer 5 according to the node number information included in the destination number field F2 even for a data packet which is not in an unfired state.
58.

The data buffer 558 is used by the processing device 5.
When the number of data packets flowing through 06 increases, the data packets are temporarily stored so as not to overflow the pipeline of the processing device 506. The data buffer 558 is usually composed of a first-in first-out memory. The data buffer 558 sequentially fetches and stores the data packets input from the branching unit 556, and if the merging unit 550 is in an empty state, the control unit with program storage unit via the data packet merging unit 550 in the stored order. The data packet is transmitted to 552. In the processing device 506, the ignition control 552 with program storage and the arithmetic processing 554 normally form a pipeline, and the data processing is executed while overlapping each other, thereby speeding up the data processing.

FIG. 17 is a diagram showing the functional configuration of the ignition control unit with program storage shown in FIG. FIG. 17
In, the paired data detection unit 562 decodes the instruction in the instruction field F4 of the given input data packet and determines whether the instruction is a unary operation instruction or a binary operation instruction. , Which is activated under the control of the instruction identifying unit 602, and performs a hash operation (which will be described later) on the destination node number and the generation number included in the destination node number field F2 and the generation number field F3 of the input data packet. A read control unit 606 that generates an address in the queuing memory 604 and reads the data (data packet) at the corresponding address.
Then, the priority of the data (data packet) read from the queuing memory 604 by the read control unit 606 and the input data packet is determined according to a predetermined condition, and it is also determined whether the data is a pair of data. Priority determination unit 608 and priority determination unit 608
A packet control unit 610 for performing a predetermined process on the input data packet and the read data (data packet) in accordance with the determination result of. When the priority determination unit 608 determines that the read data (data packet) and the input data packet are paired data, the packet control unit 610 generates an ignition packet and generates a program storage unit. To 564.

The instruction identifying unit 602 has an instruction field F4.
The instruction may be identified by looking at the unary operation instruction / binary operation instruction flag included in.

The queuing memory 604 sets a valid flag (VLD) for a data packet which normally waits for a pair of data and stores the data packet. The priority determination unit 608
The hash collision between the data read from the queuing memory 604 and the input data packet and the firing instruction are determined. At the time of hash collision, the priority determination unit 60
8 determines which data packet is stored in the queuing memory 604 according to a predetermined priority order. At the time of hash collision, the data packet not stored in the queuing memory 604 is transmitted to the program storage unit 564 with the unfired flag NFR set to “1” in the packet control unit 610. Here, the hash calculation performed by the read control unit 606 at the time of address generation and the hash collision in the priority determination unit 608 will be described.

FIG. 18 is a diagram showing the effect of the hash calculation. In the dynamic data driven method, a plurality of sets of input data are allowed for a certain process. An identifier such as a generation number is introduced to identify the plurality of sets of input data. Therefore, the physical space of the memory having the destination node number and the generation number as an address is used as a place for waiting the paired data. As a waiting area for this data, it is desirable to have a memory space containing all combinations of all destination node numbers and generation numbers used. However, when the number of generations and node numbers to be handled increases, it is not realistic from the viewpoint of memory usage efficiency to have a memory space having addresses of all such destination node numbers and generation numbers, and it is economical. Not even the target. Therefore, as shown in FIG. 18, a hash operation is performed on the destination node number and the generation number,
A waiting memory address space whose address is the value obtained as a result is created.

The hash operation means an operation performed for changing a plurality of fields (normal keys) to different arrangements. Performing some predetermined operation on the original key in order to transform the original key into a new key is called a hash operation. There are various methods for this hash operation. A simple hash operation is called the division and remainder method. In this division remainder method,
An appropriate number is selected, the dividend is divided by using the selected number as a divisor, and the quotient and the remainder are obtained. This remainder is the converted key. In this case, the divisor is, for example, 100
If 0 is used, the converted key will be modulo 10 of the original key.
It becomes 00. That is, for example, when the divisor is 1000, the destination node number and the generation number are modulo 100.
A hash address is generated by calculating 0. In this case, as shown in FIG. 18, since the node number / generation number space is compressed into the waiting memory address space by the hash operation, the address of the waiting memory address space (hereinafter referred to as hash address) and the address in the node number / generation number space And one-to-many correspondence. Such overlapping of hash addresses is called hash collision. As the hash operation, there are a folding method, a radix conversion method, a number rearrangement method, and the like, in addition to the above-mentioned division and remainder method.

As shown in FIG. 19, in the node number / generation number space 800, areas ND1 / GN1 and ND2 / G having different destination node numbers ND and generation numbers GN are provided.
There is a state in which N2, ND3 / GN3, and ND4 / GN4 correspond to the hash address HAi in the waiting memory address space. A state in which a plurality of node number / generation number addresses exist for one hash address is called degeneration.

The read control unit 606 performs the above-mentioned hash calculation to generate an address for the queuing memory 604. In this case, even if the data has different destination node numbers and generation numbers, the waiting memory 6
The waiting area of the same address 04 is used. Therefore, hash collision occurs.

Now, when a data packet is written in the queuing memory 604 for queuing the paired data (the queuing data is normally flagged as valid), the destination node number or generation number is different. When data having the same hash address is given, it is necessary to determine which data is preferentially processed. This priority determination is executed by the priority determination unit 608. The priority determination unit 608 compares the priority of the data read from the queuing memory 604 with the input data, writes the data packet with the higher priority to the queuing memory 604, and the data packet with the lower priority is not The ignition flag NFR is set and output. The writing of the data packet to the queuing memory 604 and the turning on / off of the unfired flag are executed by the packet control unit 610. In the following description, the priority determination criteria used by the priority determination unit 608 are (1) a smaller generation number has a higher priority, and (2) a same generation number has a destination node number. It is assumed that the criterion that the smaller is the higher is used.

When a hash collision does not occur and a pair of data is detected, the packet control unit 610 transmits the data packet to the program storage unit 564 with the valid flag off and the unfired flag off.

The program storage unit 564 receives the data packet from the paired data detection unit 562, and identifies the firing of the data packet, and the firing / non-firing of the firing discrimination unit 620. A next instruction fetch unit 624 that generates an address based on the destination node number included in the destination node number field F2 of the input data packet according to the instruction information, and fetches the next instruction from the program memory 622, and this next instruction fetch unit 624. For the data packet fetched in step S6, the contents of the destination node number field F2 and the instruction field F4 of the input data packet are transferred to the next instruction fetch unit 624 according to the firing instruction from the firing identification unit 620.
It includes a packet generation unit 626 that updates with the next destination information and instruction information fetched from the program memory 622 by. The packet generation unit 626 uses the firing identification unit 6
When 20 does not identify the firing, that is, when the non-firing flag of the input data packet is set and is in the ON state, this input data packet is not processed and is output as it is.

The data packet from the packet generator 626 is transmitted to the arithmetic processing unit 554. next,
The operation of paired data detection unit 552 and program storage unit 564 will be described with reference to the operation flow charts of FIGS. 20 and 21.

FIG. 20 is a flow chart showing the operation of the paired data detection unit. The operation of the paired data detection unit will be described below with reference to FIGS. 17 and 20.

When an input data packet is given, the instruction discriminating unit 602 first decodes the instruction (step S1) to determine whether the operation instruction included in the input data packet is a binary operation instruction or a unary operation instruction. A determination is made (step S2). At this time, the binary operation instruction may include both a two-variable operation instruction and a constant operation instruction. Further, as the instruction decoding operation, the decoding and discriminating operation may be performed simply by looking at the unary operation instruction / binary operation instruction flag.

If it is determined in step S2 that it is not a binary operation instruction, the instruction is a unary operation instruction,
Since the paired data is not waiting, the unfired flag of the data packet is reset to the off state (step S
4) It is output.

When it is determined in step S2 that the operation instruction is a binary operation instruction, the read control unit 606 performs a hash operation on the destination node number and the generation number included in the input data packet to generate a hash address, The waiting memory 604 is accessed (step S6).

In step S6, the priority determination unit 60
In step S8, it is determined whether the data packet read from the queuing memory 604 by the read control unit 606 is a valid data packet, that is, whether or not it is a queuing data packet (step S8). This is executed by checking the valid flag for the data packet waiting in the queuing memory 604.

In step S8, if there is no valid data packet, the input data packet is stored in the queuing memory 604 according to the generated hash address by the packet control unit 610 for queuing, and a valid flag is set ( Step S10). At this time, a valid data flag indicating that it is valid data is also set.

In step S8, when there is a valid waiting data packet, the priority determining unit 608 determines whether the destination node number and generation number of the input data packet and the read data packet match / mismatch. That is, it is determined whether or not a hash collision has occurred (step S12).

If it is determined in step S12 that a hash collision has not occurred, it is a pair of data. Therefore, in this state, the packet control unit 610
Generates an ignition data packet, and the unfired flag is reset to the off state and output (step S1).
4).

When it is determined in step S12 that a hash collision has occurred (this is executed by the priority determination unit 608 shown in FIG. 17), the priority order of this input data packet and the read data packet is determined. Is performed. According to the priority standard, the generation numbers are compared first, and the smaller generation number is determined to have higher priority. When the generation numbers are the same, it is determined that the smaller the destination node number is, the higher the priority is. The data packet determined to have a high priority according to this criterion is stored in the queuing memory 604, and its valid data flag is turned on.

On the other hand, the data packet determined to have the low priority is output with its unfired flag set to the ON state (step S16).

By the above-described processing operation, the paired data detection unit 562 stores a data packet for waiting, saves an input data packet (sets the unfired flag in the ON state and outputs it), and generates a fired packet. Is executed and the processing result is transmitted to the program storage unit 564. Next, FIGS.
The operation of the program storage unit will be described with reference to FIG.

First, the data packet transmitted from the paired data detection unit 562 is discriminated by the firing identification section 660 as to whether the non-firing flag is on or off (step S20). If the unfired flag is in the ON state and the packet is a waiting data packet, it is output as it is. When the unfired flag is in the OFF state and the data packet is a fired data packet, the program memory 622 is accessed for the next instruction fetch of the program instruction (step S22). The destination node number included in the input data packet is used for this access.
At this time, the same hash calculation as that performed by the paired data detection unit 562 may be executed.

According to the data read from program memory 622 in step S22, that is, the data flow program, the following processing is performed on the input data packet. That is, the destination node number of the instruction field F4 and the destination node number field F2 of the input data packet is updated. After this update, the unfired flag is reset and output.

The data packet output from the program storage unit is applied to the arithmetic processing unit 554. If the unfired flag of the input data packet is off, the arithmetic processing unit 554 performs arithmetic processing on the data contained therein according to the instruction contained in the instruction field F4, and outputs the processing result to the operand data field F5. To store.

The arithmetic processing unit 554 does not execute the arithmetic processing when the unfired flag of the input data packet is on.

The output data packet of the arithmetic processing unit 554 is transmitted to the branching unit 556. If the unfired flag of the given data packet is in the off state, the branching unit 556 selectively outputs to one of the outside of the device and the data buffer 558 according to the destination node number contained in the destination node number field F2 contained therein. Output. When the unfired flag of the given data packet is in the ON state, this branching unit 556 transfers the input data packet to the data buffer 558.

The data buffer 558 is the processing unit 5
The fluctuation of the data packet flowing through 06 is absorbed.

[0046]

As described above, the data packet is transferred to the data detection unit 562.fwdarw.program storage unit 564.fwdarw.arithmetic processing unit 554.fwdarw.branch unit 556.fwdarw.data buffer 558.fwdarw.merging unit 5.
The information processing based on the data flow program stored in the program storage unit 564 progresses by continuing to cycle from 50 to the pair data detection unit 562 ....
The circular path of this data packet is usually pipelined.

Similarly, in the paired data detection unit 562, a data packet whose unfired flag is turned on is paired data detection unit 562 → program storage unit 564 → arithmetic processing unit 554 → branch unit 5 as well.
56-> data buffer 558-> merging unit 550 and a pipelined cyclic path similar to the data packet in the process of data processing. The data packet whose on-fire flag is on is stored in the program storage unit 564.
And the queuing memory 604 in the data detection unit 562 without being processed by the arithmetic processing unit 554.
This patrol path continues to be patrolled until the waiting area of is available.

As the number of unfired data packets increases and the number of data packets stored in the data buffer 558 increases, the pipeline in this cyclic path becomes longer. For this reason, there arises a problem that the speed at which the data packet, which may be processed immediately, travels through this cyclic path is reduced.

A data packet which can be immediately processed is detected by the paired data detection unit 562, is immediately set to the firing state, and is not fired unless an empty area is formed in the waiting memory 604 of the paired data detection unit 652. The state data packet will remain in the unfired state forever and the process will not proceed. As a result, the overall processing speed decreases. This state will be described in more detail below.

FIG. 22 is a diagram showing an example of the flow of data packets in the cyclic path in the data driven type information processing apparatus. In FIG. 22, the data buffer 558 is
Merging unit 550, pair data detection unit 562, program storage unit 564, arithmetic processing unit 554
Since there are more data packets than can be accommodated in the pipeline including the branch unit 556, a plurality of data packets are stored to absorb the overflow of this pipeline. The data packet stored in the data buffer 558 is provided to the paired data detection unit 562 via the merging unit 550 when the input of the merging unit 550 has a space.

Attention is now paid to the data packets 110a, 101b and 110b included in the data buffer 558. It is assumed that these data packets 101b, 110a, and 110b redundantly use the same waiting area of the waiting memory 604 included in the paired data detection unit 562. That is, the same hash address is generated. The data packet 101b has its unfired flag NRF in the off state (“0”), and is detected as the paired data packet 101a waiting in the paired data detection unit 562 and fired. The unfired flag NRF of the data packets 110a and 110b is in the ON state (“1”), and the unfired flag NRF in the data detection unit 562 uses the waiting area of the waiting memory 604. This is a data packet output with the NRF turned on. Based on this assumption, the flow of data packet processing will be described.

The data buffer 558 is a first-in first-out memory. The output order of the data packets 110a, 101b, and 110b does not change.

First, the data packet 110a is given to the data detection unit 562. The waiting area for the data packet 110a is used by the data packet 101a having a high priority. Therefore, the data packet 110a is output again with the unfired flag turned on.

Next, the data packet 101b is given to the data detection unit 562. The data packet 101b forms a pair with the data packet 101a stored in the queuing memory 604, and thus is detected as paired data. This allows the data packet 101
The waiting area in which a has been stored becomes an empty area. The data packets 101a and 101b are output to the program storage unit 564 as paired data.

Then, when the data packet 110b is transmitted to the data detection unit 562, the waiting memory 6
No. 04 is stored in the corresponding waiting area. Until another data packet 110a is input to the data detection unit 562 again, the same queuing area is shared, and if another high-priority data packet is not input, the data packet 1
When 10a is given to the pair data detection unit 562,
This data packet 110a and data packet 110b
Are detected as paired data.

Therefore, until the corresponding queuing area in the queuing memory 604 becomes empty, the low priority data packet continues to circulate in the circular path (pipeline) in the unfired state. Also, the data packet 101b
Is paired with the data packet 101a, but is given to the paired data detection unit 562 in the order of input to the data buffer 558, the processing of the ignitable data packet is delayed, and the processing speed of this processing device increases. descend. The unfired data packets 110a and 110b continue to circulate on this circular path until the data packet 101a is detected as paired data and consumed. The processing of the data packets 110a and 110b is delayed, which reduces the overall processing speed.

The data buffer 558 is composed of, for example, a shift register type first-in first-out memory.
In this case, even if there is a free area in the data buffer 558, the input data packet is
The delay time received at 58 is constant. Therefore, due to the delay in the data buffer 558, the valid data packet cannot circulate in the circular path at high speed, which reduces the processing speed.

Therefore, an object of the present invention is to provide a data driven type information processing apparatus capable of processing a data flow program at high speed and efficiently.

Another object of the present invention is to provide a data driven type information processing apparatus capable of suppressing the generation of unfired data packets.

Still another object of the present invention is to provide a data buffer whose delay time can be changed according to the number of stored data.

Still another object of the present invention is to provide a data buffer capable of improving the processing efficiency of a data flow program.

[0062]

According to another aspect of the present invention, there is provided a data driven type information processing apparatus which receives data from one side of a data cyclic path and temporarily stores the data, and stores the stored data via the cyclic path. A buffer memory circuit for transmitting to the data detection unit is included. The buffer memory circuit includes a storage unit for storing data and a key included in the received input data so that the stored data is stored in a predetermined order according to the input data and the key data included in the stored data. It includes circuit means for rearranging the stored data of the storage unit according to the data and the key data of the stored data.

In the data driven type information processing apparatus according to the second aspect of the present invention, the data rearrangement means comprises means for rearranging the stored data according to the same discrimination criterion as the priority discrimination criterion executed in the paired data detection section. Including.

The data buffer according to claim 3 is arranged along the data transmission line between the input section for receiving the input data and the output section for outputting the output data, and is for sequentially storing and outputting the input data. Of a plurality of data memories connected in cascade with each other and a data memory of a position to be mirrored on this data transmission path, when there is no data stored in the data memory on the output side, the input side First transfer means for transferring the data in the data memory to the data memory on the read output side and a predetermined key included in the data stored in the data memory on the input side provided in the data memory at the position to be mirrored Comparing means for comparing the data with predetermined key data of the data stored in the output side data memory, and the comparison of the output side data memory according to the comparison result of the comparing means. And means for exchanging data with the input side data memory storing data.

[0065]

In the data driven type information processing apparatus according to the present invention, the data packets in the data buffer are arranged by the rearrangement means in a predetermined order according to the key data contained therein and are sequentially transmitted to the paired data detection unit. It
As a result, it becomes possible to provide the data packets to the paired data detection units in the order of efficiently processing the data flow program.

In the data driven type information processing apparatus according to the second aspect, the data packets in the data buffer are rearranged according to the same discrimination criterion as the priority discrimination criterion used in the paired data detection unit. As a result, a data packet having a high possibility of forming a pair and being fired with respect to the data packet in the waiting state is transmitted to the pair data detection unit quickly.

In the data buffer according to the third aspect, the data is transferred from the input side data memory to the output side data memory by the first transfer means when there is no stored data in the output side data memory. The number of storage stages of the data buffer can be changed according to the number of stored data, and the data can be output at high speed.

Further, by exchanging the input side data memory and the output side data memory according to the size of the key data, it becomes possible to always arrange the output data string according to the size of the key data. It becomes possible to easily and surely realize rearrangement of data according to the contents of data processing.

[0069]

1 is a diagram showing the configuration of a data driven type information processing apparatus according to an embodiment of the present invention. In FIG. 1, the configuration of the data driven engine unit is functionally shown.
In the configuration shown in FIG. 1, the same parts as those in the configuration shown in FIG. 16 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, a branching unit 556 and a merging unit 550
And a data buffer 1 for absorbing fluctuations in the flow of data packets. Data buffer 1
Includes a memory unit 2 for storing the data packet from the branch unit 556, and a rearrangement control unit 10 for rearranging the data packet stored in the memory unit 2 according to the magnitude relation of the key data.

The rearrangement control unit 10 detects the key detecting unit 4 for detecting a predetermined key (data) from the input data packet given from the branching unit 556 and each key of the data packet stored in the memory unit 2. The key monitor 3 to be monitored, the key comparison unit 5 that compares the key information from the key monitor 3 and the key information from the key detection unit 4 and outputs a signal indicating the magnitude relationship, and the comparison result from this key comparison unit 5. An array control unit 6 is included for switching the order of arraying the data packets in the memory unit 2 according to the information.

As shown in FIG. 2, the keys to be used are the non-fire flag NFR (“1” when non-fire), from the top.
Generation number and destination node number are used. The generation number and the destination node number are used as a discrimination criterion for discriminating the priority in the paired data detection unit 562. Therefore, this paired data detection unit 562
A determination criterion similar to the priority determination criterion used for is used as a data packet rearrangement evaluation criterion in the data buffer 1.

In FIG. 1, the pair data detection unit 56.
2 is a waiting memory 6 for storing waiting data packets.
04, and a writing / control unit 20 for storing and reading a data packet in the waiting memory and determining the priority. This writing / reading control unit 20 has an instruction identifying unit 602 and a reading control unit 60 in the configuration shown in FIG.
6, including a priority determination unit 608 and a packet control unit 610. Next, the operation will be described. Units excluding the data buffer 1, that is, the merging unit 550, the pair data detection unit 562, the program storage unit 564,
Operations of the arithmetic processing unit 554 and the branching unit 556 are similar to those of the conventional data driven type information processing apparatus shown in FIGS. Therefore, in the following description, the data buffer 1 used in the present invention will be described.
Only the operation of will be described.

The key detector 4 generates key data by extracting a predetermined key, that is, an unfired flag NFR, a generation number and a destination node number from the input data packet supplied from the branching unit 556. The key monitor 3 monitors the key data of each data packet stored in the memory unit 2. At the time of data input, the key comparison unit 5 receives the key data from the key monitor 3 and the key data from the key detection unit 4 and compares the sizes. The arrangement control unit 6 rearranges the data packets so that the output data packets are arranged in the ascending order of the key data according to the comparison information from the key comparison unit 5. Therefore, when the data packet is output from the memory unit 2, (1) the data packet in which the non-fire flag NFR is not set (NFR = 0) is the data packet in which the non-fire flag is set (NFR = 1). ), (2) the data packet having the same non-firing flag NFR has a smaller generation number, and (3) the data packet having the same non-firing flag NFR and the same generation number. Is output first when the destination node number is small.

A data packet in which the non-fire flag NFR is not set, that is, in the off state, is likely to have a pair of data packets stored in the waiting memory 604 or will be stored in the waiting memory 604 from now on. Also,
If the unfired flags NFR are in the same state, the smaller generation number is more likely to be executed first. If the unfired flag NFR is in the same state and the generation numbers are the same, the smaller destination node number is more likely to be processed first (in the data flow program, the normal data arc has a smaller node number). Flowing from one to the other). Therefore, by rearranging and outputting the output data according to such a priority order, it is possible to quickly output a data packet that is likely to be processed earlier, and the processing efficiency of the data flow program is improved. This operation will be described with reference to FIG.

The data buffer 1 has a data rearrangement function, that is, a data rearrangement function. Therefore, FIG.
As shown in, when the data packet 110a, the data packet 101b, and the data packet 110b are input in this order, the data packet 101b with the unfired flag NRF in the off state is output first. The data packet 101b is supplied to the pair data detection unit 562 and forms a pair with the data packet 101a stored in the queuing memory 604. As a result, an ignition packet is generated by the data packets 101a and 101b, and an empty space is created in the waiting area of the data memory 604.

Next, the data packet 110a is supplied to the data detection unit 562 and stored in the waiting area of the waiting memory 604.

After that, the data packet 110b is given to the paired data detection unit 562. Due to the rearrangement of the output data, the time difference between the data packet 110a and the data packet 110b being given to the data detection unit 562 is smaller than before.
While the data packet 110a and the data packet 110b are output from the memory unit 2, there is no input of a data packet having a higher priority to the data buffer 1, or the data packet input from the outside from the merging unit 550 is this data packet. 110a and 110b
The data packet 110a and the data packet 110b are successively provided to the paired data detection unit 562 unless interrupted during this period. Therefore, the data packet 11
0a and the data packet 110b are detected as paired data by the paired data detection unit 562 and fired, the possibility that a data packet accessing the same waiting area of the waiting memory 604 will appear is reduced. A specific example of the output rearrangement of the data packet will be described.

FIG. 3 schematically shows a state in which the output order of the output data in the data buffer 1 is rearranged.
Consider a state where the key data 10106H is waiting in the waiting memory 604. Now, the output data in the memory unit 2 is 00405H, 00505H, 102
Consider a state in which a data packet of 00206H is newly input when the data packets are arranged in the order of 06H and 10307H. This newly input data packet 00106
H is paired with the waiting data packet (key data 00106H) in the waiting memory. In this case, under the function of the rearrangement control unit, the newly input data packet (key data 00106H) has the highest priority because the non-fire flag NRF is off (“0”) and the generation number is “01”. Is output. The data packet output with the highest priority forms a pair of data with the waiting data packet. As a result, the queuing data packet is consumed, a vacant area is promptly created in the queuing area, and the circulation of the non-firing data packet in which the non-firing flag is ON is prevented. Here, it is assumed that the paired data are data packets having the same node number and the same generation number. Since the data packet of the key data 00405H and the data packet of the key data 10405H form a pair as the output data packet, there is a high possibility that the paired data will be given to the pair data detection unit in a short period of time. This makes it possible to speed up the processing of the data flow program and improve the processing efficiency.

As described above, the priority order is determined according to the comparison of the magnitudes of the unfired flags NFR and the priority determination criteria similar to the priority determination in the paired data detection unit 562,
By changing the order of the data packets stored in the memory unit based on this priority and outputting them, data packets that may be processed immediately can circulate at high speed without being disturbed by unfired packets. It is possible to send on the path. Further, by rearranging the order of the output data, the data waiting area can be released quickly. Furthermore, it is possible to reduce the distance between data packets that are likely to be paired data, and the data waiting area in the paired data detection unit can function efficiently, resulting in unnecessary movement in data processing. It is possible to reduce the occurrence of unfired data packets that appear to be occurring. This improves the processing efficiency of the data flow program.

Next, the structure for rearranging the output data according to the priority order of the key data will be described.

FIG. 4 is a diagram showing an example of a specific configuration of the data buffer shown in FIG. In FIG. 4, the data buffer 1 includes latches 110a and 11a having selective input functions, which are cascaded with each other for transmitting an input data packet.
0b, 110c, ..., And 110n, and latches 110a to 1 with a selective input function for transmitting this input data packet.
Output data transmission selection input function latches 210a, 21 that are provided in correspondence with each other and are connected in series.
0b, 210c, ..., And 210n, and the corresponding latches 110i and 210i with a selection input function (i =
a) to n), which extracts the key data from the data packet stored in the corresponding latch, compares the size relationship, and controls the exchange of the data stored in the corresponding latch according to the comparison result. Data replacement control circuits 310a, 310b, 310c, ..., 310n.

The input data packet DI supplied to the input section 101a has a data width of m-1 bit, and the signal line 1
One bit is added to the valid data flag VLD given via 02. Therefore, m-bit data is applied to one input A of this latch with selection function. The selection input function latches 110a to 110n are provided with an input data transfer clock C supplied through the clock input 103.
According to KF, the stored data is transferred to the latch with the selective input function at the next stage. When the valid data flag VLD stored in the latches 110a to 110n is "1"("H" level), it indicates that the data packet stored in the latch is valid. Valid data flag VLD
Is "0"("L" level), it indicates that the data packet contained in the latch is invalid.

Latches 210a to 210n with a selective input function for outputting an output data packet are clock input 2
03 output data transfer clock CKB
In response to the latch, the stored data is latched in the preceding stage (output unit 20
To a latch with a selection input function for output close to 1).

Data exchange control circuits 310a to 310n
Is an n-bit data extracted from the n-bit data stored in the corresponding latch as key data, and transfers the data from the input side latch to the output side latch according to the size relation of the key data. And exchanging data between the input side latch and the output side latch. The comparison result of the data exchange control circuits 310a to 310n becomes a definite state in response to the clock signal CKC applied to the clock input 301.

In FIG. 4, the input data output unit 101b, the status flag FULL output signal line 105, and the signal line 10 for transmitting the clock signal CKF are shown on the right side of the drawing.
6, the signal line 302 for transmitting the clock signal CKC, the signal line 206 for transmitting the clock signal CKB, and the signal line 204 for inputting output data show the state in which this data buffer is connected to the data buffer of the next stage. The data buffer shown in FIG. 4 includes circuit components having the same structure and can be easily expanded. Signal line 1
If the status flag FULL appearing on 05 is "1",
The state where valid data is stored in all of the latches 110a to 110n for input data is shown. Further, the m-1 bit data given from the signal line 204 becomes m bit data together with the validity flag VLD of "0" (given from the signal line 205), and the latch 210
given to n. The status flag EMPTY supplied from the signal line 202 is the latch for this output data 210a ...
210n indicates whether or not there is a valid data packet to be output. This status flag FULL and EMPTY
Correspond to the validity flag VLD given from the signal line 102 and the validity flag VLD given from the signal line 205, respectively.

Next, the data input operation and output operation of the data buffer shown in FIG. 4 will be described. First, the operation at the time of data input will be described with reference to FIG. 5, which is an operation flow chart thereof.

First, it is determined whether or not the status flag FULL output from the signal line 105 is "0" (step S30). When the status flag FULL is "1", the latches 110a to 11 for this input data
This indicates that valid data is stored in all 0n, indicating that a new data packet cannot be input. Therefore, this status flag FULL
No data packet is input until is "0".

When the status flag FULL becomes "0", the data packet DI is input to the signal line 101a. m-
The 1-bit data packet DI has a valid data flag VL.
It is applied to latch 110a together with D ("1"). Here, in the initial state, reset RESET is applied to latches 110a to 110n and 210a to 210n, and these latches 110a to 110n and 210a.
Valid data flag VLD included in ˜210n is “0”
Is reset to.

When the status flag FULL is "0", the data packet DI is given via the signal line 101a. The m-1 bit data packet is supplied to one input A of the latch 110a as m bit data together with the validity flag VLD indicating the validity from the signal line 102. The operation of fetching and shifting the input data packet DI, the stored data Di, and the valid data flag VLD (hereinafter, both are simply referred to as data) in the latches 110a to 110n is controlled by the clock signal CKF. That is, when the clock signal CKF is applied via the signal line 103, the latches 110a to 110n transfer the latched data to the latch of the next stage and latch the newly applied data. For example, latch 11
The data stored in 0a is transferred to the latch 110b, and the data stored in the latch 110b is transferred to the latch 1b.
It is transferred to 10c (step S32).

Next, in FIG. 4, the stored data of the latches facing each other are compared. Data exchange control circuit 3
10a to 310n are input data latches 110i
(I is one of a to n) has valid data (valid data flag VLD is "1") and output data latch 210i does not have valid data (valid data flag VLD = "0"). It is determined whether or not (step S34). When valid data exists in the input data latch 110i and does not exist in the output data latch 210i, the data DI stored in the latch 110i and the data stored in the output side latch 210i. Exchange with Qi is executed (step S3).
8).

Input data latch 110i has valid data (VLD = 1) and output side latch 210i.
If there is valid data, the desired n-bit key data is extracted from the stored data DI and Qi, and the size of the key data Di (n) and Qi (n) is compared (step S36). Input data latch 110i
If the key data Di (n) of the data Di stored in the data is smaller than the key data Qi (n) of the data Qi stored in the output data latch 210i, the data replacement control circuit Data Di under control
And data Qi are exchanged via the other input port B (step S38).

In step S36, the key data Di of Di stored in the latch 110i for input data is stored.
If (n) is greater than or equal to the key data Qi (n) of the data Qi stored in the output data latch 210i, data exchange is not executed. Then, it waits for input data to be given again. As a result, the latch 210a closest to the output unit 201 always stores the data having the smallest key data Qi (n). For example, in the initial state, when data DI is first applied, it is stored in input data latch 110a. The data stored in the latch 110a is transferred to the latch 210a (for the first time, the input data packet DI
This is because valid data is not stored in the output latch 210a when is given). When an input data packet is applied next, the key data of the data stored in latch 210a and the key data of the newly applied input data are compared in magnitude. Data is exchanged or not according to the comparison result of this magnitude. Next time a new data packet is stored,
This second data packet is transferred to the latch 110b and then to the latch 210b (a state in which output data has not been output yet). The key data of the third input data packet is compared with the key data of the data stored in the latch 210a.
By repeating this operation, the data having the smallest key data is latched in the output data latch 210a, and the data having the second smallest key data is latched in the output data latch 210b in the next stage. That is, in the data latches 210a to 210n on the output side, the output data is rearranged and stored according to the magnitude relation of the key data. Next, the data read operation will be described with reference to FIG. 6 which is an operation flow chart thereof.

When outputting data, first the signal line 2
It is determined whether or not the status flag EMPTY given from 02 is "1" (step S40). When the status flag EMPTY is "1", the latch 210a
Since valid data is stored in, data can be output. When the status flag EMPTY is "0", there is no data to be output, so the data output is in a waiting state until the status flag EMPTY becomes "1".

At the time of data output, output data clock signal CKB is applied onto signal line 203. As a result, the latches 210a to 210n perform the shift operation, transmit the latched data to the latch at the previous stage via the output terminal Y, and the output unit 201 outputs the output data packet QO (step S42).

Next, the replacement control circuits 310a to 310 are again provided.
At n, the determination of data transfer and exchange between each corresponding latch 110i and latch 210i is executed. That is, in step S44, the valid data flag V of the data Qi stored in the output data latch 210i.
It is determined whether LD is "1". When the valid data flag VLD is "0", there is no valid data in the output data latch 210i, and therefore data is transferred from the corresponding input data latch 110i (when valid data exists in the latch 110i). ).

In step S44, the latch 210i
When the valid data flag VLD of the data Qi included in is "1", the key data Di (l) and Qi (n) of the data Di and Qi are compared in magnitude. Data D included in the input data latch 110i
When the key data Di (l) of i is smaller than the key data Qi (n) of the output data Qi, data exchange is performed between the latch 110i and the latch 210i (step S48).

The key data Di (l) is the key data Qi.
In the case of (l) or more, data exchange is not performed. The determination operation in step S46 and step S4
The data exchange operation in 8 ensures that the data having the minimum key data Qi (n) is arranged in the latch 210a.

In the data buffer shown in FIG. 4, the number of stages for storing the data is variable according to the number of stored data. That is, data is input when clock signals CKF and CKC are applied, and data is output immediately when clock signals CKB and CKC are applied. Therefore, unlike the buffer memory having the shift register configuration, the transmission delay received by the data packet can be changed according to the number of valid data, and the data packet can always be immediately and rapidly transmitted to the data detection unit. . Next, the specific configuration and operation of each circuit portion will be described.

FIG. 7 is a diagram showing the configuration of the latch with selection input function shown in FIG. This latch with selection input function 11
0 (and 210) is one of the input data DA (m bits) given to the input port A and the input data DB (m bits) given to the input port B at its clock input C.
It takes in and outputs according to clock signals CK1 and CK2 applied to K1 and CK2. That is, when the clock signal CK1 is given to the clock input CK1, the input data DA given to the input port A is taken in, and when the clock signal CK2 is given to the clock input CK2, the input data B given to the input port B is taken. Take in. The latch 110 (210) outputs the data taken in at the falling edge of the corresponding clock signal from its output port Y. In the configuration shown in FIG. 4, the latch 110 (210) receives the output data from the adjacent latch at the input port A and faces the corresponding input port B (the output data latch or the input data latch).
Receive the output of. As a result, data can be exchanged and transferred.

FIG. 8 is a diagram showing an example of a specific structure of the latch with the selective input function. In FIG. 8, the latch with selective input function includes an n-channel MOS transistor (insulated gate type field effect transistor) 401 that passes a signal applied to the input port A in response to the clock signal CK1 applied to the clock input CK1, and a transistor. Four
Inverter circuits 402 and 404 which are connected in cascade and which receive the output of 01, and the gate of which receives the signal applied to the clock input CK1 through the inverter circuit 410, and the output of the inverter circuit 404.
N-channel MOS transistor 4 transmitting to the input of 02
06 and the clock signals CK1 and CK2 applied to the clock inputs CK1 and CK2, respectively.
Circuit 428, RS flip-flop 412 reset in response to the output of OR circuit 428 and set in response to the output of inverter circuit 410, and inverter circuit 4 in response to output φ1 of RS flip-flop 412.
N-channel MOS for transmitting the output of 04 to the output port Y
A transistor 408 is included. RS flip-flop 41
2 is set to the set state in response to the rise of the signal applied to the set input S, sets its output signal φ1 to "H", and is set to the reset state in response to the rise of the signal applied to the reset input R. , Its output signal φ1 is "L"
Fall to.

The latch with selective input function further transmits an n-channel M for transmitting the signal applied to the input port B in response to the clock signal CK2 applied to the clock input CK2.
The OS transistor 414, two stages of cascaded inverter circuits 416 and 418 that amplify the signal transmitted by the transistor 414, an inverter circuit 424 that inverts the clock signal CK2, and an inverter circuit that responds to the output of the inverter circuit 424. An n-channel MOS transistor 422 that returns the output of 418 to the input of the inverter circuit 416, and an RS flip-flop that is set in response to the output of the inverter circuit 424 and is reset in response to the output of the OR circuit 428. 426,
It includes an n-channel MOS transistor 420 transmitting the output of inverter circuit 418 to output port Y in response to output signal φ2 of RS flip-flop 426.

In this latch with selective input function, the driving force of inverter circuits 404 and 418 is made larger than the driving force of inverter circuits 402 and 416. As a result, when the transistors 406 and 422 are turned on, a latch circuit is formed.

This latch with selective input function further includes n channel MOS transistors 430 and 432 which reset the inputs of inverter circuits 402 and 416 to the ground potential in response to the reset signal applied to reset input RESET. The operation of the latch with selective input function shown in FIGS. 7 and 8 will now be described with reference to FIG. 9 which is an operation waveform diagram thereof.

Now, assume that the flip-flop 412 is in the set state and the signal φ1 is "H". In this state, it is assumed that the transistor 408 is in the on state and the data given to the input port A is output from the output port Y. In this state, the transistor 406 is on, and the inverter circuits 402 and 404 and the transistor 406 form a latch circuit. The RS flip-flop 426 is in the reset state, and the signal φ2 is at the "L" level.

In this state, when the clock signal CK1 applied to the clock input CK1 rises to "H", the output of the inverter circuit 410 becomes "L" and the output of the OR circuit 428 becomes "H". As a result, the RS flip-flop 4
12 is reset, the signal φ1 falls to "L", and the transistor 408 is turned off. On the other hand, the transistor 401 is turned on in response to the clock signal CK1, and passes the data DA applied to the input port A. Transistor 406 is still off and the data from transistor 401 is simply amplified by inverter circuits 402 and 404.

When the clock signal CK1 falls to "L", the transistor 401 is turned off and the transistor 40 is turned off.
6 is turned on, and the signals given up to that point are the inverter circuits 402 and 404 and the transistor 40.
It is latched by a latch circuit composed of 6. The output signal of inverter circuit 410 rises to "H", RS flip-flop 412 is set, and signal φ1 rises to "H". As a result, the inverter circuit 404
Is transmitted to the output port Y and is output as output data DO.

Then, when the clock signal CK2 applied to the clock input CK2 becomes "H", the output of the OR circuit 428 becomes "H", the RS flip-flop 412 is reset, and the signal φ1 falls to "L". . Transistor 414 is turned on in response to clock signal CK2, and passes the signal applied to input port B. Transistors 414 and 422 are still off, and the signal applied to input port B is amplified by inverter circuits 416 and 418.

Next, when the clock signal CK2 falls to "L", the transistor 414 is turned off and the transistor 422 is turned on. As a result, the signals given up to that point are converted into inverter circuits 416 and 41.
8 and the transistor 422. The inverter circuit 42 responds to the fall of the clock signal CK2.
The output of 4 rises to "H", and RS flip-flop 4
26 is set, the signal φ2 rises to "H", and the transistor 420 is turned on. As a result, the output of the inverter circuit 418 is transmitted to the output port Y.

As described above, when the clock signal is applied to the clock input CK1, the signal applied to the input port A is selected and applied to the input port B when the clock signal is applied to the clock input CK2. The output signal is output.

In the structure shown in FIG. 8, when the clock signal CK1 or CK2 rises to "H", the transistors 408 and 420 are turned off and the signal state of the output port Y may become unstable. To be
In this case, a latch circuit activated by a signal obtained by ORing the clock signals CK1 and CK2 may be further provided at the output port Y. This makes it possible to transfer the data reliably. This latch circuit is in a through state in which the applied signal is passed as it is when the clock signals CK1 and CK2 are "L".

The structure of such a latch circuit includes inverter circuits 402 and 404 and a transistor 406.
It is possible to apply the configuration of the latch circuit consisting of.

If the configuration shown in FIGS. 7 and 8 is made to correspond to the configuration shown in FIG. 4, the output of the adjacent latch circuit is given to the input port A, and the corresponding input which faces the input port B is provided. The output of the latch from the output side or the output side is given. The clock input CK1 is a clock signal C
It is KF or CKB, and the comparison result instruction signal from the data exchange control circuit is applied to the clock input CK2.

The data latched in the latch with selective input function is a (m-1) -bit data packet and a 1-bit valid data flag VLD indicating whether the latched data is valid or not. is there. If the valid data flag VLD is "1", it indicates that the data stored in the buffer is valid.

FIG. 10 shows a structure of the data exchange control circuit shown in FIG. In FIG. 10, data exchange control circuit 310 receives n-bit data via signal lines 301 and 302. The n-bit data includes (n-1) -bit key data and 1-bit valid data flag VLD. In FIG. 10, in order to distinguish this input data, the valid data flag of one input data is shown as VLDA, and the valid data flag of the other input data is shown as VLDB.

The data exchange control circuit 310 further receives an input port A for receiving (n-1) -bit key data out of the n-bit data supplied from the signal line 301.
And the B port that receives (n-1) -bit key data out of the n-bit data provided via the signal line 302, and the size of the key data provided to these input ports A and B are compared, and the comparison is made. Output port LT that outputs the result
And a output LT of the comparator 350
3-input AN for receiving (output port and output signal are indicated by the same reference numeral) and valid data flags VLDA and VLDB
A comparison is made between a D circuit 310, a gate circuit 320 that receives a valid data flag VLDA at its true input and a valid data flag VLDB at its false input, and an OR circuit 330 that receives the output of the AND circuit 310 and the output of the gate circuit 320. AN receiving instruction signal CKC and output of OR circuit 330
A D circuit 340 is included. AND instruction circuit 340 generates a replacement instruction signal CKCH for exchanging data. This signal CKCH is the clock signal CK shown in FIGS. 7 and 8.
Corresponds to 2.

The comparator 350 outputs "1" from its output port LT when the (n-1) -bit data given to the input port A is smaller than the (n-1) -bit data given to the input port B. The signal of "" is output. In this case, the comparator 350 rearranges the output data in ascending order of the key data. It is possible to rearrange in descending order by reversing the criterion of the comparator 350. In the following description,
Since it is necessary to arrange the data packets in ascending order of the key data, the operation when the comparator 350 rearranges the data in ascending order will be described. It can be easily realized when rearranging the data in descending order.

Of the outputs from the two latches 110 and 210, n-bit key data is applied to the data exchange control circuit 310. The comparator 350 compares the magnitudes of the (n-1) -bit data values given to the input ports A and B, respectively. When the data value given to the input port A is smaller than the (n-1) -bit data value given to the input port B, the output port LT becomes "1".

AND circuit 310 receives output LT of comparator 350 and valid data flags VLDA and VLDB. The valid data flag VLDA is a flag indicating validity / invalidity of the data stored in the data latch provided on the input side, and the valid data flag VLDB is the data stored in the latch provided on the output side. Valid /
This is a flag indicating invalidity. The AND circuit 310 has 3
When all the inputs are "H"("1"), the "H" signal is output. Therefore, the AND circuit 310 outputs the signal of "1" in the following cases. That is, the valid data flags VLDA and VLDB are both "1" and the output LT of the comparator 350 is "1". In this state, the valid data is stored in the input data latch 110, the valid data is stored in the output data latch 210, and the input data latch 110 is stored.
This is the case where the key data of the data stored in is smaller than the key data of the data latched by the output data latch 210.

The gate circuit 320 uses the valid data flag V
The signal of "1" is output only when LDA is "1" and the valid data flag VLDB is "0". The OR circuit 330 outputs a signal of "1" when one of the outputs of the AND circuit 310 and the gate circuit 320 is "1".
The AND circuit 340 responds to the clock signal CKC with an O signal.
The output of the R circuit 330 is transmitted. Therefore, the output CKCH of the AND circuit 340 becomes "1" in the following two cases. (1) Valid data is latched in both the input data latch 110 and the output data latch 210, and the key data stored in the input data latch 110 is higher than the key data stored in the output latch 210. When it is small, and (2) when valid data is latched in the input data latch 110 and valid data is not latched in the output data latch 210.

The output signal CKCH of the AND circuit 340 is
It is applied to clock input CK2 shown in FIGS. 7 and 8. Thereby, the exchange of data is realized.

FIG. 11 is a signal waveform diagram representing an overall operation of the circuit shown in FIG. The overall operation will be briefly described below.

When the input data DI is supplied, the clock signal CKF is supplied after confirming that the status flag FULL is "0". As a result, the input data latches 110a to 110n fetch, latch and output the input data.

Then, the comparison control signal CKC is given,
The data exchange control circuit 310 outputs the comparison result according to the control signal CKC. According to the control signal CKC, the replacement control signal CKCH becomes "1" or "0", and the data rearrangement is executed.

When the status flag FULL is "1",
This indicates that the valid data is fully stored in the data buffer 1 and that new data cannot be input.

When outputting data, the status flag E
After confirming that MPTY is "1", the output clock signal CKB is applied. After outputting the data, the control signal CKC is given. As a result, the signal CKCH becomes "1" or "0", and the rearrangement of the output data is executed again. When the status flag EMPTY is "0", it means that there is no valid output data in the data buffer 1, and the data cannot be output.

In the data buffer shown in FIG. 4, latches 110 and 210 with selection input function and data exchange control circuit 310 are regularly arranged. That is, in the data buffer 1 shown in FIG. 4, unit circuits having the same circuit configuration are regularly and repeatedly arranged. Therefore, the data buffer 1 can be easily expanded and the number of data that can be stored can be increased.

Furthermore, this data buffer is not only applied to the purpose of rearranging data packets in a data driven type information processing apparatus. Generally, it can be applied to applications in which the arrangement order of data needs to be changed according to a predetermined rule. The present invention can be applied to applications in which the arrangement order of data is determined according to the size relation of key data (may be the data itself) included in the data.

FIG. 12 shows the general structure of this data buffer. In FIG. 12, a data buffer circuit 900
Is a three-stage cascaded data buffer 1a,
1b and 1c, and an input / output control unit 950 for controlling input / output of data in this data buffer. The data buffers 1a, 1b and 1c have the same structure as the data buffer 1 shown in FIG. The input / output control unit 950 uses the valid data flag V provided along the input data transmission path.
An input FULL receiving an LD and an input EM receiving a valid data flag VLD output along the output data transmission line.
Input PUS for receiving PTY and input request signal INREQ
H and an input POP that receives the output request signal OTREQ,
It includes an output ACKI which outputs an input permission signal INACK, an output ACKO which outputs an output permission signal OTACK indicating permission for an output request, and clock outputs CCK, CCK and CKB which output clock signals CKF, CCK and CKB.

The input / output control unit 950 inputs "1" and "0" of the valid data flag VLD given to the input FULL.
According to the input request signal INREQ
The ACK is set to "1" or "0" to control permission and waiting of acceptance of input data.

The input / output control unit 950 further receives the input EMP.
The enable signal OTACK for the output request signal OTREQ is set to "1" or "0" according to "1" and "0" of the valid data flag VLD given to TY. As a result, data input / output is performed according to the storage status of the data latched in the data buffers 1a-1c. The input / output control unit 950 is an interface circuit, which is supplied with the output request signal OTREQ and generates the clock signals CKB and CKC when the output permission signal OTACK is output. The input / output control unit 950 also receives the input request signal INREQ and inputs the input permission signal INAC.
When K is generated, the clock signals CKF and CKC
To occur.

[0131]

According to the data driven type information processing apparatus of the first aspect, the output data packet is rearranged according to the key data included in the data packet. This allows
The data packets are provided to the paired data detection units in the order of efficiently processing the data flow program, and the data processing efficiency is increased. Further, even if the number of data packets for which the non-firing flag is set in the pair-to-data detection unit increases, the rearrangement of the output data packets does not reduce the data processing efficiency.

In the data driven type information processing apparatus according to the second aspect, the arrangement of the output data packets is executed according to the same discrimination criterion as the priority discrimination criterion in the paired data detection unit. For this reason, data packets that may be paired data can be brought close to each other, the data waiting area of the paired data detection unit can be efficiently used, and generation of unfired data packets can be suppressed. Therefore, the processing efficiency of the data flow program can be improved.

According to the data buffer of claim 3,
The arrangement order of the output data can be changed according to the contents of the stored data, and the output data series arranged according to the processing contents can be obtained at high speed. Further, since the number of storage stages can be changed depending on the number of stored data, there is no vacancy in the storage stage regardless of the number of stored data, high-speed data output can be performed, and data processing can be performed. The efficiency can be improved. Further, since the circuits having the same structure are regularly arranged in this data buffer, the layout thereof is easy and the scale can be easily expanded.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an engine of a data driven type information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of key data used in a data driven type information processing apparatus according to an embodiment of the present invention.

FIG. 3 is a diagram exemplifying a data rearrangement operation in a data driven information processing apparatus which is an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a data buffer shown in FIG.

5 is a flowchart showing a data input operation of the data buffer shown in FIG.

6 is a flowchart showing a data output operation of the data buffer shown in FIG.

FIG. 7 is a diagram showing an external configuration of the latch with selective input function shown in FIG.

8 is a diagram showing a specific configuration of the latch with selective input function shown in FIG.

9 is a signal waveform diagram showing an operation of the latch with selective input function shown in FIGS. 7 and 8. FIG.

10 is a diagram showing a configuration of a data exchange control circuit shown in FIG.

11 is a signal waveform diagram showing an overall operation of the data buffer shown in FIG.

12 is a diagram showing a configuration when the data buffer shown in FIG. 4 is expanded.

FIG. 13 is a diagram showing an example of a data flow graph.

FIG. 14 is a diagram showing a structure of a data packet used in an engine of a data driven type information processing apparatus.

FIG. 15 is a diagram showing an overall configuration of a data driven type information processing apparatus.

16 is a block diagram showing a configuration of a data driven engine shown in FIG.

17 is a block diagram showing a configuration of an ignition control unit with a program storage shown in FIG.

FIG. 18 is a diagram for explaining a hash operation.

FIG. 19 is a diagram for explaining degeneracy of a memory space.

FIG. 20 is a flowchart showing an operation of the paired data detection unit shown in FIG. 17.

21 is a flowchart showing the operation of the program storage unit shown in FIG.

FIG. 22 is a diagram for explaining a problem of a conventional data driven type information processing device.

[Explanation of Codes] 1 data buffer 2 memory unit 3 key monitor 4 key detection unit 5 key comparison unit 6 array control unit 10 rearrangement control unit 110a to 110n input data selection input function latch 210a to 210n output data selection input Latch with function 310a to 310n Data exchange controller 506 Data driven engine 550 Merge unit 552 Ignition control unit with program memory 554 Arithmetic processing unit 556 Branch unit 558 Data buffer 562 Pair data detection unit 564 Program storage unit 900 Data buffer circuit 950 Input / output Control unit

Claims (3)

[Claims] 1. A pair data detection means having a data circulation path and detecting paired data from data on the data circulation path, wherein the pair data detection means fires when pair data is detected. A data driven information processing apparatus having a function of executing corresponding processing, wherein the data driven information processing apparatus receives data from one of the data cyclic paths and temporarily stores the data, and stores the stored data via the cyclic path to the paired data. The data includes key data for determining an arrangement order, and the buffer memory means arranges the stored data in a predetermined order according to the key data included in each data. So that the stored data is rearranged according to the key data contained in the received data and the key data of the stored data. Type information processing apparatus. 2. The data driven type information processing apparatus according to claim 1, wherein the paired data detection means has a degenerate memory space and a waiting memory means for temporarily storing data to be paired. When data to be formed into a pair is given, and when the data is already stored in the address to store the data to be formed into the received pair, which data is stored in the queuing memory according to a predetermined priority order. Means for rearranging the stored data according to the key data according to the same priority as the priority determined by the priority determination means. Including. 3. A plurality of data storage means connected in series and arranged along a data transmission path having a data input section and a data output section for sequentially storing and outputting input data, said data transmission The data of the input side data storage means is provided to the data storage means at the position of the mirroring target along the path, and when the output side data storage means does not have effective storage data, Transfer means for transferring to the data storage means at the position of the mirroring target along the data transmission path, and predetermined key data and output part data storage means included in the data of the input side data storage means Comparing means for comparing with predetermined key data included in the data, and stored data of the corresponding output side data storing means and corresponding input according to the comparison result of the comparing means. Including the exchange means for exchanging and storing data side data storage means, data buffer.