JPH06196653A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide an oxidation-resistant film near the upper edge part of a capacitor trench so as to have a capacitor electrode and a capacitor oxide film separated from each other. CONSTITUTION:An N<+>-type impurity layer 14 which is the one side capacitor electrode is formed on the surface of a P-type silicon substrate 11 in a trench 13 formed in the substrate 11 and a capacitor oxide film 16 is formed on the inner wall of the impurity layer 14. The trench 13 is filled with a polycrystalline silicon film 17 which is the other side capacitor electrode. A silicon nitride film 27 which is oxidation-resistant is formed on the surface of the polycrystalline silicon film 17 and near the upper edge part 13a of the trench 13 and the rest of the part of the polycrystalline silicon film 17 is covered with a silicon oxide film 25. A gate electrode 20 is formed on the substrate 11 and near the upper edge part 13a of the trench 13 with a gate oxide film 21 therebetween. An N<+>-type impurity layer 18 which is a drain region is formed and an aluminum wiring (bit line) 24 which is formed on an interlayer insulating film 22 is connected to the N<+>-type impurity layer 18 through a contact hole 23 formed in the interlayer insulating film 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a groove type capacitor electrode.

[0002]

2. Description of the Related Art As a memory cell of a dynamic RAM has been highly integrated, a capacitor which is a constituent element of the memory cell has been miniaturized. However, the capacitor capacity is S / S for soft error prevention and sense amplifier sensing. A value of several tens of fF is necessary to secure the N ratio. Therefore, in order to cope with this miniaturization, there is a memory cell in which the capacitance is increased by forming a capacitor having a groove formed in a conventional semiconductor substrate.

FIG. 4 is a sectional view showing the structure of a conventional memory cell having a groove type capacitor electrode. A field oxide film 12 for element isolation is formed on a P-type silicon substrate 11, and a groove 13 is opened by a lithography process.
N ⁺ by ion implantation on the surface of The type impurity layer 14 is formed. N ^{+ in the} next lithography process Type impurity layer 15 is formed, and then N ⁺ Capacitor oxide film 16 on layers 14 and 15
Is formed.

Further, a polycrystalline silicon film 17 to which a constant voltage is applied is formed on the capacitor oxide film 16 and the field oxide film 12.
Capacitor electrodes made of is formed, on its side N ⁺ Of the source region N ^{+ which} is in electrical contact with the type impurity layer 14 N ⁺ of the drain region is formed on the surface of the substrate on the side of the gate electrode 20 with the gate impurity film 19 and the gate oxide film 21 interposed therebetween. Type impurity layer 18
Is formed.

As described above, the memory cell composed of one switching transistor and one capacitor is
Information is written to and read from the capacitor by controlling the switching transistor.

However, in such a structure, the width W1 of the capacitor electrode extending from the groove upper edge portion 13a in the source region direction needs to be about 0.5 μm in consideration of the misalignment, and the source region is also required. Width W2 is N ⁺ Considering the misalignment between the layer 15 and the gate electrode 20, about 1.0 μm is required, so that a margin of about 1.5 μm is required between the gate electrode 20 and the groove upper edge portion 13a. This hinders miniaturization of the memory cell and is not preferable.

FIG. 5 is a sectional view showing the structure of a conventional memory cell having a groove-type capacitor electrode, which is an improvement of the structure of FIG. 4 in terms of miniaturization. 4 is different from FIG. 4 in that the gate electrode 20 is provided on the upper edge portion of the groove 13 without extending the capacitor electrode on the substrate.
The configuration is such that it is brought close to a.

As a result, the alignment margin shown in FIG. 4 is not necessary, and miniaturization is possible. Further, the silicon oxide film 22 is formed on the entire surface including the gate and the capacitor electrode portion by the CVD method.
To form a contact hole 23, and an aluminum wiring 24 serving as a bit line is formed through the contact hole 23 to form N ^{+ in the} drain region. Connected with layer 18.

However, there is a problem with the configuration shown in FIG. In the manufacturing process of the memory cell, an oxidation process such as formation of a gate oxide film is performed several times even after the formation of the capacitor electrode, so that the surface of the polycrystalline silicon film 17 of the capacitor electrode is also oxidized.

The polycrystalline silicon oxide film 25 thus formed is the capacitor oxide film 16 inside the groove and the polycrystalline silicon film.
17 It is also formed in the portion 30 where the surfaces are in contact. In general, when silicon is oxidized, the polycrystalline silicon in the portion 30 is oxidized, so that stress is applied to the inner wall of the groove and the electrical characteristics of the memory cell itself are deteriorated.

[0011]

As described above, in the conventional structure for miniaturizing the gate electrode close to the groove, stress is applied to the inner wall of the groove during the oxidation process during the manufacturing process, and the electrical characteristics are deteriorated. There are drawbacks.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor memory device which achieves miniaturization of a memory cell without deterioration of electric characteristics of the memory cell. It is in.

[0013]

According to another aspect of the present invention, there is provided a semiconductor memory device including a groove formed in a semiconductor substrate, a conductive layer formed on a surface of an inner wall of the groove to serve as one of capacitor electrodes, and a groove including the conductive layer. A capacitor insulating film formed on the inner wall of the substrate, a transistor for data transfer on the substrate near the upper edge of the groove and having a gate electrode on the conductive layer, and insulated from the substrate by the capacitor insulating film. The conductive film to be the other capacitor electrode buried in the groove is covered with the inner wall near the upper edge of the groove exposed from the conductive film so that the capacitor insulating film and the conductive film near the upper edge of the groove do not come into direct contact with each other. And a film having oxidation resistance as described above.

[0014]

In the present invention, due to the presence of the oxidation resistant film, the vicinity of the surface of the capacitor electrode layer which is in contact with the capacitor insulating film is not oxidized by the oxidation step. Therefore, no stress is applied to the inner wall of the groove.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a sectional view showing the structure of a memory cell having a groove type capacitor electrode according to an embodiment of the present invention. A field oxide film 12 is formed on a P-type silicon substrate 11, and a groove 13 is formed in the substrate 11. On the surface of the substrate 11 facing the groove 13, one of the capacitor electrodes N ⁺ A type impurity layer 14 is formed. N ⁺ A capacitor oxide film 16 is formed on the inner wall surface of the groove 13 in which the type impurity layer 14 is formed. A polycrystalline silicon film 17 to be the other capacitor electrode filling the groove 13 is formed and extends to the field oxide film 12. On the polycrystalline silicon film 17, the groove upper edge portion 13
A silicon nitride film 27 having oxidation resistance is formed in the vicinity of a, and the others are covered with a silicon oxide film 25.

A gate electrode 20 is formed on the substrate 11 adjacent to the groove upper edge portion 13 with a gate oxide film 21 interposed therebetween. N ⁺ becomes a drain region on the surface of the substrate 11 on the side opposite to the groove 13 with the gate electrode 20 separated. The type impurity layer 18 is formed. An interlayer insulating film 22 made of a silicon oxide film is deposited on the entire surface including the gate electrode 20 and the capacitor portion, and an aluminum wiring (bit line) 24 and N ⁺ formed on the interlayer insulating film 22. Type impurity layer
18 are connected through a contact hole 23 in the interlayer insulating film 22.

According to the structure of the above embodiment, the groove upper edge 3a is formed.
By providing the gate electrode 20 in the vicinity of the vicinity of the gate electrode 20, it contributes to miniaturization of the memory cell, and the surface of the polycrystalline silicon film 17 serving as the capacitor electrode is in contact with the capacitor oxide film 16 in the vicinity of the groove upper edge 13a. Is covered with a silicon nitride film. Therefore, the surface of the polycrystalline silicon film 17 (capacitor electrode) under the silicon nitride film 27 is not oxidized, and stress is not applied to the inner wall of the groove 13. As a result,
The structure achieves both reliability and miniaturization. 2 and 3 are sectional views showing a method of manufacturing the structure of FIG. 1 in the order of steps.

First, as shown in FIG. 2, a field oxide film 12 for element isolation is formed on a P-type silicon substrate 11. Subsequent lithography process, substrate by RIE method
Groove 13 is formed in 11. After that, N ⁺ is formed on the surface of the substrate 11 facing the groove 13 by thermal diffusion. A type impurity layer 14 is formed.

The resist film used in the above lithography process is stripped off, and a capacitor oxide film 16 is formed in the element region including the inner wall of the groove 13 by thermal oxidation. Next, after sequentially depositing a polycrystalline silicon film 17 and a resist film over the entire surface including the groove 13,
By patterning, the resist film 26 is left in a predetermined portion including on the groove 13. Then, isotropic etching is performed using the resist film 26 as a mask to form a capacitor electrode (polycrystalline silicon film 17). At that time, the polycrystalline silicon film 17 in the vicinity of the groove upper edge portion 3a is also removed.

Next, as shown in FIG. 3, a resist film is formed.
After removing 26, a silicon nitride film is deposited on the entire surface and RI
Etching is performed by the E method until the surface of the silicon substrate 11 is reached. At this time, the silicon nitride film 27 remains on the inner wall of the groove near the upper edge 3a of the groove. That is, the surface of the polycrystalline silicon film 17 which is the capacitor electrode and the capacitor oxide film 16
The portion in contact with is covered with the silicon nitride film.

Next, as shown in FIG. 1, the gate oxide film 21 is formed by thermal oxidation. At this time, the portion of the surface of the polycrystalline silicon film 17 not covered with the silicon nitride film 27 is oxidized, so that the polycrystalline silicon oxide film 25 is also formed. Further, polycrystalline silicon is deposited on the entire surface, and RIE is performed using a resist pattern (not shown) formed thereon as a mask to form a gate electrode 20.

Ion implantation is performed using the gate electrode 20 as a mask, and heat treatment is performed to form N ⁺ which becomes a drain region. A type impurity layer 18 is formed. An interlayer insulating film 22 made of a silicon oxide film is deposited and formed on the entire surface by a CVD method, and N ⁺ A contact hole 23 is provided in the interlayer insulating film 22 on the type impurity layer 18. Aluminum wiring 24 (bit line) is formed on the interlayer insulating film 22,
N ⁺ via contact hole 23 It is electrically connected to the type impurity layer 18.

According to the above structure, the polycrystalline silicon film 17 serving as the other capacitor electrode in the memory cell is set to a constant potential such as 0 V, and the one capacitor electrode N ^+. Information writing to and reading from the capacitor are controlled by turning on and off the switching transistor whose source region is on the gate electrode 20 side of the layer 14.

[0025]

As described above, according to the present invention,
The oxidation resistance film covers the inner wall near the upper edge of the groove exposed from the silicon oxide film, which is the capacitor electrode, so that stress due to the oxidation process does not occur at this part, so the electrical characteristics of the memory cell are improved. It is possible to provide a semiconductor memory device that achieves miniaturization of a memory cell without deterioration of the memory cell.

[Brief description of drawings]

FIG. 1 is a sectional view of a structure according to an embodiment of the present invention.

FIG. 2 is a first cross-sectional view showing the manufacturing process of the configuration of FIG.

3 is a second cross-sectional view showing the manufacturing process of the configuration of FIG. 1. FIG.

FIG. 4 is a first cross-sectional view showing the structure of a conventional memory cell having a groove-type capacitor electrode.

FIG. 5 is a second cross-sectional view showing the configuration of a memory cell having a conventional groove-type capacitor electrode.

[Explanation of symbols] 11 ... P-type silicon substrate, 12 ... Field oxide film, 13 ...
Grooves, 14, 18 ... N ⁺ -Type impurity layer, 16 ... Capacitor oxide film,
17 ... Polycrystalline silicon film, 20 ... Gate electrode, 21 ... Gate oxide film, 22 ... Interlayer insulating film, 23 ... Contact hole, 24 ... Aluminum wiring, 25 ... Silicon oxide film, 26 ... Resist film, 27 ... Silicon nitride film .

Claims (1)

[Claims] 1. A groove formed in a semiconductor substrate, a conductive layer formed on a surface of an inner wall of the groove to serve as one capacitor electrode, and a capacitor insulating film formed on an inner wall of the groove in which the conductive layer exists. A transistor for data transfer, which is on the substrate adjacent to the upper edge of the groove and has a gate electrode on the conductive layer, and another capacitor electrode which is insulated from the substrate by the capacitor insulating film and is embedded in the groove. A conductive film; and a film having oxidation resistance that covers the inner wall near the upper edge of the groove exposed from the conductive film and prevents the conductive film from directly contacting the capacitor insulating film near the upper edge of the groove. A semiconductor memory device characterized by the above.