JPH06195454A - Video image processor - Google Patents

Abstract

PURPOSE:To provide a system to cope with problems such as the control of the input/output of a video signal and the realizing method for the start of an image processing synchronized with the video signal to be the problems when a video image is processed by a parallel processing processor of one- dimensional array system. CONSTITUTION:A parallel processor 1 is connected by plural processors 2 in a one-dimensional state and each processor is composed of a memory 21, a processing element 22, a serial data input register 23 and a serial data output register 24. The serial data input register 23 and the serial data output register 24 are connected with the video signal input circuit 3 and the video signal output circuit 24 at the outside of the parallel processor 1. A controller 5 is composed of a parallel program memory 51, an interruption control circuit 52 and a sequencer 53, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a video image processing device.

[0002]

2. Description of the Related Art When performing the same processing on a large number of data,
It is possible to speed up the processing by SIMD type processing in which data is distributed to a plurality of processors and the same instruction is simultaneously executed. One-dimensional S in which a large number of processors are connected one-dimensionally to one of such SIMD computers
There is an IMD type computer. For example, in video image processing, the speed of image processing can be increased by using a computer having processors for the number of pixels in one line of an image. In such a video image processing device,
After the image for one frame is stored in the memory unit, the image processing for the entire image is started in synchronization with the vertical synchronizing signal.

[0003]

In the conventional video image processing apparatus, an image for one frame is stored after storing an image for one frame, and the image processing for the entire image is started in synchronization with the vertical synchronizing signal. It was necessary to input the image of the next frame to another memory area while performing the processing. Therefore, there is a delay of one frame time from the input of the image data to the output of the processing result. Further, the image input is performed separately from the calculation in the processor, and the image input cannot be configured as a calculation instruction.

[0004]

In order to solve the above-mentioned problems, a parallel processing apparatus according to the present invention executes means for sequentially inputting video signals to a processor, means for outputting video signals from the processor, and execution by the processor. Means for storing a program, a means for detecting a vertical synchronizing signal and a horizontal synchronizing signal of a video signal, and generating an interrupt signal, and an instruction to be executed next according to the stored program and the interrupt signal. It has a means for determining and a means for broadcasting the determined instruction sequence to the processor.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video image processing apparatus according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a video image processing apparatus according to the present invention.

In FIG. 1, reference numeral 1 is a parallel processor in which a plurality of processors 2 are connected one-dimensionally. Each processor is a memory 21, processing emerent 2
2, a serial data input register 23 and a serial data output register 24.

The serial data input register 23 and the serial data output register 24 are constituted by a shift register or a serial access memory in a video RAM, and data for one row of a video image is clocked independently of the operation of the parallel processor 1. You can input and output sequentially with.

The serial data input register 23 and the serial data output register 24 are connected to the video signal input circuit 3 and the video signal output circuit 4 outside the parallel processor 1. The video signal input circuit 3 includes, for example, a video camera and an A / D circuit, and the parallel processor 1
To send the data to be processed by the parallel processor 1. The video signal output circuit 4 is composed of, for example, a D / A circuit and a monitor, and displays the data processed by the parallel processor 1.

Reference numeral 5 is a controller having a function of supplying instructions to the parallel processor 1. The controller 5 is composed of a program memory 51, an interrupt control circuit 52, a sequencer 53 and the like. The program memory 51 stores an instruction string to be processed by the parallel processor 1. The interrupt control circuit 52 is provided with the vertical synchronizing signal 31 given from the video signal input circuit 3 and the video signal output circuit 4,
41, an interrupt signal 54 corresponding to the horizontal synchronizing signals 32, 42 is generated and given to the sequencer 53. Sequencer 5
3 determines an instruction to be executed next in the parallel processor 1 according to the program held in the program memory 51 and the interrupt signal 54 given from the interrupt control circuit 52, and broadcasts the instruction to the parallel processor 1 through the instruction supply bus 55. .

The video input circuit 3 sends input image data to the parallel processor 1, and the data is input to the serial data input register 23. When the image data for one row is input, the video input circuit 3 detects that the horizontal synchronization signal 3
2 is output. The horizontal synchronizing signal 32 is the interrupt control circuit 5
Entered in 2. The interrupt control circuit 52 issues an interrupt corresponding to the horizontal synchronizing signal 32 to the sequencer 53, and as a result, the interrupt program is executed by the sequencer 53.

In the instruction set of the parallel processor 1, a data transfer instruction between the serial data input register 23, the serial data output register 24 and the memory 21, the serial data input register 23, the serial data output register 24 and the processing element 22. And a data transfer instruction between the memory 21 and the processing element 22, and the interrupt program activated by the horizontal synchronizing signal 32 of the video input / output circuit 3 is stored in the serial data input register 23. It is composed of a command for transferring the image data of one line to the memory 21 or the processing element 22, a command string for performing image processing for the one line, and the like.

Further, the video output circuit 4 generates a horizontal synchronizing signal 42 when the display of the image data for one row stored in the serial data output register 24 is completed,
The interrupt control circuit 52 which received it interrupts the sequencer. The program executed as a result is composed of an instruction for transferring the data of the line to be displayed next from the memory 21 to the serial data output register 24.

The interrupt program requested by the interrupt control circuit 52 in response to the vertical synchronizing signals 31 and 41 is, for example, in resetting the pointer to the memory 21 for inserting a new image, or in processing for each row by the horizontal synchronizing signals 32 and 42. Instead, it is used to start an interrupt program that executes processing for the entire image. By starting different interrupt programs according to the sync signal for the even field and the sync signal for the odd field, the storage location and the processing content can be changed between the even field and the odd field.

FIG. 2 is a diagram showing the configuration of the interrupt control circuit 52. The interrupt control circuit 52 includes an arbitration circuit 10, an interrupt request signal generation circuit 11, and an interrupt vector register 12.

FIG. 2 is a diagram showing a case where the vertical sync signal of the even field and the vertical sync signal of the odd field are separately input to the interrupt control circuit 52. The arbitration circuit 10 is supplied with six types of synchronizing signals as vertical synchronizing signals 31a and 41a for even fields, vertical synchronizing signals 31b and 41b for odd fields, and horizontal synchronizing signals 32 and 42.

The arbitration circuit 10 is a circuit for deciding which synchronization signal an interrupt request is to be made when a plurality of synchronization signals are simultaneously input, and uses, for example, a priority encoder or the like. After deciding which synchronization signal the interrupt request is to be made to, the arbitration circuit 10 sends a signal to the interrupt request signal generation circuit 11 and also informs the interrupt vector register 12 of the type of the selected synchronization signal.

The interrupt request signal generation circuit generates an interrupt request signal 54a for the sequencer 53. The interrupt vector register 12 is the arbitration circuit 1
The interrupt vector 54b corresponding to the synchronization signal selected by 0 is sent to the sequencer 53.

[0019]

As described above, the video image processing apparatus according to the present invention can start a program for data transfer and image processing by a vertical synchronizing signal and a horizontal synchronizing signal of a video signal. The configuration of the data transfer circuit is simplified, the data transfer can be executed in the program, and the image processing can be easily performed every time one line of the image is input or output.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video image processing apparatus which is an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an interrupt control circuit.

[Explanation of symbols]

 1 parallel processor 2 processor 21 memory 22 processing element 23 serial data input register 24 serial data output register 3 video signal input circuit 4 video signal output circuit 5 controller 51 program memory 52 interrupt control circuit 53 sequencer 31, 41 vertical sync signal 32, 42 Horizontal sync signal 54 Interrupt signal 55 Instruction supply bus 10 Arbitration circuit 11 Interrupt request signal generation circuit 12 Interrupt vector register 31a, 41a Even field vertical sync signal 31b, 41b Odd field vertical sync signal 54a Interrupt request signal 54a, 54b Interrupt vector

Claims (1)

[Claims] 1. A plurality of processors are connected in a one-dimensional form,
SIMD type video image processing for executing the same instruction in all processors, means for sequentially inputting a video signal to the processor, means for sequentially outputting a video signal from the processor, and means for storing a program to be executed by the processor A means for detecting a vertical synchronizing signal and a horizontal synchronizing signal of a video signal to generate an interrupt signal; a means for determining an instruction to be executed next according to a stored program and the interrupt signal; And a means for broadcasting the generated instruction example to the processor.