JPH06195409A - Logical circuit connection rule verification method - Google Patents

Abstract

PURPOSE:To attain a high speed processing by avoiding duplicated verification by obtaining information necessary for the verification of the connection rule of a hierarchical block on the high-order side of a hierarchical block and storing it at the time of verifying the connection rule of the hierarchical block. CONSTITUTION:This method executes the step of verifying the connection rule with regard to a net closing inside of the hierarchical block successively from the hierarchical block on a lower side toward that on a higher side and the step of obtaining information necessary for the verification of the connection rule of the hierarchical block on the high-order side with regard to a net connected to the hierarchical block on the high-order side of the hierarchical block and storing it. Namely, this logical circuit connection rule verification method verifies the connection rule successively from the hierarchical block on the low-order side toward that on the high-order side and at the time of verifying the connection rule of a hierarchical block, the method obtains information necessary for the verification of the connection rule of the hierarchical block on the high-order side of the hierarchical block and stores it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit connection rule verification method for verifying a connection rule of a logic circuit in a logic circuit design using a CAD device, and more specifically, verification of a hierarchically designed logic circuit. And a logic circuit connection rule verification method for performing

[0002]

2. Description of the Related Art When designing an LSI logic circuit using a CAD device, for example, a plurality of hierarchical blocks CH shown in FIG.
Consider a hierarchical structure consisting of IP, BLK1, BLK2, BLK3, BLK4. Each hierarchical block is composed of a logic element portion and a logic element portion composed of a net connecting the logic elements, and a lower hierarchical block whose structure is indicated by a black box when a lower hierarchical block exists. In the hierarchical structure shown in this example, the hierarchical block B
LK2 is arranged in two places. When designing a logic circuit, circuit design is performed for each hierarchical block either sequentially or in a shared manner.

Once this logic circuit design is completed, it is verified whether or not the fan-in and fan-out are suitable, and whether or not other logic elements whose connection is prohibited are connected to a predetermined connection rule. Be done. In the verification of this connection rule, conventionally, a hierarchical structure is developed, and the connection information composed of the expanded logic element and its connection net is verified, or when the verification is performed without expanding the hierarchical connection information, Verification is performed by checking the connection between hierarchical blocks from the upper layer to the lower layer.

The conventional connection rule verification method will be described below.
Verification of fan-in and fan-out will be described as an example.
FIG. 3 is a flow showing an example of a conventional connection rule verification method performed by expanding a hierarchy. A logic circuit is designed and input for each hierarchical block using the logic circuit input means, and information for each hierarchical level regarding the input logic circuit is stored.

In the verification of the logic circuit connection rule, first, the stored logic circuit information for each hierarchical block is referred to expand all the layers, and the lower hierarchical blocks are all made up of logic elements and their connection nets. The expressed expanded logic circuit information is created. Next, the output drive capability is verified for all the nets of the expanded logic circuit by referring to the created expanded logic circuit information and the cell library, and the verification result is created.

FIG. 4 is a flow chart showing an example of a conventional method of verifying a connection rule with hierarchical connection information as it is. First, a logic circuit is designed and input for each hierarchy using the logic circuit input means, and the logic circuit information for each hierarchy created by this is stored. In verifying the logic circuit connection rule, it is determined whether or not the net is a closed net in the hierarchical block sequentially from the highest hierarchical block CHIP and sequentially for all nets in the hierarchical block. For all the pins (input terminal or output terminal) connected to, it is judged whether all the pins are the pins of the logic element in the hierarchical block or the pins of the logic element in the lower hierarchical block are included. If the net is connected to the lower hierarchical block, it goes down to the lower layer and the circuit configuration in the lower hierarchical block is checked to find the pin to connect to the net. . In this way, when the connection pin of the net is obtained, the cell library is referred to, the suitability of the output drive capability is verified, and the verification result is created. By repeating the above for all the nets of the hierarchical block and further for all the hierarchical blocks, the connection rule of the entire logic circuit is verified.

[0007]

However, if the method of expanding all the layers as shown in FIG. 3 and verifying the connection rule is adopted, for example, the layer block BL shown in FIG. 2 is used.
When there are a plurality of hierarchical blocks arranged in the entire logic circuit like K2, the verification is repeated by the number of arranged hierarchical blocks, and there is a problem that the processing takes time.

In the method for verifying the connection rule with the hierarchical connection information as shown in FIG. 4, the verification of the duplicate connection rule is avoided for the same whole hierarchical block as described above, but it is described above. As described above, when verifying the connection rule of a hierarchical block, the net in the hierarchical block is not limited to connecting the logic elements of the hierarchical block, but may be inside the lower hierarchical block. In that case, the connection rule of the hierarchical block is verified only when the internal circuit configuration of the lower hierarchical block is entered. Therefore, for example, in the case of the hierarchical structure shown in FIG. 2, it is necessary to enter the inside of the hierarchical block BLK2 when verifying the connection rule of the hierarchical block BLK1 and again when verifying the connection rule of the hierarchical block BLK3. There is a problem that it is necessary to enter the inside of the block BLK2, and therefore it is necessary to overlap the inside of the same hierarchical block in duplicate, and it takes time to process.

In view of the above circumstances, the present invention proposes a logic circuit connection rule verification method capable of avoiding duplicate verification even when there is a hierarchical block commonly used a plurality of times and thereby performing high-speed processing. The purpose is to

[0010]

According to the logic circuit connection rule verification method of the present invention which achieves the above object, a logic element section consisting of logic elements and a net connecting logic elements and a lower hierarchical block are present. In the logic circuit connection rule verification method for verifying the connection rule of the logic circuit formed by combining a plurality of hierarchical blocks configured with a lower hierarchical block whose configuration is indicated by a black box to form a hierarchical structure, A step of sequentially verifying connection rules for nets closed in the hierarchical block from the lower hierarchical block to the upper hierarchical block, and a net connected to an upper hierarchical block of the hierarchical block. And storing the information necessary for verifying the connection rule of the upper hierarchical block with respect to It is intended to.

[0011]

The logical circuit connection rule verification method of the present invention sequentially verifies the connection rule from the lower hierarchical block to the upper hierarchical block, and verifies the connection rule of a certain hierarchical block. Since the information necessary for verifying the connection rule of the upper hierarchical block of the hierarchical block is obtained and stored at the time of execution, when the connection rule of a certain hierarchical block is verified, the lower hierarchy of the hierarchical block Even if the block exists, it is only necessary to refer to the stored information, and it is not necessary to go inside the lower hierarchical block to check its connection, and therefore, the hierarchical block commonly used multiple times can be When it exists, duplicate verification is avoided and high-speed connection rule verification processing is realized.

[0012]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a flowchart showing an embodiment of the logic circuit connection rule verification method of the present invention. First, a logic circuit is designed and input for each hierarchy using the logic circuit input means, and the logic circuit information for each hierarchy created by this is stored. In verifying the logic circuit connection rule, the following processing is executed for all hierarchical blocks in order from the lower layer to the upper layer. Nets are sequentially picked up one by one with respect to the hierarchical block for which the connection rule is to be made, and it is determined whether the taken net is a net closed in the hierarchical block or a net extending over other hierarchical nets. It If the net is a net closed within the hierarchical block or a net extending only to the lower hierarchical block included in the hierarchical block, the output drive capability verification means connects the logic circuit information and the lower hierarchical block. By referring to the rule information (described later) and the cell library, the fan-in and fan-out of the pin connected by the net is checked, and it is verified whether the output drive capacity of the net satisfies the regulation, and the verification is performed. Results are created. If the net to be verified is not a closed net in the hierarchical block but a net extending over the upper hierarchical net, the connection rule information, that is, the pin of the hierarchical block connected to the net. Depending on whether is an input pin or an output pin, the input load on that pin,
The output drive capability is checked, and the information is stored in the table as shown in Table 1 by the connection rule storage means.

[0013]

[Table 1]

Table 1 shows the hierarchical block BLK1 shown in FIG.
By performing the above-mentioned processing for all nets of a certain hierarchical block, a table as illustrated in Table 1 is created for that hierarchical block. This table shows that hierarchical block (in the case of Table 1, hierarchical block B
It is used when verifying the output drive capability of the upper hierarchical block of LK1) (the hierarchical block CHIP in the case of Table 1).

By performing the above-mentioned processing for all hierarchical blocks from the lower hierarchy to the upper hierarchy, and for all nets of each hierarchical block, the connection rule of the entire logic circuit is verified. At this time, for example, when there is a hierarchical block that appears a plurality of times in one hierarchical structure, such as the hierarchical block BLK2 shown in FIG. 2, connection rule verification is repeated for the hierarchical block that appears a plurality of times. That is, it is omitted that the internal circuit configuration of the input / output end of the lower hierarchical block is duplicated for a plurality of times, so that the connection rule is efficiently verified. Be done.

Normally, the verification of the connection rule is executed a plurality of times at the design stage of the logic circuit, but a table such as Table 1 is prepared for each hierarchical block and changed at the design stage. By constructing the table again only for the hierarchical block, the verification of the connection rule becomes more efficient.

[0017]

As described above, the logic circuit connection rule verification method of the present invention sequentially verifies the connection rules from the lower hierarchical block to the upper hierarchical block. When the connection rule of a hierarchical block is verified, the information necessary for verifying the connection rule of the upper hierarchical block of the hierarchical block is obtained and stored, so that there is a hierarchical block commonly used multiple times. Therefore, duplicate verification is avoided and high-speed connection rule verification processing is realized.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a logic circuit connection rule verification method of the present invention.

FIG. 2 is a diagram showing an example of a hierarchical structure of a logic circuit.

FIG. 3 is a flow showing an example of a conventional connection rule verification method performed by expanding a hierarchy.

FIG. 4 is a flowchart showing a conventional example of a method for verifying a connection rule with hierarchical connection information as it is.

Claims (1)

[Claims] 1. A hierarchical block composed of a logical element portion comprising a logic element and a net connecting the logical elements and a lower hierarchical block whose structure is indicated by a black box when a lower hierarchical block exists. In a logic circuit connection rule verification method for verifying a connection rule of a logic circuit formed by combining a plurality of layers to form a hierarchical structure, the hierarchical blocks are sequentially arranged from the lower hierarchical block to the upper hierarchical block. A step of verifying a connection rule for a closed net in the network, and obtaining and storing information necessary for verifying a connection rule of the upper hierarchical block for a net connected to a higher hierarchical block of the hierarchical block. A method for verifying a logic circuit connection rule, comprising: