JPH06195402A - Optimal design supporting system for product development - Google Patents

Abstract

PURPOSE:To drastically reduce development manhour by executing optimization by simultaneously evaluating the improvement of the performance of a product, a low cost, the improvement of a quality and a product developing period. CONSTITUTION:Evaluation information based on information concerning the object product of CAD/CAM/CAT processors is generated by a design evaluation information generation part interface 31 and generated evaluation information is inputted to a life cycle cost simulator 50. The simulator 50 executes simulation by associating the quality of the product and the cost. A user interface 60 inputs a parameter, etc., by interactive input to the simulation. Besides, the user interface 60 refers to and changes the knowledge base of a rule base expert system 90 consisting of an object directivity data base. A design rule check 75 executes rule-check based on the expert system 90, design information 80 of the object product and evaluation information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer aided design system (Computer Aided) for improving the design efficiency of a circuit board.
The present invention relates to a product development optimum design support system that enables early commercialization, quality improvement, and cost reduction of a circuit board based on design information created using a design system (hereinafter referred to as a CAD system).

[0002]

2. Description of the Related Art The first conventional method for evaluating whether or not a circuit board has a structure that is easy to manufacture is referred to as a design review at the time of design, and a person skilled in designing and manufacturing can easily make a circuit board based on experience. There is known a general method for determining the need for improvement and pointing out the portion requiring improvement.

As a second conventional method, as shown in FIG. 2 which shows a flow of evaluation of design and manufacturability and design improvement, a process plan is made based on the design drawing and an estimated assembly cost is calculated. Then, there is a method of judging whether the structure is good or bad by taking this value and the experience of a skilled person such as designing and manufacturing into consideration.

A third conventional method is Japanese Patent Laid-Open No.
As described in Japanese Patent Publication No. 1-59900, there is a printed board package assembly evaluation method for automatically evaluating the assembly automation rate of a printed board package. In this method, in order to evaluate the easiness of automation when inserting the components in the assembly of the printed board package, the standard attachment time of the standard insertion semiconductor integrated circuit by hand is set to 100, and the components to be evaluated are inserted. Express the difficulty level with a deduction score,
From this, the accumulated deduction points of the parts inserted manually are calculated, and the fully deducted value is deducted from 100 when the fully automatic case is set to 100, and the score of this value is used as the index of assembly automation.

[0005]

The first conventional method described above is qualitative, and the objective is to determine how good or bad the structure of the evaluation target product is and how effective it is when it is improved. There is a problem that it is difficult to express quantitatively and quantitatively, and only those who have sufficient experience in design and production technology can implement it.

In the second conventional method, even if the assembly cost of the entire board, each part, or part of the part can be estimated, whether the design structure is good or bad and whether improvement is necessary only from the value can be estimated. It is difficult to judge whether or not it is difficult to evaluate, and it requires experience and knowledge and considerable calculation time to evaluate it, and it is difficult to evaluate unless the design is completed. Even if it happens, once the design is completed, it takes a lot of time to change the design.
As shown in FIG. 2, there has been a problem in that the production is often transferred without making a design change, so that productivity improvement and cost reduction cannot often be realized.

In the third conventional method, evaluation can be performed without much experience, but the evaluation index is a method in which only the ease of automation of assembly when inserting a component into a circuit board is expressed by a score. That is, assembling a normal circuit board includes mounting the circuit board, inserting the insertion component, reversing the substrate, mounting the chip component,
Since the circuit board is manufactured through various processes such as drying, board reversal, insertion of odd-shaped components, manual insertion, soldering, cleaning, retrofitting, inspection, etc., the man-hour ratio for component insertion is The ratio is about 10 to 30%, and there is a problem that the quality of the ease of assembly cannot be accurately and comprehensively determined only by automating the insertion of the components.

In sum of the above problems, (1) the evaluation is qualitative, not quantitative.

(2) Only an experienced person can evaluate, or some knowledge of the evaluation method is required.

(3) If only the cost is evaluated, the performance and quality cannot be comprehensively evaluated.

(4) Evaluation takes a lot of time and labor.

(5) The evaluation cannot be performed unless the design is completed or approaches the end, and it is difficult to improve the design after the determination.

(6) It is difficult to improve the product because the quality of the design of each part is not easy to understand.

(7) The evaluation index is not associated with the cost.

That is,

Therefore, the technical problem to be solved by the present invention is to solve the problems of the above-mentioned technique, and the purpose thereof is (1) quantitative evaluation,
(2) No experience is required, and (3) not only cost evaluation, but also mutual evaluation items such as performance improvement, quality improvement, and short-term product development can be evaluated in a unified manner, and (4) evaluation is easy and (5) Evaluation can be done at an early stage of design and development.

(6) It can be evaluated at the component level.

(7) It has performance, quality, and delivery evaluation indexes, and these indexes are associated with costs.

(8) CAD / CAM (Computer under design)
Aided Manufacturing) / CAT (Computer Aided Tes)
Evaluation can be done directly from the information.

(9) Integral cost optimization design evaluation can be performed immediately during design.

The evaluation method as described above is to provide an integrated cost optimization design system that can be automatically performed.

[0022]

In order to achieve the above object, according to the present invention, the target product of the target product of the computer aided support system for improving the design efficiency of the product is identified based on the information of the target product. , Wiring difficulty, product size, manufacturability, delivery date data, error durability data, reliability and maintainability data, and other information about product quality, and cost data. The target product is manufactured based on the design evaluation information generation unit that generates the evaluation information, the evaluation information database that stores the information generated by the evaluation information generation unit, and the information stored in the evaluation information database. Cost and the product quality of the target product, an evaluation index is generated using the same evaluation scale, and the life cycle cost is calculated based on the evaluation index. A life cycle cost simulator for simulating the above and design information of a similar product similar to the target product into the minimum knowledge units that compose the product, and define the design procedure by combining the minimum knowledge units. A rule-based expert system, a dialogue unit for referring to a knowledge unit of the rule-based expert system and exchanging information for generating a design procedure of the target product, and a knowledge unit of the rule-based expert system. Of the target product and design rule check means for automatically evaluating the design procedure of the target product.

Each of the above will be explained individually. First, the same evaluation criteria are used for simultaneously evaluating and optimizing contradictory evaluation items of different performances such as performance improvement, low cost, quality improvement and short-term product development. Provided.

In addition, since evaluation is performed without requiring experience or knowledge about similar products, the product information can be evaluated from IF to TH.
An expert system with similar product information and knowledge base that was EN-based was provided.

Further, in order to estimate not only the assembly cost but also the life cycle cost of design, manufacturing, test, operation / maintenance and reuse / reuse / disposal, a life cycle cost simulator is provided and evaluation items are provided. This is a comprehensive evaluation of the degree of achievement of with the cost as the key.

Furthermore, in order to be able to carry out design evaluation at an early stage of design development, the product characteristic feasibility from design / manufacturing / inspection / operation / reuse / reuse / disposal and the hierarchical structure that constitutes it are hierarchized. A product quality factor analysis means is provided to optimize the built-in quality and these characteristic values in a multi-layered structure.

Furthermore, since the product quality evaluation indexes are provided and these indexes are associated with the costs, the relationship between the characteristic feasibility and the costs is expressed by the same evaluation standard.
We provided a life cycle cost simulator consisting of a wiring difficulty simulator, error durability simulator, manufacturing ease simulator, delivery time simulator, reliability + maintainability simulator, downsizing simulator, and testability simulator.

A standard format interface capable of generating design evaluation information from a CAD / CAM / CAT processor is provided so that evaluation can be performed immediately during design.

Regarding product development, a development investment efficiency prediction means for dividing the net profit expected to be obtained by research and development by the life cycle cost is provided in order to make a decision on development at the concept stage. .

As a result of the above, in order to support the product quality optimization design in product development, a system has been established in which both the company manager and the person in charge of design can clarify the goal with the information of quality improvement, which is a common goal.

[0031]

[Function] A method for simultaneously evaluating and optimizing contradictory evaluation items such as performance improvement, low cost, quality improvement, and short-term product development is the SN of the product feasibility of the entire product and the built-in quality that constitutes it. (Signal Noise) The same evaluation standard called the ratio is set and integrated design evaluation is performed. Regarding the SN ratio, for example, "Fundamental Use of Optical Fiber" (Ohmsha, Toshio Nemoto, Magazine "Electronics", Showa 5)
January 6 issue appendix) p. 138 to p. 139.

The design / evaluation information generation unit allows CAD / CA
The output signal of the M / CAT processor is at least one of cost data, wiring difficulty, product size, manufacturability, delivery date data, error durability data, and reliability + maintainability data.
CAD / CAM / CAT processing information can be directly input to the life cycle cost simulator by converting into one information.

As a result, design, manufacturing, test, operation,
Since it is possible to generate evaluation information for reuse / reuse and disposal, it is possible to perform integrated design evaluation of product development.

The life cycle cost simulator has product quality evaluation indexes based on the evaluation information database generated by the design evaluation information generating section, and these indexes are associated with costs. By expressing the relationship with the same evaluation criteria, it is possible to use information that is one or more of wiring difficulty, error durability, manufacturability, delivery time, reliability + maintainability, downsizing, and testability. Perform a simulation.

The rule-based expert system analyzes the design work based on the design information of the similar product according to the IF-THEN rules, classifies the product data and the minimum knowledge (work) unit constituting the product data, and uses this knowledge. (work)
A similar product is searched by constructing an object-oriented database according to a design procedure in which units are combined to make one meaning and defining attributes.

A rule-based expert system is efficiently created by an interactive means, and a knowledge editing function for referring / changing the knowledge base of the expert system is provided, thereby eliminating the need for execution procedure work by ordinary procedural program coating. .

By the design rule checking means, a rule-based expert system, design information and CAD
A rule check is performed using a design rule execution module that connects / CAM / CAT processing information.

Further, by means of the product quality factor analysis means, the feasibility of manufacturing from design / manufacturing / inspection / operation / reuse / reuse / disposal, the built-in quality that constitutes it, and these characteristic values are used. By optimizing the multi-layered structure, the design evaluation can be performed at an early stage of product development.

Further, the development investment efficiency predicting means obtains the development investment efficiency by dividing the net profit expected to be obtained by the research and development by the life cycle cost, and makes a decision on the development at the concept stage regarding the product development. To do.

[0040]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing an outline of the configuration of a product development optimum design support system to which the present invention is applied. The product development optimum design support system 30 shown in FIG.
From a database created by an AM / CAT processing device or stored in a CAD / CAM / CAT database (not shown), for example, EDIF (Electronic Disign
Interchange Format) and the like, the cost data 32 extracted by the design evaluation information generation interface unit 31, the wiring difficulty 33, the product size 34, the manufacturability 35, the testability 36, the delivery date data 37, the error tolerance. Based on the evaluation information database 40 based on the data 38 and the reliability + maintainability data 39, the rifle cycle cost simulator 50 automatically simulates the relationship between each design evaluation information and the cost. The result of the life cycle cost simulation is a user interface 60 having a knowledge editing function for referring and changing the knowledge bases of the designer and the expert system.
Is passed to a rule-based expert system (design knowledge base having both data and procedures) 90 for storing design knowledge. Based on the design rule check 75, the rule-based expert system 90 checks the product target specifications 81, standard part information 82, characteristic parameters 83,
It is combined with design information 80 including component placement information 84, error durability information 85, reliability + maintainability information 86, and the like.

The contents of the rule-based expert system (design knowledge base) 90 are based on the design information of similar products.
It is as shown in FIG. Here, when design work is analyzed and sub-circuits and sub-parts are divided into functional units as knowledge, some minimum knowledge (work) units are classified into so-called objects, that is, units having both data and procedures. You can

The knowledge (work) units are combined to represent one meaningful design work. This is referred to as a design procedure 72, and this design procedure is hierarchized by an object-oriented database and called by an attribute definition to represent a series of design work. With this object-oriented database, knowledge (work) can be made into sub-circuits and sub-components (modularization) in functional units, and design information can be easily searched.

In FIG. 3, as an example of the rule-based expert system (design knowledge base) 90,
The NC data calculation result 73 for the mounting machine, such as how the parts are attached to the product data 71, is shown.

When components are mounted with a mounting machine, if they are arranged at a high mounting density, as shown in FIG. 4 (a), the mounting machine head and the vertical component 1 that has already been mounted interfere with each other to mount the mounting machine. In some cases, the vertical component 2 cannot be mounted. Similarly, FIG. 4B shows that, when the lead is clinched by the anvil, the chip component 1 already mounted and the anvil interfere with each other. Here, the anvil is a clinching mechanism of a mounting machine for clinching a lead of a component.

Such a rule check of the interference of the mounted state is performed in the rule-based expert system (design knowledge base) 90 shown in FIG. 3 based on the component placement information and the mounting machine name. As part duplication check,
The clinch shape of the lead can be defined separately from the part shape definition. As a mounting rule check, the anvil shape can be checked separately from the head shape of the mounting machine. As described above, the design rule check 75 includes the rule-based expert system 90, the design information 80, and the CAD / CAM / CAT processor 20.
It is a design execution module that connects with and can automatically check rules based on various product target specifications 81.

Here, characteristic realizability (evaluation index) is assumed as a scale for realizing the characteristic, and this is taken as θ.
_i, and 0 < θi < 1 is satisfied as a constraint condition. Further, a linear model λ _i = α + β χ _i , _i = 1,2 ...
· Assume.

Here, α and β are parameters of the intercept and the slope, respectively.

It is assumed that θ is a logistic function (Equation 1) and is given by the following equation. What is given by the following equation is "analysis of binary data" (Asakura Shoten, D.M.
R. Cook, Shoji Goto et al.) P. 24 to p. 25
It is described in.

[0050]

[Equation 1]

Assuming β> 0 with θ _i given by (Equation 1) as a function of χ, the result is as shown in FIG. 5 (a).

Here, assuming the following expression for converting the property feasibility θ _i ,

[0053]

[Equation 2]

Differentiating (Equation 2),

[0055]

[Equation 3]

When (Equation 3) is integrated from θ ₁ to θ ₂ ,

[0057]

[Equation 4]

Here, assuming that the SN ratio is η from the expression in decibels,

[0059]

[Equation 5]

For example, letting θ _i in (Equation 5) be the reliability,
Since 1−θ _i is the unreliability, (Equation 5) conceptually represents the ratio of the reliability and the unreliability.

Here, consider the characteristic feasibility θ of an automatic payment machine as an example. At this time, as θ, for example, it is assumed that the reliability (the rate at which money is correctly inserted when the card is inserted) is 0.994 in the market. The effect of adding the following three functions for increasing the reliability will be examined by the above method.

A: The part A is changed to a new part.

B: The circuit is renewed.

C: A dustproof device is attached.

In order to confirm the effect on the three functions, the tests were conducted separately, and the data shown in Table 1 was obtained as a result of the forced test (100 times test while applying vibration and dust). To do.

[0066]

[Table 1]

Table 2 shows the effect of the functions A, B and C expressed in decibels according to (Equation 5).

[0068]

[Table 2]

Therefore, the effect (gain) when all three functions are adopted is 21.30 dB when the functions A, B, and C are independent events.

The market reliability of 0.994 is 22.19 as follows.
Since it is dB, the effect of adopting all three functions is

[0071]

[Equation 6]

As a result, θ = 0.99955 is obtained.
That is, the characteristic feasibility θ is from 99.4% to 99.95.
Improves to 5%.

FIG. 5 (b) shows the result of expressing FIG. 5 (a) in decibel units using (Equation 5). That is, it can be seen that the characteristic feasibility θ and the SN ratio η are in a relationship capable of mutually inverse conversion. Therefore, the product development can be comprehensively evaluated by superimposing various evaluation items on η from the function of θ (Equation 1). Here, the SN ratio is also
Assuming that the magnitude of variation is σ and the average value is M, η is expressed by the following equation.

[0074]

[Equation 7]

In (Equation 2), with λ as a characteristic value and χ as a signal factor, a difference α at a reference point χ ₀ of a certain signal factor χ.
FIG. 6 shows the case where the adjustment is made so that the value becomes zero. Note that m
The level values of the signal factors for achieving the target values of ₁ , m ₂ , ..., m _h are χ ₁ , χ ₂ , ..., χ _h, and the characteristic values after zero adjustment are λ ₁ , λ ₂ , ..., λ. _{Let h} .

The relationship between the characteristic value λ and the signal factor χ at this time is given by the following equation.

[0077]

[Equation 8]

[0078] Now, by performing the calibration of the proportional constants chi _0, the value of lambda for β is chi ₀ as shown in FIG. 6 as lambda ₀

[0079]

[Equation 9]

The target value is m and the characteristic value λ is y. Here, when the loss cost function when deviating from the target value is C (λ), it becomes as shown in FIG. 7.

The loss cost is zero when the characteristic value λ is equal to the target value m, or the loss is minimum when the characteristic value λ is equal to m. That is, the following equation is generally established.

[0082]

[Equation 10]

[0083]

[Equation 11]

Taylor expansion of C (λ) around the target value m gives

[0085]

[Equation 12]

Here, (Equation 10) and (Equation 11) are replaced by (Equation 1)
Substituting into 2) and omitting terms above (λ-m) ³
The loss cost function C (λ) is approximated by the following equation.

[0087]

[Equation 13]

Here, k is a constant. In FIG. 7, first, Δ ₀ is obtained as a functional limit of how much the characteristic value λ deviates from m to cause a trouble.

A _{0 is on} the left side of (Equation 13), and (λ−
Substituting △ ₀ for m)

[0090]

[Equation 14]

Here, A ₀ is (the average of) the loss cost when a trouble occurs is A ₀ yen. From this, the proportional constant k is obtained by the following equation.

[0092]

[Equation 15]

Therefore, the loss cost function C is approximated by the following equation.

[0094]

[Equation 16]

Here, in the design, the characteristic value λ changes in the environment or deteriorates during use. If the average of the square of the difference between the environmental conditions at this time and the target value during the design life is taken as the variance and σ ² is taken, the operation loss cost Cu is calculated by the following formula.

[0096]

[Equation 17]

In FIG. 7, if the cost A of a similar product is
If ′ and the functional limit Δ ′ are known, the following equation must be established from (Equation 16).

[0098]

[Equation 18]

That is, by interactively inputting the characteristic value λ and the target value specification m in the user interface 60 of FIG.
The cost C can be automatically calculated from (Equation 16).

Similarly, in the production process as shown in FIG. 8, in order to obtain the quality level of the process, the characteristic values of the product produced by the process are set to λ ₁ , λ ₂ , ... The error, that is, the variance σ ² can be obtained by the following equation.

[0101]

[Formula 19]

Then, the manufacturing loss cost Cp can be calculated by the following equation.

[0103]

[Equation 20]

Here, Δ is the tolerance given at the production factory, and A is the loss cost of rework, reuse / reuse, or disposal when a rejected product is found at the factory.

To quantitatively evaluate the design quality, FIG.
As shown in Fig. 2, using a circuit board as an example, a built-in quality design scale that a developer builds in order to satisfy the design requirement scale and the design requirement scale based on user requirements and development specifications, and configures it. The characteristic values are further measured and evaluated in four layers of signal factors constituting the characteristic values.

As the design requirement scale, the first layer has wiring difficulty, error durability, manufacturability, quick delivery, low cost, reliability + maintainability (including sociality), downsizing, and testing. It is evaluated on eight scales of ease.

As the built-in quality design scale, the second layer is evaluated by a scale such as mounting density, electromagnetic noise characteristic, and transmission line characteristic, and further, characteristic values constituting these layers as the third layer and characteristics as the fourth layer. Factor analysis is performed using a hierarchical structure consisting of signal factors that make up values. These product quality factor analysis means 51 use quality measures structured in four layers, and FIG. 9 shows the structure of the quality factor analysis means 51.

Here, for example, design requirement scales of wiring difficulty, error durability, manufacturability, quick delivery, low cost, reliability + maintainability, downsizing, and testability are represented by θ _A , θ. _B , θ _C , θ _D , θ _E , θ _F , θ _G , and θ _H, and the SN ratio represented by (Equation 5) of the built-in quality design scale is η, and now each term of this SN ratio is supported. And each, ω
_The method of averaging with weights of ₁ , ω ₂ , ..., ω _n, that is, the weighted average of the design requirement measure is as follows when explained with the example shown in FIG.

Weighted average of design requirement scale = (ω ₁ η ₁ + ω
₂ η ₂ + ... + ω _n η _n ) / (ω ₁ + ω ₂ + ... + ω _n ). Therefore, the design quality design measure is represented by the weighted average of the SN ratios of the related built-in quality design measures.

Based on this, the characteristic feasibility θ from (Equation 5)
When converted to (0 < θ < 1), a radar chart can be created by plotting with a graphing means (not shown) as shown in FIG.

That is, as shown in FIG. 11, by visualizing eight design requirement scales, it is possible to compare the actual value with the target specification value and make a pass / fail judgment at the conceptual design stage of the product.

The mounting density, which is a built-in quality design measure of wiring difficulty, is obtained by determining the number of board layers depending on the size of the board area. Here, the wiring difficulty is a scale for wiring on the substrate.

The package size S of the QFP (Quard Flat Package) is obtained from the following equation from FIG.

[0114]

[Equation 21]

When this package is arranged at a distance n times the terminal pitch, the arrangement pitch P is

[0116]

[Equation 22]

D. Seraphim's formula (DPSeraphim: “Chip
-module-package interfaces ", (IEEE, Trans.CHMT, CHMT
-1, p.305 to p.309)), the total wiring length L is

[0118]

[Equation 23]

Here, L: total wiring length, the required wiring length La per unit area is

[0120]

[Equation 24]

If the wiring efficiency of the wiring board is e, this QF
The maximum wiring capacity Lmax required for a wiring board mounting P is

[0122]

[Equation 25]

In the case of a QFP-equipped wiring board with Pl = 0.635 mm and Nt = 200 pins, if La = 45 cm / cm ² , then e = 0.25 to 0.50
Therefore, Lmax = (45 / 0.5 to 45 / 0.25), that is, a wiring board having a wiring accommodating capacity of about (90 to 180) cm / cm ² .

In the case of a two-layer board, (90/2 to 180/2) cm / cm ² = (45 to 90) cm / cm ² → average 67.5
＝ 70cm / cm ² / layer Similarly, when lead pitch is 0.5mm and number of terminals is 400, La = 63.0c
When ^{m / cm 2, Lmax = 63} / 0.5~63 / 0.25 = 126~252cm / cm 2 1 layer per the wiring rule of ^{70cm / cm 2, 126 / 70~252} / 70 = 1.8~3.6 ≦ 2~ 4 layers Therefore, if the wiring capacity per layer is η and the number of layers is t,

[0125]

[Equation 26]

FIG. 12B shows the result of obtaining the relationship between the mounting density and the number of substrate layers based on (Equation 26).

Next, as shown in FIG. 13, the bare board manufacturing cost C _{B, B} is obtained by interactively inputting the plate thickness, the plate thickness number, the minimum pattern width, etc. of a standard size (for example, 1 m × 1 m) substrate. The bare board manufacturing cost C _{B, B} is calculated by the following equation.

[0128]

[Equation 27]

The number of substrate layers and the bare board manufacturing cost C _{B, B} when the bare board manufacturing cost is calculated by (Equation 27).
FIG. 14 shows the relationship with.

Further, as shown in FIG. 15, the bare board manufacturing cost for each of the number of channels, the normal diameter of the holes of the substrate, and the small diameter is required. Furthermore, the parts purchase cost C _Q , the cost, etc. stored in advance in the CAD product library (not shown) of FIG. 1 and the tact time and the cost of the group of parts of the grouping processing database 70 shown in FIG. 16 are assembled. The total cost of the circuit board is obtained by obtaining the estimated cost C _A and summing these with the bare board manufacturing cost C _{B, B.} Here, the allocation means a manufacturing cost per unit time.

Further, the number of board layers (obtained from the number of signal layers by (Equation 26)) is obtained from the wirable area and the wiring difficult area of the circuit board shown in FIG. 12, and the information shown in FIG. 15 is also obtained. In addition, the optimal number of substrate layers that satisfies the target cost can be obtained.

Based on the above results, the relationship between the wiring difficulty (generally proportional to 1 / the number of substrate layers) and the cost is shown in FIG.

In the circuit design stage, the components used in the circuit diagram are usually certified components whose reliability has been confirmed. Therefore, the certified component is, for example, a QF as shown in FIG.
In P, the component projected area including the size of the board-side pad (see FIG. 13C) to be mounted is fixed.

Therefore, when the circuit components to be used are determined, as shown in FIGS. 13B and 13C, the size of the wirable substrate, the total number of pins of the component, the lattice spacing, and the number of inter-lattice channels are calculated from CAD. Is automatically generated, and the number of layers and the number of channels that can be wired are estimated from (Equation 26). Furthermore, from (Equation 27), the wiring board thickness, the number of boards to be cut,
Assuming the minimum pattern width and the number of holes, the bare board manufacturing cost is estimated.

In this way, by estimating the mounting form and the total cost of the circuit board at the circuit design stage,
It is possible to estimate the quality of mounting of the circuit board in consideration of the cost.

At the circuit design stage, the circuit diagram is shown in FIG.
Circuit division (circuit cutout) into sub-circuits as shown in (a)
Then, each block is divided and evaluated, and the results are tabulated and displayed in a spreadsheet 260 as shown in FIG. 36 (b) to obtain the wiring difficulty (Lmax, η, etc.) of each part. Value), manufacturability (Equation 28), total cost of each part, board area, etc. can be compared. This makes it easy for the user to allocate the circuits evenly and to implement a balanced circuit as a whole. Furthermore, by cutting out a sub-circuit of an arbitrary functional block in one circuit diagram and assuming the board area, etc., if the board area cannot be mounted in the assumed area, the circuit is converted to ASIC (Ap
It is also possible to support studies such as replication specific IC conversion). Generally, when the circuit board moves to the packaging design, the development period is delayed when the circuit design is revisited and the design is changed. However, according to the present invention, the design evaluation can be performed for each block circuit at the circuit design stage, so that there is an effect that the development period can be shortened.

Next, the relationship between the error durability and the cost C _N is expressed as shown in FIG. 18 in the same relationship as that of FIG. 7 described above. Here, the error durability is the resistance to errors such as electromagnetic noise characteristics and transmission line characteristics that are not known until a so-called product is manufactured. For example, these error tolerances can be analyzed in advance by an analog simulator such as SPICE.

The manufacturability will be described below with reference to the user interface 60 (line mounting order) shown in FIG. Here, manufacturability is a measure of product easiness of manufacture θc
FIG. 19 shows the relationship between the manufacturability θc and the cost C _M.
As shown in, the easier the product is to make, the lower the cost will be.

The manufacturability θc is the number of parts corresponding to each weight ω, where the manufacturability weight ω is 1.0 from good manufacturability to 0.1 and poor manufacturability is 0.1. The manufacturability θc is given by

[0140]

[Equation 28]

As can be seen from (Equation 28), θc is 0 to 1
It is a scale that can evaluate the easiness of making a product considering the number of parts.

As shown in FIG. 8, the mounting diagram contains know-how of component mounting information. That is, the mounting order rule 100 for improving the automation rate has a mounting order such that the insertion IC is inserted before the axial part, the insertion IC is inserted before the radial part, and the axial part is inserted before the radial part. However, based on this rule, the insertion IC component inserting machine 150 → axial component inserting machine 160 → radial component inserting machine 180 → robot variant component inserting machine 190 → the first to fifth steps of manual insertion 200 are configured. The dedicated robot 210 is used together with mechanical parts, for example, when a heat sink for heat radiation is screwed to a power transistor and used. Further, the connector is handled as a hand-inserted component 220 because it is necessary to prevent flux from adhering to the contact portion and to have cleaning resistance.

Here, the component interference with the mounted components as already described with reference to FIG. 4A is shown in FIG. 8 as the vertical component 1 and the vertical component 2 of the aluminum capacitor.

In the present invention, as shown in FIG.
Similar components obtained by grouping 70 the circuit components are prepared. With respect to the component group classified by the similarity of the component form, the chip component group stores operation contents such as adhesive application B, downward movement assembly ↓, and component mounting attribute information such as takt time.

A grouping process 70 is performed on such a group of similar components to create a database, adjacent components are grouped, the head and anvil interference is checked as shown in FIG. 4, and the mounting order rule 100 shown in FIG. The mounting order of the component mounting line can be determined based on

When there are a plurality of lines as shown in FIG. 21, the line is CAD /
The lot information of the lot to be produced is received from the CAM system, and the delivery date simulator 54 uses the expert system 90 composed of knowledge-based and rule-based similar plan information to create a user interface 60 (plan line table).
You can plan by interactive input on the screen.

Here, since the knowledge base 91 has a plurality of lines having the same function in the case of a line, it has a hierarchical structure in which the same function group is integrated for each operation function based on the information shown in FIG. Also, the same function is subdivided by tact ability.

Further, the lot information in the case where lot division allocation has occurred in the past information of similar products is composed of data hierarchically structured by the object-oriented database.

As customer needs diversify and change, it is necessary to meet market needs and produce and supply merchandise in a timely manner and in a required amount when needed.

In the system according to the present invention, the know-how of the planner is stored in the expert system as plan information of similar products in the IF-THEN rule-based rule-based format shown in FIG. Figure 21
Refer to the production quantity, delivery date, etc. of the lot detailed information of the production lot in the screen of the user interface 60 (planning line table) shown in FIG.
It is called in a rule format and is manually modified in an interactive format.

As described above, the delivery time simulator 54 can shorten the delivery time of the product, thereby reducing the delivery time and the cost C.
The relationship of _I is as shown in FIG. Here, quick delivery is a measure for producing and supplying products to the market in a short period of time.
Expressed as the reciprocal of the time it takes to produce and supply a product. As can be seen from FIG. 20, the cost is naturally reduced if the cost is constant as the manufacturing is performed in a short period of time.

As for reliability and maintainability, FIG.
As shown in, the failure rate λ of the product is represented by the total value of the failure rate λ _{E of the} circuit and the failure rate λ _M of the mechanical parts when the mechanical parts are mixedly mounted. That is, the component failure rate λ is registered in the standard component information 82 of FIG. 1, and the product N _{1 of the} number N ₁ of the same parts included in the product and the failure rate λ ₁
It is calculated from λ ₁ by the following equation.

[0153]

[Equation 29]

The relationship between the reliability + maintainability and sociality and the cost C _L is as shown in FIG. Here, sociality is the degree of influence of a product on society such as environmental protection and product liability.

Further, the downsizing property of the product is one of the important functions of the product along with the progress of microelectronics. By adopting the surface mounting component such as the chip component as shown in FIG. It is realized by improving the surface mounting rate.

Further, the downsizing property is improved as shown in FIG. 25 by mounting the circuit components three-dimensionally with no clearance using a solit modeler (not shown).

The relationship between the downsizing property and the cost C _S described above is expressed as shown in FIG. 27 with reference to the product size 34 in FIG.

Product inspection is an important design requirement measure for ensuring product quality.

As shown in FIG. 26, the process capability index Cp is calculated by the following equation.

[0160]

[Equation 30]

That is, when the process capability coefficient Cp is achieved, the product variation is within the tolerance, so that the so-called acceptance inspection becomes unnecessary, and as a result, the relationship between the testability and the cost C _T is shown in FIG. As shown in (a).

However, for this reason, the process control becomes strict, so that the check cost becomes high as shown in FIG. 28 (b). Therefore, it is necessary to set appropriate control limits.

The cost calculated as above is shown in FIG.
As shown in FIG. 9, in the circuit board, requirement analysis, design (circuit design C _D , component layout C _S , wiring C _W ), manufacturing C _M , test C
Costs such as _T and maintenance _CL (including disposal / reuse / recycling) are summed up, that is, life cycle total cost
110 is calculated by the life cycle cost simulator 50 of FIG. Where life cycle cost 110
As shown in FIG. 34, the circuit design cost aforementioned C _D
Etc., component placement costs previously described C _S etc., the cost aforementioned C _W
Etc., manufacturing cost is C _M, etc., test cost is C _T, etc., operation / maintenance cost is C _L, etc., disposal cost C, etc.
_L is obtained by the integrator 111 as the above-mentioned integration of C _{L and the} like.

Further, when the product target specification 81 is determined through the user interface 60 of FIG. 1 as shown in the life cycle cost of FIG. 30, the same as the rule-based similar plan information 92 of FIG. IF to THE
It is also possible to estimate the life cycle cost 110 from the similar product parameter database 120 that is rule-based in the N format.

The life cycle cost simulator 50 includes a wiring difficulty simulator 51, an error durability simulator 52, a manufacturability simulator 53, a delivery schedule simulator 54, a reliability + maintainability (including sociality) simulator 55, and downsizing. It is composed of a simulator 56 and a testability simulator 57, and their structures are as shown in FIG.

Each of these life cycle cost simulators 50 is capable of parallel processing not shown, and is capable of simultaneous parallel processing by a distributed real-time OS (Operating System).

In this way, the product life cycle cost C110 is obtained, but the net profit M obtained by research and development is M.
Is divided by C, the development investment efficiency μ is obtained.

The relationship between the life cycle cost C and the net profit M is as shown in the development investment efficiency predicting means 250 of FIG.

At this time, μ varies depending on the target product as a company, but it is clear that 100% or more is desirable.

Predicting the development investment efficiency μ by such a development investment efficiency predicting means 250 at the research and development stage is a very important index in corporate strategy, and is automatically calculated in the present invention. ing. The concept of the product development optimum design of the present invention as described above is achieved by the third place of the methodology, the computer support tool and the humanware as shown in FIG. That is, as a methodology, characteristic feasibility θ as a unified evaluation scale for life cycle cost
The life cycle cost simulator 50 has been introduced as a computer support tool as a life cycle cost compatible simulator, and the top-down and bottom-up hot exchanges as humanware have made it possible for the designer to consider product quality factors. Analysis means 51
The feature is that the development investment efficiency prediction means 250 is introduced to the manager.

FIG. 37 shows the automatic evaluation items by the computer.
310 and the evaluation items 320 to be evaluated by the dialog with the user are collectively described. A functional unit for performing the automatic evaluation item 310 is provided in the design rule check 75, and a functional unit for performing the evaluation item 320 to be evaluated by the interaction with the user is provided in the user interface 60. As shown in this figure, automatic evaluation items by computer
As 310, component interference check, number of layers that can be wired, channel number range estimation, reliability + maintainability evaluation, downsizing evaluation, life cycle cost simulation,
There is a prediction of development investment efficiency. The evaluation items 320 evaluated by the interaction with the user include loss cost calculation, bare board manufacturing cost, sub-circuit division evaluation, error durability evaluation, manufacturability evaluation, delivery time simulation, testability evaluation, product quality factor analysis. There is.

According to the present invention, by performing a simulation at the conceptual stage of the circuit board, it is possible to realize early commercialization as shown in FIG. 33 and to improve quality and reduce cost.

[0173]

As described above, according to the present invention, it is possible to simultaneously achieve the contradictory development goals of performance improvement, low cost, quality improvement and short-term product development.

Further, by incorporating a lot of information about the life cycle at the conceptual design stage, it becomes possible to design with higher quality.

Further, according to the present invention, it is possible to design a new product by utilizing the know-how of a similar product having a production record, and it is also possible to shorten the development period of the new product.

Since CAD / CAM / CAT processing can be performed in parallel at the same time, there is an effect that the design efficiency is significantly improved as compared with the conventional case.

Furthermore, according to the present invention, CAD / CAM /
By unifying the interface that connects the CAT processing devices, you can modify the CAD data by simply modifying the CAD data.
The data for AM / CAT can also be modified, and the effect of significantly reducing the number of work steps can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an outline of an overall configuration of a product development optimum design support system according to an embodiment of the present description.

FIG. 2 is an explanatory diagram illustrating a flow of conventional product design and manufacturing evaluation and improvement.

FIG. 3 is an explanatory diagram showing a design knowledge base of a rule-based expert system.

FIG. 4 is an explanatory view showing interference by an insertion head or anvil of a component.

FIG. 5 is an explanatory diagram showing a relationship between characteristic feasibility and a signal factor, and an SN ratio and a signal factor.

FIG. 6 is an explanatory diagram showing a relationship between a signal factor and a characteristic value.

FIG. 7 is an explanatory diagram showing characteristic values and loss cost functions.

FIG. 8 is an explanatory diagram showing a line mounting sequence of a user interface.

FIG. 9 is an explanatory diagram showing a product quality factor analysis means of the life cycle simulator.

FIG. 10 is an explanatory diagram showing the structure of product quality.

FIG. 11 is an explanatory diagram showing a radar chart of characteristic feasibility of a life cycle cost simulator screen.

FIG. 12 is an explanatory diagram showing the relationship between the mounting density and the number of substrate layers.

FIG. 13 is an explanatory diagram showing an interactive input screen for calculating a bare board cost of the life cycle cost simulator screen.

FIG. 14 is an explanatory diagram showing the relationship between the number of substrate layers and the bare board cost.

FIG. 15 is an explanatory diagram showing a mounting density and a total cost of a life cycle cost simulator screen.

FIG. 16 is an explanatory diagram showing a grouping processing database.

FIG. 17 is an explanatory diagram showing a relationship between wiring difficulty and cost.

FIG. 18 is an explanatory diagram showing a relationship between error durability and cost.

FIG. 19 is an explanatory diagram showing a relationship between manufacturability and cost.

FIG. 20 is an explanatory diagram showing the relationship between shortened delivery time and cost.

FIG. 21 is an explanatory diagram illustrating a configuration of a delivery date simulator.

FIG. 22 is an explanatory diagram showing an example of knowledge base registration in the IF-THEN rule format.

FIG. 23 is an explanatory diagram showing a failure rate of products.

FIG. 24 is an explanatory diagram showing a relationship between reliability + maintainability and cost.

FIG. 25 is an explanatory diagram showing a surface mounting rate, mounting without clearance and downsizing.

FIG. 26 is an explanatory diagram showing process capability coefficients.

FIG. 27 is an explanatory diagram showing a relationship between downsizing property and cost.

FIG. 28 is an explanatory diagram showing the relationship between testability and cost.

FIG. 29 is an explanatory diagram showing a total cost curve diagram of life cycle costs.

FIG. 30 is an explanatory diagram showing life cycle cost prediction based on similar products.

FIG. 31 is an explanatory diagram showing a development investment efficiency prediction method for a life cycle cost simulator screen.

FIG. 32 is an explanatory diagram showing a configuration of a life cycle cost simulator.

FIG. 33 is an explanatory diagram showing the effect of reducing the design man-hours of the present invention.

FIG. 34 is an explanatory diagram showing constituent factors of the life cycle cost and a method of accumulating these components.

FIG. 35 is an explanatory diagram showing the concept of product development optimum design of the present invention.

FIG. 36 is an explanatory diagram showing a circuit block division evaluation unit by table calculation.

FIG. 37 is an explanatory diagram of automatic evaluation items by a computer and evaluation items evaluated by a dialog with a user.

[Explanation of symbols]

20 ... CAD / CAM / CAT processing device, 31 ... Design evaluation information interface unit, 40 ... Evaluation information database unit, 50 ... Life cycle cost simulator, 51
... product quality factor analysis means, 75 ... design rule check, 80 ... design information, 90 ... rule-based expert system, 250 ... development investment efficiency prediction means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuharu Hayakawa 890 Kashimada, Sachi-ku, Kawasaki, Kanagawa Hitachi System Plaza Shin-Kawasaki Information Systems Division, Hitachi, Ltd. (72) Inventor Hiroshi Nishida 2880 Kunifu, Odawara, Kanagawa Company Hitachi Storage Systems Division (72) Inventor Yojiro Tezuka 2880 Kozu, Odawara, Kanagawa Stock Company Hitachi Storage Systems Division (72) Inventor Teruo Mori 2880 Kozu, Odawara, Kanagawa Hitachi Ltd. In storage system division (72) Inventor Satoshi Minoshima 2880 Kozu, Odawara-shi, Kanagawa Hitachi Ltd. Storage system division (72) Inventor Masaaki Ikeda 4-chome Kanda Surugadai, Chiyoda-ku, Tokyo (72) Inventor, Shoji Arimoto, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company, Hitachi, Ltd.

Claims (6)

[Claims] 1. A wiring difficulty level, a product size, and a manufacturability of a target product based on information about the target product of a computer-aided support system for improving product design efficiency.
A design evaluation information generation unit that generates evaluation information that is an evaluation target including information about product quality including at least one of delivery date data, error durability data, reliability and maintainability data, and cost data, An evaluation information database that stores the information generated by the evaluation information generation unit, and based on the information stored in the evaluation information database,
A life cycle cost simulator that generates an evaluation index using the same evaluation scale for each of the cost for manufacturing the target product and the product quality of the target product, and simulates the life cycle cost based on the evaluation index. And a rule-based expert system constructed by classifying design information of similar products similar to the target product into minimum knowledge units that constitute the product and defining a design procedure by combining the minimum knowledge units. And a dialogue unit that refers to a knowledge unit of the rule-based expert system to exchange information for generating a design procedure of the target product, information of the knowledge unit of the rule-based expert system, and the target product. A design that automatically evaluates the design procedure of the target product using the related information. Product development optimal design support system characterized by comprising: a rule check means. 2. The design evaluation information generating section, based on information related to a target product of the computer aided support system,
From information on product quality including at least one of wiring difficulty, product size, manufacturability, delivery date data, error durability data, reliability and maintainability data of the target product, and cost data. The product development optimum design support system according to claim 1, wherein evaluation information to be evaluated is input to the life cycle cost simulator. 3. The life cycle cost simulator is made up of characteristic feasibility of a product from design / manufacturing / inspection / operation / reuse / reuse / disposal, built-in quality constituting the product, and these characteristic values. The product development optimum design support system according to claim 1, further comprising a product quality factor analysis means for performing optimization in a multi-layer structure. 4. The life cycle cost simulator has a development investment efficiency predicting means for obtaining a development investment efficiency by dividing a net profit expected to be obtained by research and development by a life cycle cost. Item 1 Optimal design support system for product development. 5. The design rule checking means determines a total value of the number of component pins of circuit components to be used in a circuit design stage in the computer-aided support system as a projected area of a component including a pad size from an assumed substrate area. The pin density is estimated by dividing by the value obtained by subtracting the aggregated value, the wiring capacity is estimated based on the pin density, and the number of layers that can be mounted is calculated by dividing the wiring capacity by the wiring accommodating value per layer. 2. The product development optimum design support system according to claim 1, which estimates and compares the number of mountable layers with an estimated total cost to determine whether the circuit board is good or bad. 6. The interactive means inputs the information of the result of evaluation by dividing each block into a circuit and designing at the circuit design stage of the circuit board in the computer-aided support system. A means for totalizing and displaying the information, a means for inputting at least one of wiring difficulty of each part, manufacturability, total cost of each part, and circuit allocation information having a uniform board area, The product development optimum design support system according to claim 1, further comprising: