JPH06195219A - Data processor - Google Patents

Abstract

PURPOSE:To provide a data processor where the deterioration of efficiency at the time of executing a return sub-routine instruction is avoided and waste in a pipeline processing mechanism does not occur on the execution of the sub-routine jump instruction. CONSTITUTION:A freeze bit 227 preventing a return destination instruction from being substituted for a newly prefetched instruction when the return destination instruction is stored in a data memory 210 at the time of executing the sub-routine jump instruction is provided. Furthermore, an address saving register (RA) storing the return destination address at the time of executing the sub-routine jump instruction is provided. An address saving register (RAS) storing plural return destination addresses at the time of executing the sub-routine jump instruction is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for prefetching instructions to perform pipeline processing, and more particularly to a data processing device for executing return subroutine instruction processing at high speed and predicting a branch jump instruction.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 7, 8 and 9. FIG. 7 is a schematic diagram showing each stage of the pipeline when the pipeline processing of five stages is performed in the conventional microprocessor.

In the example shown in FIG. 7, an instruction fetch stage (hereinafter referred to as an IF stage) 101 for prefetching an instruction, a decode stage (hereinafter referred to as a D stage) 102 for decoding an instruction, and an address calculation of operands are performed. Operand address calculation stage to perform (hereinafter, A
Operand fetch stage (hereinafter, referred to as F stage) 106, which includes a stage 103), a stage for accessing micro ROM (particularly referred to as R stage) 104 and a stage for prefetching operands (particularly referred to as OF stage) 105, and executes an instruction The five stages of execution stages (hereinafter referred to as E stages) 107 are the basics of pipeline processing.

Further, the instruction code is decomposed into a plurality of pipeline processing units (hereinafter referred to as step codes) and processed so that balanced pipeline processing can be performed in each stage in processing the instructions. IF stage 101 to D
The information passed to the stage 102 is the instruction code 108 itself. The information passed from the D stage 102 to the A stage 103 is the information related to the operation designated by the instruction (hereinafter, D
It is two pieces of information, that is, the code 109) and the information regarding the operand address calculation (hereinafter referred to as the A code 110).

Information passed from the A stage 103 to the F stage 106 is an R code 111 including an entry address of a microprogram routine, parameters to the microprogram, and an F code 112 including an operand address and access instruction information. There are two types of information. F stage
The information passed from the E 106 to the E stage 107 is two pieces of information, an E code 113 including operation control information, a literal, etc., and an S code 114 including an operand, an operand address, etc.

FIGS. 8 and 9 are block diagrams showing a specific internal configuration example of each pipeline processing stage shown in FIG. Note that FIG. 8 mainly shows the IF stage 101.
9 and FIG. 9 mainly show the internal configurations of the A stage 103, the F stage 106 and the E stage 107, respectively.

In the IF stage 101 of FIG.
201 is an instruction fetch register (IIN) that stores the instruction code fetched from the outside, 202 is a selection circuit (SELCT) that selects either the output of the instruction fetch register 201 or the instruction code output from the internal cache, 203 is an instruction queue for storing instruction codes in the fetch order,
Is a fetch address counter (QINPC) that calculates the address of the instruction fetch destination, 205 is an incrementer (INC) that counts up the address value of the fetch address counter 204, and 206 is a tag register that stores the address tag. 207 is an index register that stores the index of the address, 208 is an index decoder that decodes the index value and asserts the instruction cache entry, 209 is tag memory that stores the address tag of the instruction cache, and 210 is the instruction cache. , 211 indicates a data memory output BOUT of the entry asserted by the index decoder 208, and 212 indicates a fetch address register CAA for storing an instruction fetch address.

Reference numeral 280 is registration data for registering an instruction code fetched from the outside in the data memory 210, and reference numeral 281 is an instruction code without passing through the instruction queue 203.
Each shows a bypass for loading on IN bus 251.

In the D stage 102 of FIG.
Reference numeral 213 denotes an instruction decoding unit that decodes the instruction code 108, and 214 denotes a PC arithmetic unit that calculates the start address of the instruction code being processed by the instruction decoding unit 213.

Reference numeral 283 is a branch displacement address value of a branch instruction, 284 is a PC control signal for calculating a program count (PC) value, 286 is a subroutine jump instruction detection signal, and 287 is a branch destination address. , 288 indicates the start address of the decoded instruction.

At the A stage 103 in FIG.
Reference numeral 215 denotes an address calculator that calculates the address of the operand required for the processing in the E stage 107. Further, reference numeral 289 indicates an operand fetch address indicating a fetch destination of the operand.

In the F stage 106 of FIG.
217 is a micro ROM for controlling the F stage 106 and the E stage 107, 218 is an F code address register (FA) for storing the calculation result of the address calculation unit 215, and 220 is an address of the F code address register 218. The S code data register (SD) for storing the operands is shown.

In E stage 107 of FIG.
221 is a register file that internally stores the data used in the E stage 107, and 222 is an ALU that performs binary operation.
223 is an external data register (DD) for storing external data processed by the E stage 107, and 224 is an E stage 107.
The external data address register (AA) for storing the address of the external data to be processed in FIG.

Further, reference numeral 250 is a DD bus for loading data input / output to / from the data processor, 251 is a QIN bus for loading an instruction code, and 252 is a branch destination address value. The CA bus, 253 is the DISP bus that loads the displacement address value of the branch instruction, 254 is the AO bus that loads the output of the address calculation unit 215, and 256 is the
S1 bus for loading ALU 222 calculation source, 255 for AL
S2 bus to load the calculation source of U222, 257 is ALU
The DO bus for loading the operation result of 222 and 258 for the AA bus for loading the address of the data which this data processing unit inputs / outputs to / from the outside are respectively shown.

The operation of the conventional data processing apparatus as described above is as follows. Here, the case of processing a normal instruction other than the jump instruction will be described first.

First, an instruction code is loaded onto the DD bus 250 from the outside according to the address indicated by the CAA 212. The loaded instruction code is taken into IIN 201. IIN 201
The instruction code fetched by the device is temporarily stored in the instruction queue 203 via the SELCT 202 and then stored in the FIFO (First In First
Out) will be loaded onto QIN bus 251 according to order. When the branch destination instruction is fetched immediately after the branch instruction, the branch destination instruction code is loaded directly into the QIN bus 251 through the bypass 281 without passing through the instruction queue 203.

On the other hand, if the branch destination instruction exists in the data memory 210 of the instruction cache, the data memory output 21
Select 1 in SELCT 202 and Q via bypass 281 directly
The branch target instruction code is loaded into the IN bus 251. For subsequent instruction code fetching, the value of QINPC 204 is incremented by INC 205, loaded on CA bus 252, fetched to CAA 212, and the instruction code is fetched sequentially according to the address value of this CAA 212.

The instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. As a result of this instruction code being decoded, the instruction length decoded as the PC control signal 284 is output to the PC operation unit 214, and the instruction decoding unit 213 calculates the start address (PC value) of the instruction code to be decoded accordingly.

The address calculation unit 215 is an instruction decoding unit 213.
Operand address value is calculated according to the A code 110 given by
Load on bus 254.

The operand fetch address 289 loaded on the AO bus 254 is fetched by the FA 218 and loaded on the AA bus 258. According to the address output to the AA bus 258, the operand is externally loaded into the DD bus 250 and further loaded into the SD 220.

The operands used in the operation are loaded from SD 220 to S2 bus 255. One operand is loaded from register file 221 or DD 223 onto S1 bus 256. The value of DD 223 is externally loaded to DD bus 250 and taken into DD 223 according to the address value loaded to AA bus 258 from AA 224. S1 bus 256 and S2 bus 25
The two values loaded into 5 are calculated by the ALU 222, and the calculation result is loaded into the DO bus 257 and registered in the register file.
Captured by 221 or DD captured by DD 223
It is loaded onto the bus 250 and transferred to external memory. Thereafter, the pipeline processing in each stage repeats the same operation.

Next, the operation of processing a return subroutine (RTS) instruction in the conventional data processing apparatus will be described. The value of QINPC 204 is incremented according to HA sequential INC 205, and the RTS instruction is externally loaded onto DD bus 250 and taken into IIN 201. The instruction code for this RTS instruction is SE, as if a normal instruction were processed.
ICT 201 input selected in LCT 201 and instruction queue 203
Via QIN bus 251.

The RTS instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. Then, as a result of the decoding, the instruction length of the decoded RTS instruction is output to the PC operation unit 214 as the PC control signal 284, and the start address (PC value) of the instruction next to the RTS instruction is calculated.

The address calculation unit 215 includes an instruction decoding unit 21
Since the A code 110 relating to the RTS instruction is given from 3, the operand address value is calculated and the operand fetch address 289 is loaded into the AO bus 254.

The operand fetch address 289 loaded on the AO bus 254 is fetched by the FA 218 and loaded on the AA bus 258. The operand is externally loaded onto DD bus 250 according to the address output on AA bus 258, and SD
It is taken in by 220.

The operands used in the operation are loaded from SD 220 to S2 bus 255. One operand is loaded from register file 221 or DD 223 onto S1 bus 256. The value of DD 223 is externally loaded to DD bus 250 and taken into DD 223 according to the address value loaded from AA 224 to AA bus 258. S1 bus 256 and S2 bus
The two values loaded in 255 are operated on by the ALU 222, and the operation result is loaded on the DO bus 257 and fetched in the register file 221. The operation result fetched in the register file shows the return destination address of the RTS instruction, and this entry destination address is loaded into the CA bus 252.

The return destination address loaded in the CA bus 252 is fetched in the QINPC 204, CAA 212, tag register 206, and index register 207. The return destination address fetched by the CAA 212 is loaded into the AA bus 258, and the return destination instruction is fetched from the outside and loaded into the DD bus 250. QINPC 2 after fetching the return destination instruction
The return address fetched in 04 is incremented by INC 205 and the subsequent instructions of the return destination instruction are fetched in sequence.

On the other hand, the instruction cache is searched according to the return address fetched in the tag register 206 and the index register 207, and if it is already registered in the instruction cache, it is registered in the data memory 210 from the entry indicated by the index decoder 208. Return destination instruction code is output and data memory output register
Captured by BOUT 211. In SELCT 202, in response to the instruction cache hit, the value of BOUT 211 is selected and output to the instruction queue 203. When the instruction immediately after the jump instruction such as the return instruction is processed, the return destination instruction code is directly loaded into the QIN bus 251 without passing through the instruction queue 203. The following operation is the same as the operation of a normal instruction in the processing after the instruction decoding unit.

[0029]

By the way, in the conventional data processing device for prefetching the above-mentioned instruction,
When processing a subroutine jump instruction, it is necessary to fetch the return destination instruction again from the outside when executing the return subroutine instruction, even though the return destination instruction is prefetched together with the subroutine jump instruction with a high probability. However, the processing efficiency was lowered.

Further, when the pipeline processing mechanism is provided, there is a problem that all the contents processed by the pipeline processing mechanism are wasted.

The present invention has been made in view of the above circumstances, and when executing a subroutine jump instruction, avoids a decrease in efficiency during execution of a return subroutine instruction, and does not waste data in the pipeline processing mechanism. It is intended to provide a processing device.

[0032]

According to a first aspect of the invention, when a return jump instruction is stored in an instruction storage means when a subroutine jump instruction is executed, the instruction is newly prefetched. Equipped with a means to prevent replacement by.

The second aspect of the invention further comprises address storage means for storing the return address when the subroutine jump instruction is executed.

Further, the third invention comprises an address storage means for storing a plurality of return destination addresses when the subroutine jump instruction is executed.

[0035]

In the first aspect, when the subroutine jump instruction is executed, if the return destination instruction is stored in the instruction storage means, the instruction is not replaced with the newly prefetched instruction. Therefore, when the return subroutine instruction is executed, the return destination instruction is read from the instruction storage means without being newly fetched from the outside.

In the second invention, when the subroutine jump instruction is executed, its return destination address is stored in the address storage means, and the instruction of the address stored in this address storage means is fetched in the instruction storage means. It When the return subroutine instruction is executed, the return destination instruction is read from the instruction storage means according to the return destination address read from the address storage means without being newly fetched from the outside.

Further, in the third invention, when the subroutine jump instruction is executed, the return destination addresses thereof are sequentially stored in the address storage means, and the instruction of the address stored in the address storage means is stored in the instruction storage means. To be fetched. When the return subroutine instruction is executed, the return destination instruction is sequentially read from the instruction storage means according to the return destination address read from the address storage means without being newly fetched from the outside.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. First, the data processing apparatus of the first invention of the present invention, in which the concrete internal configuration example of each pipeline processing stage is shown in the block diagrams of FIGS. 1 and 2, will be described.

FIG. 1 mainly shows the internal structures of the IF stage 101 and the D stage 102, and FIG. 2 mainly shows the internal structures of the A stage 103, the F stage 106 and the E stage 107, respectively. 8 and 9 which are referred to in the description of the conventional example, indicate the same or corresponding parts.

In the IF stage 101 of FIG.
201 is an instruction fetch register (IIN) that stores the instruction code fetched from the outside, 202 is a selection circuit (SELCT) that selects either the output of the instruction fetch register 201 or the instruction code output from the internal cache, 203 is an instruction queue for storing instruction codes in the fetch order,
Is a fetch address counter (QINPC) that calculates the address of the instruction fetch destination, 205 is an incrementer (INC) that counts up the address value of the fetch address counter 204, and 206 is a tag register that stores the address tag. 207 is an index register that stores the index of the address, 208 is an index decoder that decodes the index value and asserts the instruction cache entry, 209 is tag memory that stores the address tag of the instruction cache, and 210 is the instruction cache. , 211 indicates a data memory output BOUT of the entry asserted by the index decoder 208, and 212 indicates a fetch address register CAA for storing an instruction fetch address.

The structure of the IF stage 101 described above is the same as that of the conventional example shown in FIG. 8. However, in the data processor of the first invention, the index decoder 208 of the instruction cache is further shown in the IF stage 101. The tag memory output register 225 of the entry, the tag address fetched from the CA bus 252 and stored in the tag register 206 and the tag memory output of the tag memory 209 of the instruction cache and held in the tag memory output register 225. A tag address comparator 226 for comparing the output value and a freeze bit 227 that can freeze each entry in the data memory 210 of the instruction cache are provided.

Reference numeral 280 indicates registration data for registering an instruction code fetched from the outside in the data memory 210, and 281 indicates the instruction code without passing through the instruction queue 203.
Each shows a bypass for loading on IN bus 251.

In the D stage 102 of FIG.
Reference numeral 213 denotes an instruction decoding unit that decodes the instruction code 108, and 214 denotes a PC arithmetic unit that calculates the start address of the instruction code being processed by the instruction decoding unit 213.

Reference numeral 283 is a branch displacement address value of a branch instruction, 284 is a PC control signal for calculating a program count (PC) value, 286 is a subroutine jump instruction detection signal, and 287 is a branch destination address. , 288 indicates the start address of the decoded instruction.

In the A stage 103 of FIG.
Reference numeral 215 denotes an address calculator that calculates the address of the operand required for the processing in the E stage 107. The configuration of the above A stage 103 is the same as that of the conventional example shown in FIG. 9, but in the data processor of the first aspect of the present invention, the instruction decoding unit 213 further decodes the return instruction in the A stage 103. A return subroutine instruction (RTS) detect signal 293 is provided. Further, reference numeral 289 indicates an operand fetch address indicating a fetch destination of the operand.

In the F stage 106 of FIG.
217 is a micro ROM for controlling the F stage 106 and the E stage 107, 218 is an F code address register (FA) for storing the calculation result of the address calculation unit 215, and 220 is an address of the F code address register 218. The S code data register (SD) for storing the operands is shown.

The configuration of the above F stage 106 is similar to that of the conventional example shown in FIG. 9, but in the data processing apparatus of the first invention, the value of the F code address register 218 is further added to the F stage 106. Address save register (RA) to save
219 and a return address control signal 292 for instructing the CA bus 252 to load a return address.

In E stage 107 of FIG.
221 is a register file that internally stores the data used in the E stage 107, and 222 is an ALU that performs binary operation.
223 is an external data register (DD) for storing external data processed by the E stage 107, and 224 is an E stage 107.
The external data address register (AA) for storing the address of the external data to be processed in FIG.

Further, reference numeral 250 is a DD bus for loading data input / output to / from the outside by this data processing device, 251 is a QIN bus for loading an instruction code, and 252 is a branch destination address value. The CA bus, 253 is the DISP bus that loads the displacement address value of the branch instruction, 254 is the AO bus that loads the output of the address calculation unit 215, and 256 is the
S1 bus for loading ALU 222 calculation source, 255 for AL
S2 bus to load the calculation source of U222, 257 is ALU
The DO bus for loading the operation result of 222 and 258 for the AA bus for loading the address of the data which this data processing unit inputs / outputs to / from the outside are respectively shown.

The operation of processing the subroutine jump (JSR) instruction in the data processor according to the first aspect of the present invention will be described below. However, since the operations of the normal instructions other than the jump instruction are the same as those of the conventional data processing device, the description thereof will be omitted.

First, the JSR instruction code is loaded onto the DD bus 250 from the outside according to the address indicated by the CAA 212.
The loaded JSR instruction code is taken into IIN 201. The JSR instruction code fetched by IIN202 is SELCT 2
After being stored in the instruction queue 203 via 02, the FIF
Loaded on QIN bus 251 according to O (First In First Out) order.

The JSR instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. As a result of this instruction code being decoded, it is instructed to fetch the branch displacement address value 283 as the PC control signal 284 from the DISP bus 253. The PC calculation unit 214 calculates the branch destination address 287 from the branch displacement address value 283 according to the PC control signal 284 and loads it on the CA bus 252. The branch destination address 287 loaded on the CA bus 252 is taken into the CAA 212, QINPC 204, and the tag register 206 and index register 207 of the instruction cache.

In the instruction cache, the tag memory is searched according to the values of the tag register 206 and the index register 207. If it is already registered in the instruction cache, the instruction code from the data memory corresponding to that entry
It is output to BOUT 211, the instruction code on the instruction cache side is selected by SELCT 202, and loaded to QIN bus 251 via bypass 281.

If not yet registered, according to the branch destination address loaded from CAA 212 to AA bus 258,
The branch destination instruction code is fetched into the external memory and this
Loaded onto DD Bus 250 and taken into IIN 201. SE
In LCT 202, IIN 201 is selected and the branch destination instruction code is loaded into QIN bus 251 via bypass 281.
After fetching the branch destination instruction code, the value of QINPC 204 again
The value obtained by incrementing (= branch destination address) by INC 205 is loaded to CA bus 252 and fetched to CAA 212.
Fetching of the subsequent instruction at the branch destination address continues.

On the other hand, the address calculation unit 21 of the A stage 103
In 5, when the JSR instruction is decoded by the instruction decoding unit 213, the instruction length of the JSR instruction decoded as the A code 110 is received from the instruction decoding unit 213. Also, PC
Receives the start address of the JSR instruction from the operation unit 214. JSR
The next instruction (return destination instruction) address of the JSR instruction is calculated from the instruction length of the instruction and the start address of the JSR instruction, and loaded to the AO bus 254.

The return destination address loaded on the AO bus 254 is fetched into the FA 218. Further, upon receiving the subroutine jump instruction (JSR) detection signal 286 from the instruction decoding unit 213, the return address fetched in the FA 218 is saved in the RA 219. Further, when the JSR detection signal 286 is input to the micro ROM 217, the return address control signal 292 is output and the return destination address saved in RA 219 is loaded into the CA bus 252.

As for the return destination address loaded in the CA bus 252, the upper address is fetched in the tag register 206 and the lower address is fetched in the index register 207. The index decoder 208 asserts a specific entry according to the value in the index register 207,
The tag address is output from the tag memory 209 to the tag memory output register 225.

In the tag address comparator 226, the CA bus 252
The value of the tag register 206 fetched from is compared with the value of the tag memory output register 225. If you hit J
If the SR detection signal 286 is asserted, the output BOUT 211 of the data memory 210 of the entry asserted by the index decoder 208 is not output to the SELCT 202. Instead, the freeze bit 227 of the asserted entry described above is set to protect it from being replaced by another externally fetched instruction.

Also, when a mishit occurs, the JSR detection signal 28
If 6 is asserted, the fetch of the instruction subsequent to the branch destination instruction is continued according to the value of QINPC 204 without fetching the return destination externally.

When the subroutine jump instruction is executed again, the same operation as described above is repeated.

Finally, the operation of the data processing apparatus of the present invention when processing a return subroutine (RTS) instruction will be described. The value of QINPC 204 is sequentially incremented according to INC 205, and the RTS instruction is externally loaded to DD bus 250 and taken into IIN 201. SELCT 201 selects the input of IIN 201 as in a normal instruction and the instruction queue
It is loaded onto QIN bus 251 via 203.

The RTS instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. When the RTS instruction is decoded in the instruction decoding unit 213, the RTS instruction detection signal
Output 293 to micro ROM 217.

In the micro ROM 217, the RTS instruction detection signal 29
In response to 3, output the return address control signal 292,
Return address saved in RA 219 to CA bus 252
To load. After this, the other jump instructions (JSR
Command etc.) That is, the return address loaded on the CA bus 252 is the CAA 212, QINPC 204, the instruction cache tag register 206, and the index register 20.
Incorporated in 7.

The instruction cache searches the address memory according to the values of the tag register 206 and the index register 207. Since the freeze bit 227 of the entry of the return destination instruction is set in advance to protect the return destination instruction from being replaced, the instruction cache is hit with a high probability.

Similar to a normal instruction cache search, the index decoder 208 asserts a particular entry according to the value in the index register 207. The asserted values of the tag memory 209 and the data memory 210 are fetched into the tag memory output register 225 and BOUT 211, respectively. The tag address comparator 226 compares with the value of the tag register 206 fetched from the CA bus 252.

When there is a hit, the value of BOUT 211 is SELC
The return destination instruction is loaded directly into the QIN bus 251 via the bypass 281 according to the hit signal input to T 202. Also, the freeze signal 227 previously set by the hit signal is reset. On the other hand, in the case of a mishit, it is fetched to the external memory according to the return destination address loaded from the CAA 212 to the AA bus 258.

Thereafter, the instruction following the return destination instruction is QINPC.
The value obtained by incrementing the return address of 204 with INC 205 is loaded into CA bus 252 and loaded into CAA 212, and CA
Continue fetching sequentially according to the value of A 212.

Next, the data processor of the second invention of the present invention, in which the concrete internal configuration example of each pipeline processing stage is shown in the block diagrams of FIGS. 3 and 4, will be explained. Note that FIG. 3 mainly shows the internal configurations of the IF stage 101 and the D stage 102, and FIG. 4 mainly shows the internal configurations of the A stage 103, the F stage 106, and the E stage 107, respectively. 8 and 9 referred to in the description of FIG. 8 indicate the same or corresponding parts.

In the IF stage 101 of FIG.
201 is an instruction fetch register (IIN) that stores the instruction code fetched from the outside, 202 is a selection circuit (SELCT) that selects either the output of the instruction fetch register 201 or the instruction code output from the internal cache, 203 is an instruction queue for storing instruction codes in the fetch order,
Is a fetch address counter (QINPC) that calculates the address of the instruction fetch destination, 205 is an incrementer (INC) that counts up the address value of the fetch address counter 204, and 206 is a tag register that stores the address tag. 207 is an index register that stores the index of the address, 208 is an index decoder that decodes the index value and asserts the instruction cache entry, 209 is tag memory that stores the address tag of the instruction cache, and 210 is the instruction cache. , 211 indicates a data memory output BOUT of the entry asserted by the index decoder 208, and 212 indicates a fetch address register CAA for storing an instruction fetch address.

Reference numeral 280 indicates registration data for registering the instruction code fetched from the outside in the data memory 210, and reference numeral 281 indicates the instruction code without passing through the instruction queue 203.
Each shows a bypass for loading on IN bus 251.

In the D stage 102 of FIG.
Reference numeral 213 denotes an instruction decoding unit that decodes the instruction code 108, and 214 denotes a PC arithmetic unit that calculates the start address of the instruction code being processed by the instruction decoding unit 213.

Reference numeral 283 is a branch displacement address value of a branch instruction, 284 is a PC control signal for calculating a program count (PC) value, 286 is a subroutine jump instruction detection signal, and 287 is a branch destination address. , 288 indicates the start address of the decoded instruction.

In A stage 103 of FIG. 4, reference numeral
Reference numeral 215 denotes an address calculator that calculates the address of the operand required for the processing in the E stage 107. Further, reference numeral 289 indicates an operand fetch address indicating a fetch destination of the operand.

In the F stage 106 of FIG.
217 is a micro ROM for controlling the F stage 106 and the E stage 107, 218 is an F code address register (FA) for storing the calculation result of the address calculation unit 215, and 220 is an address of the F code address register 218. The S code data register (SD) for storing the operands is shown.

The configuration of the F stage 106 described above is the same as that of the conventional example shown in FIG. 9. However, in the data processing apparatus of the second invention, the F stage 106 is further provided with the instruction decoding unit 213 of the D stage 102. Detection register 216 that stores the fact that a subroutine jump instruction has been detected, and an address save register that saves the value of the F code address register 218
(RA) 219 and fetch count control signal 290 indicating how many instructions are fetched by INC 205 of IF stage 101
And detect that the return instruction has been fetched
Return fetch control signal 291 transmitted from 216 to micro ROM 217 and return address control signal 292 for instructing to load return destination address to CA bus 252
And a return subroutine instruction (RTS) detection signal 29 indicating that the instruction decoding unit 213 has decoded the return instruction.
3 is equipped.

In E stage 107 of FIG.
221 is a register file that internally stores the data used in the E stage 107, and 222 is an ALU that performs binary operation.
223 is an external data register (DD) for storing external data processed by the E stage 107, and 224 is an E stage 107.
The external data address register (AA) for storing the address of the external data to be processed in FIG.

Further, reference numeral 250 is a DD bus for loading data input / output to / from the data processor, 251 is a QIN bus for loading an instruction code, and 252 is a branch destination address value. The CA bus, 253 is the DISP bus that loads the displacement address value of the branch instruction, 254 is the AO bus that loads the output of the address calculation unit 215, and 256 is the
S1 bus for loading ALU 222 calculation source, 255 for AL
S2 bus to load the calculation source of U222, 257 is ALU
The DO bus for loading the operation result of 222 and 258 for the AA bus for loading the address of the data which this data processing unit inputs / outputs to / from the outside are respectively shown.

The operation of processing the subroutine jump (JSR) instruction in the data processor of the second invention of the present invention will be described below. However, since the operations of the normal instructions other than the jump instruction are the same as those of the conventional data processing device, the description thereof will be omitted.

First, the JSR instruction code is loaded onto the DD bus 250 from the outside according to the address indicated by the CAA 212. The loaded JSR opcode is captured in IIN 201.
The JSR instruction code fetched by IIN202 is stored in the instruction queue 203 via SELCT 202, and FIFO (First In Fi
rst Out) loaded onto QIN Bus 251 in order.

The JSR instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. As a result of this instruction code being decoded, it is instructed to fetch the branch displacement address value 283 as the PC control signal 284 from the DISP bus 253. The PC operation unit 214 calculates the branch destination address 287 from the branch displacement address value 283 according to the PC control signal 284 and loads it on the CA bus 252.

Branch destination address loaded in CA bus 252
287 is loaded into the CAA 212, QINPC 204, and the tag register 206 and index register 207 of the instruction cache.
In the instruction cache, the address memory is searched according to the values of the tag register 206 and index register 207. If it is already registered in the instruction cache, the instruction code from the data memory corresponding to that entry is BO
It is output to UT211 and the instruction code on the instruction cache side is selected by SELCT 202, and is passed through the bypass 281 to the QIN bus.
Loaded into the 251.

If not registered, CAA 212 to AA
According to the branch destination address loaded on the bus 258, the branch destination instruction code is fetched to the external memory, loaded on the DD bus 250 and fetched in the IIN 201. SELCT
In 202, IIN 201 is selected and via bypass 281
The branch instruction code is loaded into QIN bus 251. The value of QINPC 204 again after the branch destination instruction code is fetched
The value obtained by incrementing (= branch destination address) by INC 205 is loaded to CA bus 252 and fetched to CAA 212.
Fetching of the subsequent instruction at the branch destination address continues.

When the JSR instruction is decoded by the instruction decoding unit 213, the address calculation unit 215 receives the instruction length of the JSR instruction decoded as the A code 110 from the instruction decoding unit 213, and the PC operation unit 214 outputs the JSR instruction Receive the start address. The address calculation unit 215 determines the next instruction of the JSR instruction from the instruction length of the JSR instruction and the start address of the JSR instruction.
Calculate the address of (return destination instruction) and load it to AO bus 254.

The return destination address loaded on the AO bus 254 is fetched by the FA 218. Also, the instruction decoding unit 21
In response to the subroutine jump instruction (JSR) detection signal 286 from 3, the return address fetched by FA 218 is RA.
Evacuated to 219. Further, upon receiving the JSR detection signal 286, a flag is set in the detection register RC 216. After that, IF
The operation of the normal instruction continues according to the branch destination instruction fetched by the stage 101.

In the IF stage 101, the branch destination instruction is, for example, 5
If an instruction is fetched, the fetch count control signal 290 is output from the INC 205 and given to the detection register RC 216. For RC 216, if the flag is set, return fetch control signal 291 to Micro ROM 217.
Reset the flag after outputting. Micro ROM217
Then, in response to the return fetch control signal 291, the fetch operation of the return destination instruction is started.

That is, by outputting the return address control signal 292 from the micro ROM 217, the return destination address saved in the RA 219 is loaded on the CA bus 252,
A 212 capture destination register is changed from QINPC 204 value to RA 2
Switched to a value of 19. At this time, the value of QINPC 204 is kept as it is, and the instruction fetch is started from the value of QINPC 204 held again after fetching the return destination address.

According to the return destination address loaded on the AA bus 258, the return destination instruction code is externally loaded onto the DD bus 250 and taken into the IIN 210. IIN 201
The return instruction code fetched in is micro ROM 217
Under the control of, the data is not captured in the SELCT 202 but registered in the data memory 210 of the instruction cache. The entry at the time of registration in the data memory 210 is an entry designated by the index decoder 208 based on the values of the tag register 206 and the index register 207 which have fetched the return destination address loaded in the previous CA bus 252. . After the return destination instruction code is registered in the instruction cache, the value of QINPC 204 is loaded to the CA bus again
It is fetched by A 212 and fetching of sequential instructions is continued.

Finally, the operation of processing the return subroutine (RTS) instruction in the data processor of the second invention will be described. The value of QINPC 204 is sequentially incremented according to INC 205 and the RTS instruction is externally applied to DD bus 250.
Loaded into and taken into IIN 201. Inputs are selected on the IIN 201 side by the SELCT 201 and loaded into the QIN bus 251 via the instruction queue 203 in the same manner as a normal instruction.

The RTS instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. When the instruction decoding unit 213 decodes the RTS instruction, it outputs the RTS instruction detection signal 293 to the micro ROM 217. Micro ROM
In 217, by receiving the RTS instruction detection signal 293 and outputting the return address control signal 292, the return destination address saved in the RA 219 is loaded into the CA bus 252. The subsequent operation is the same as other jump instructions (JSR instruction, etc.). That is, the return destination address loaded on the CA bus 252 is fetched into the CAA 212, QINPC 204, the tag register 206 and the index register 207 of the instruction cache.

In the instruction cache, the address memory is searched according to the values in the tag register 206 and index register 207. Since the return destination instruction is registered in advance, the instruction cache always hits, and the return destination instruction code is BOUT 2 from the data memory corresponding to the entry.
Output to 11. Upon receiving the hit signal from the instruction cache, the SELCT 202 selects the instruction code of BOUT 211 and loads it into the QIN bus 251 via the bypass 281.

Thereafter, the succeeding instruction of the return destination instruction is QINP.
The value obtained by incrementing the return address of C 204 with INC 205 is loaded to CA bus 252.
212 is fetched and the fetch is sequentially continued according to the value.

As described above, according to the second aspect of the present invention, the return destination address of the return instruction is stored and the return destination instruction is registered in the internal cache to reduce the calculation processing time of the return destination address. Also, high-speed return from a return instruction is possible, and pipeline processing can be performed efficiently.

Next, the invention of the third data processing apparatus of the present invention will be described in which the concrete internal configuration examples of the respective pipeline processing stages are shown in the block diagrams of FIGS. 5 and 6. Note that FIG. 5 mainly shows IF stages 01 and D.
The internal structure of the stage 102, mainly the internal structures of the A stage 103, the F stage 106, and the E stage 107 are shown in FIG. 6, respectively, and FIGS. 3 and 4 referred to in the above description of the second invention. The same reference numerals as those in FIG. 2 denote the same or corresponding parts, and the description thereof will be omitted.

In FIG. 6, reference numeral of the F stage 106
301 is a return address stack (RAS) that can store multiple return destination addresses, 302 is a RAS write pointer that specifies the write destination in RAS 301, and 303 is
A RAS read pointer for designating a read destination from the RAS 301, a detection counter 304 for counting up its own count value 304 upon receiving a subroutine jump instruction (JSR) detection signal 286 from the instruction decoding unit 213 of the D stage 102.
CC) respectively.

The operation of processing the subroutine jump (JSR) instruction in the data processor according to the third aspect of the present invention will be described below. In particular, the second data processing device is effective when processing a plurality of subroutine jump instructions. However, since the operations of the normal instructions other than the jump instruction are the same as those of the conventional data processing device, the description thereof will be omitted.

First, the JSR instruction code is loaded onto the DD bus 250 from the outside according to the address indicated by the CAA 212. The loaded JSR opcode is captured in IIN 201.
The JSR instruction code fetched by IIN202 is stored in the instruction queue 203 via SELCT 202, and FIFO (First In Fi
rst Out) loaded onto QIN Bus 251 in order.

The JSR instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. As a result of decoding this instruction code, it is instructed to fetch the branch displacement address value 283 from the DISP bus 253 as the PC control signal 284. The PC calculation unit 214 calculates the branch destination address 287 from the branch displacement address value 283 according to the PC control signal 284 and loads it on the CA bus 252.

Branch destination address loaded to CA bus 252
287 is loaded into the CAA 212, QINPC 204, and the tag register 206 and index register 207 of the instruction cache.
In the instruction cache, the address memory is searched according to the values of the tag register 206 and index register 207. If it is already registered in the instruction cache, the instruction code from the data memory corresponding to that entry is BO
It is output to UT 211, the instruction code on the instruction cache side is selected by SELCT 202, and the QIN bus is passed through bypass 281.
Loaded into the 251.

If not registered, CAA 212 to AA
According to the branch destination address loaded on the bus 258, the branch destination instruction code is fetched to the external memory, loaded on the DD bus 250 and fetched in the IIN 201. SELCT
In 202, IIN 201 is selected and via bypass 281
The branch instruction code is loaded into QIN bus 251.

QINP is executed again after fetching the branch destination instruction code.
The value of C204 (= branch destination address) incremented by INC205 is loaded to CA bus 252.
The CAA212 fetches and continues fetching subsequent instructions at the branch target address.

When the JSR instruction is decoded by the instruction decoding unit 213, the address calculation unit 215 receives the instruction length of the JSR instruction decoded as the A code 110 from the instruction decoding unit 213 and the PC arithmetic unit 214 starts the JSR instruction at the beginning. Receive an address. Then, the address calculation unit 215 calculates the next instruction (return destination instruction) address of the JSR instruction from the instruction length of the JSR instruction and the start address of the JSR instruction, and
Load it on 254.

The return destination address loaded on the AO bus 254 is fetched by the FA 218. Further, the RCC 304 receives a subroutine jump instruction (JSR) detection signal 286 from the instruction decoding unit 213 of the D stage 102 and counts up its own count value. On the other hand, the return address fetched by the FA 218 is saved in the RAS 301 according to the value of the RAS write pointer 302. This RAS write pointer 30
2 is controlled by RCC 304. After that, IF stage
The operation of processing the normal instruction continues according to the branch destination instruction fetched by 101.

In the IF stage 101, the branch destination instruction is, for example, 5
If an instruction is fetched, the INC 205 outputs the fetch count control signal 290 and supplies it to the RCC 304. RCC 304
Then, if the count value is not "0", the micro ROM 217
The return fetch control signal 291 is output to. micro
The ROM 217 receives the return fetch control signal 291 and starts the fetch operation of the return destination instruction.

That is, by outputting the return address control signal 292 from the micro ROM 217, the RAS 301
The return destination address saved in is loaded from the RAS 301 to the CA bus 252 according to the value of the RAS read pointer 303. However, the RAS read pointer 303 is controlled by the RCC 304. CAA 212 sets the import destination register to QINP
Switch from the value of C 204 to the value of RAS 301. At this time, QI
The value of NPC 204 is kept as it is and QINPC 20 is held again after fetching the return destination address.
The instruction fetch starts from the value of 4.

According to the return destination address loaded on the AA bus 258, the return destination instruction code is externally loaded onto the DD bus 250 and taken into the IIN 210. IIN 201
The return instruction code fetched in is micro ROM 217
Under the control of (1), it is registered in the data memory 210 of the instruction cache without being taken in by the SELCT 202. The entry at the time of registration in this data memory 210 is the above CA bus 252.
It is an entry designated by the index decoder 208 based on the values of the tag register 206 and the index register 207 that have fetched the return destination address loaded in the.

After the return destination instruction code is registered in the instruction cache, the value of QINPC 204 is loaded again to the CA bus, so that CAA 212 fetches this value and the fetching of sequential instructions is continued. The JSR instruction is again sent from outside on the DD bus 25.
When it is loaded to 0, it is fetched to INN 201 like a normal instruction, and is registered to instruction queue 203 via SELCT 202. The JSR instruction code registered in the instruction queue is FIFO (Fir
St In First Out) Loaded onto QIN Bus 251 according to order.

The JSR instruction code loaded on the QIN bus 251 is fetched by the instruction decoder 213. As a result of this instruction code being decoded, it is instructed to fetch the branch displacement address value 283 as the PC control signal 284 from the DISP bus 253. The PC operation unit 214 calculates the branch destination address 287 from the branch displacement address value 283 according to the PC control signal 284 and loads it on the CA bus 252. The branch destination address 287 loaded on the CA bus 252 is fetched by the CAA 212, QINPC 204, the tag register 206, and the index register 207 of the instruction cache.

In the instruction cache, the address memory is searched according to the values of the tag register 206 and index register 207. If it is already registered in the instruction cache, the instruction code is output from the data memory corresponding to that entry to BOUT 211, the instruction code on the instruction cache side is selected by SELCT 202, and it is passed through bypass 281.
Loaded on QIN Bus 251.

If not registered, CAA 212 to AA
According to the branch destination address loaded on the bus 258, the branch destination instruction code is fetched to the external memory, loaded on the DD bus 250 and fetched in the IIN 201. SELCT
In 202, select IIN 201 and Q via bypass 281
The branch target instruction code is loaded into the IN bus 251. After fetching the branch destination instruction code, the value obtained by incrementing the value of QINPC 204 (= branch destination address) by NC 205 is the CA bus again.
It is loaded into 252, which CAA 212 fetches and continues fetching subsequent instructions at the branch target address.

When the JSR instruction is decoded again by the instruction decoding unit 213, the address calculation unit 215 changes the instruction decoding unit 213.
From the A code 110, the instruction length of the JSR instruction is received, and the head address of the JSR instruction is received from the PC operation unit 214. Then, the address calculation unit 215 calculates the address of the next instruction (return destination instruction) of the JSR instruction from the instruction length of the JSR instruction and the start address of the JSR instruction to calculate the address of the AO bus.
Load it on 254.

The return destination address loaded on the AO bus 254 is fetched by the FA 218. Further, the RCC 304 receives the subroutine jump instruction (JSR) detection signal 286 from the instruction decoding unit 213 and counts up its own count value. In this case, the count value becomes "2" because two JSR instructions are decoded. On the other hand, the return address fetched by the FA 218 is saved in the RAS 301 according to the value of the RAS write pointer 302. RAS write pointer 302
Is controlled by the detection counter 304, so the pointer is advanced by one. After that, the operation of processing the normal instruction according to the branch destination instruction fetched by the IF stage 101 is continued.

In the IF stage 101, the branch destination instruction is, for example, 5
If an instruction is fetched, the fetch count control signal 290 is output from the INC 205 and given to the RCC 304.
If the count value is not "0", the RCC304 outputs the return fetch control signal 291 to the micro ROM 217. Upon receiving the return fetch control signal 291, the micro ROM 217 starts the fetch operation of the return destination instruction.

That is, by outputting the return address control signal 292 from the micro ROM 217, the RAS 301
The return destination address saved in is loaded from the RAS 301 to the CA bus 252 according to the value of the RAS read pointer 303. The CAA 212 switches the capture destination register from the value of QINPC 204 to the value of RAS 301. At this time, QINPC 204
The value of is kept as it is, and the fetch of the instruction is started from the value of QINPC 204 held again after the return address is fetched.

According to the return destination address loaded on the AA bus 258, the return destination instruction code is externally loaded onto the DD bus 250 and taken into the IIN 210. The return instruction code fetched in the IIN 201 is registered in the data memory 210 of the instruction cache without being fetched in the SELCT 202 under the control of the micro ROM 217. At this time, the entry registered in the data memory 210 is the entry designated by the index decoder 208 based on the values of the tag register 206 and the index register 207 which have fetched the return destination address loaded in the previous CA bus 252. After the return-destination instruction code is registered in the instruction cache, the value of QINPC 204 is loaded again to the CA bus, so CAA 212 fetches it and continues fetching sequential instructions.

Finally, the operation of the data processor of the third invention of the present invention when processing a return subroutine (RTS) instruction will be described. The value of QINPC 204 is INC 20 sequentially
Incremented according to 5, RTS instruction externally DD
Loaded onto bus 250 and taken into IIN 201. These are loaded into the QIN bus 251 via the instruction queue 203 after the input of the IIN 201 is selected by the SELCT 201 in the same manner as a normal instruction.

The RTS instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. When the RTS instruction is decoded in the instruction decoding unit 213, the RTS instruction detection signal
Output 293 to RCC 304. In the RCC 304, when the RTS instruction detection signal 293 is given, the count value is counted down and the return subroutine detection control signal 294 is output to the micro ROM 217.

In the micro ROM 217, the RTS detection control signal 29
When 4 is given, the return address control signal 292 is output, and the return destination address previously saved in RAS 301 is transferred to the CA bus according to the RAS read pointer 303.
Load it on the 252. The RAS read pointer 303 stores the entry when the return destination address was last loaded into the CA bus 252, and after the return destination address is loaded into the CA bus 252, the entry is changed according to the RCC 304.

The subsequent operation is similar to that of other jump instructions (JSR instruction etc.). That is, the return destination address loaded on the CA bus 252 is fetched into the CAA 212, QINPC 204, the tag register 206 and the index register 207 of the instruction cache. In the instruction cache, the address memory is searched according to the values of the tag register 206 and index register 207. Since the return destination instruction is registered in advance, the instruction cache always hits, and the return destination instruction code is BOUT 2 from the data memory corresponding to the entry.
It is output to 11. The SELCT 202 receives the hit signal of the instruction cache, selects the instruction code of BOUT 211, and loads it to the QIN bus 251 via the bypass 281.

After that, the succeeding instruction of the return destination instruction is QINP.
The value obtained by incrementing the return address of C 204 with INC 205 is loaded to CA bus 252.
212 is fetched and the fetch is sequentially continued according to the value.

Again, the RTS instruction is externally loaded onto the DD bus 250 and taken into the IIN 201, and the SE instruction is executed in the same way as a normal instruction.
In LCT 201, the input is selected on the IIN 201 side and the instruction queue
It is loaded onto QIN bus 251 via 203.

The RTS instruction code loaded on the QIN bus 251 is fetched by the instruction decoding unit 213. When the RTS instruction is decoded in the instruction decoding unit 213, the RTS instruction detection signal
Output 293 to RCC 304. The RCC 304 counts down its own count value when the RTS instruction detection signal 293 is given, and outputs the return subroutine detection control signal 294 to the micro ROM 217.

Thereafter, the same operation as in the case where the above return subroutine is decoded is performed. As described above, in the data processing device of the third aspect of the present invention, the return destination address is stored and registered in the internal cache every time the subroutine jump instruction is decoded. Since the arithmetic processing time can be reduced and the return instruction can be returned at high speed, the pipeline processing can be efficiently performed.

[0123]

As described above, according to the data processor of the first aspect of the present invention, when the subroutine jump instruction is executed, the return destination instruction of the instruction is prefetched and already stored in the instruction storing means. Since the replacement with another instruction is prohibited, it is not necessary to fetch the indicated return destination instruction from the outside when executing the return subroutine instruction, so that the processing efficiency is improved.

According to the data processor of the second and third aspects of the present invention, since the return destination address is calculated and stored when the subroutine jump instruction is executed, the return subroutine instruction is fetched and decoded. Since the address calculation time is reduced compared to the conventional data processing device that calculates the return address after that,
A fast return from a return subroutine instruction is possible.

Even if the instruction subsequent to the jump destination instruction by the subroutine jump instruction is prefetched in the address order as in the conventional data processing device, the instruction at the address after the return subroutine instruction is wasted. Therefore, after fetching the branch destination instruction, the return destination instruction that is always executed is fetched and pre-registered in the internal cache to reduce unnecessary prefetching of instructions and enable fast return from a return subroutine instruction. ing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a specific internal configuration example of each pipeline processing stage of a data processing device according to a first aspect of the present invention.

FIG. 2 is a block diagram showing a specific internal configuration example of each pipeline processing stage of the data processing device of the first invention of the present invention.

FIG. 3 is a block diagram showing a specific internal configuration example of each pipeline processing stage of the data processing device of the second invention of the present invention.

FIG. 4 is a block diagram showing a specific internal configuration example of each pipeline processing stage of the data processing device of the second invention of the present invention.

FIG. 5 is a block diagram showing a specific internal configuration example of each pipeline processing stage of the data processing device of the third invention of the present invention.

FIG. 6 is a block diagram showing a specific internal configuration example of each pipeline processing stage of the data processing device of the third invention of the present invention.

FIG. 7 is a schematic diagram showing each stage of the pipeline when the pipeline processing of five stages is performed in the conventional microprocessor.

FIG. 8 is a block diagram showing a specific internal configuration example of each pipeline processing stage of a conventional data processing device.

FIG. 9 is a block diagram showing a specific internal configuration example of each pipeline processing stage of a conventional data processing device.

[Explanation of symbols] 203 Instruction queue 206 Tag register 207 Index register 209 Tag memory 210 Data memory 213 Instruction decoding unit 214 PC operation unit 215 Address calculation unit 216 Detection register 219 Address save register 226 Tag address comparator 227 Freeze bit 301 Address save Register 302 RAS write pointer 303 RAS read pointer 304 Detection counter

Claims (3)

[Claims] 1. An instruction fetch means for prefetching an instruction including a subroutine jump instruction for jumping from a main routine to a subroutine from outside, an instruction storage means for storing a plurality of instructions prefetched by the instruction fetch means, and the instruction storage means. Replacement control means for controlling replacement of an instruction stored in the instruction with a newly prefetched instruction, and instruction decoding for sequentially decoding the instructions stored in the instruction storage means and detecting that a subroutine jump instruction has been decoded Means, address calculating means for calculating a return destination address of the subroutine jump instruction when the instruction decoding means decodes the subroutine jump instruction, and Search means for searching whether the instruction of the return address calculated by the dress calculation means is stored in the instruction storage means, and the instruction of the return address calculated by the address calculation means as a result of the search by the search means When it is detected that the instruction is stored in the instruction storage means, the data processing device is provided with a replacement prohibition means for prohibiting replacement of the instruction by the replacement control means. 2. A data processing device for processing an instruction by a pipeline processing mechanism, wherein an instruction including a subroutine jump instruction for jumping from a main routine to a subroutine and a return subroutine instruction for returning from the subroutine to the main routine is prefetched from the outside. Instruction fetch means, instruction fetch means for prefetching instructions from the outside, instruction storage means for storing a plurality of instructions prefetched by the instruction fetch means, and sequentially decoding the instructions stored in the instruction storage means, Subroutine jump instruction and return Instruction decoding means for detecting decoding of the subroutine instruction, and return of the subroutine jump instruction when the instruction decoding means decodes the subroutine jump instruction An address calculation means for calculating an address and an address storage means for storing the return destination address calculated by the address calculation means are provided, and when the instruction decoding means detects that the subroutine jump instruction is decoded, the address calculation means The address storage means stores the return destination address calculated by the above, and the instruction fetch means does not fetch the instruction of the return destination address stored in the address storage means from the outside and store it in the instruction storage means. When the instruction decoding unit detects that the return subroutine instruction has been decoded, the return destination address stored in the address storage unit is read to the instruction storage unit, and the corresponding return destination instruction is From the instruction storage means, the instruction decoding The data processing apparatus characterized by are none to be output to the unit. 3. A data processing device for processing an instruction by a pipeline processing mechanism, wherein an instruction including a subroutine jump instruction for jumping from a main routine to a subroutine and a return subroutine instruction for returning from the subroutine to the main routine is prefetched from the outside. Instruction fetch means, instruction fetch means for prefetching instructions from the outside, instruction storage means for storing a plurality of instructions prefetched by the instruction fetch means, and sequentially decoding the instructions stored in the instruction storage means, Subroutine jump instruction and return Instruction decoding means for detecting decoding of the subroutine instruction, and return of the subroutine jump instruction when the instruction decoding means decodes the subroutine jump instruction The address calculation means for calculating the address, the address storage means for storing a plurality of return destination addresses calculated by the address calculation means, and the order of writing the addresses to the address storage means are the order of detection of the subroutine jump instruction by the instruction decoding means. Write control means for controlling the address read means from the address storage means according to the detection order of the subroutine jump instruction by the instruction decoding means, and the instruction decoding means executes the subroutine jump instruction. When it is detected that the address has been decoded, the return destination address calculated by the address calculation means is stored in the address storage means under the control of the write control means, and the instruction fetch means is stored in the address storage means. The instruction of the stored return destination address is fetched from the outside and stored in the instruction storage means, and stored in the address storage means when the instruction decoding means detects that the return subroutine instruction is decoded. The return destination address is read out to the instruction storage means under the control of the read control means, and a corresponding return destination instruction is output from the instruction storage means to the instruction decoding means. Data processing device.