JPH06189338A - Still video equipment - Google Patents

Abstract

PURPOSE:To record a high definition picture signal and a standard picture signal with same equipment. CONSTITUTION:A recording system of the still video equipment 1 has a magnetic disk driver 2, a system control circuit 10, low pass filters 11, 21, a memory control circuit 12, synchronizing signal generating circuits 13, 18, clock generating circuits 14, 19, an A/D converter 15, a memory 16, a frequency divider 17 and a D/A converter 20, and also has a synchronizing signal addition means 22, a recording processing circuit 24A, a C signal recording processing circuit 24B, an ID recording processing circuit 25, an adder 26, a recording amplifier 27, and changeover switches 23, 51-55 or the like. In the case of recording, the system of the inputted picture signal is discriminated and the recording processing system is selected depending on the system and then a picture signal is stored in and read from memories 16A-16C in a prescribed recording system and FM-modulated and recorded on a magnetic disk 3 by a magnetic head 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still video device for recording or reproducing image signals.

[0002]

2. Description of the Related Art In recent years, various recording / reproducing devices for recording and / or reproducing image, voice or other information have been developed and have become popular. Among these, the still video camera is a device capable of recording a captured image on a magnetic disk together with various information relating to the image and reproducing the captured image as a still image if necessary.

In this still video camera, a subject image is photoelectrically converted by a solid-state image pickup device to obtain a luminance signal and a color difference signal, these signals are FM-modulated and combined into a multiple image signal, and this image signal is rotated. The method of recording on the track of a magnetic disk is used. Further, ID data signals regarding field recording / frame recording, track number, shooting date, etc. are set to DPSK (Differential Pha).
se Sift Keying) and is recorded on a magnetic disk by superimposing it on the image signal by a frequency multiplexing method.

When reproducing the image signal recorded on the magnetic disk, the sampling pulse generated by the FM demodulated luminance signal and chrominance signal based on the vertical and horizontal synchronizing signals extracted from the luminance signal, respectively. According to the above, it is temporarily stored in a memory as digital data, read out according to a predetermined reference clock, converted into an analog signal, and then output to a video output terminal through an output circuit.

In a still video device typified by such a still video camera, when recording image signals of various television systems on a magnetic disk, recording is performed according to the system of image signals input to the still video device. It is necessary to change the processing method.

For example, when the input image signal is a standard TV signal (standard image signal) such as an NTSC signal, the screen is not divided and the time axis is not expanded, and the luminance signal and the line-sequential color difference are obtained. It is recorded by a recording processing method in which a signal and a signal are recorded on the same track in an overlapping manner.

When the input image signal is an HDTV signal (high-definition image signal) such as a high-definition signal, the recording band is insufficient in the above-described recording processing method, and therefore an image cannot be recorded. Therefore, for example, the image signal corresponding to one screen is divided into a plurality of tracks, and the time axis is expanded and recorded. With such a recording processing method, the frequency band of the image signal that can be recorded is substantially expanded, so that it is possible to record an image with high definition.

However, there is no still video device capable of selecting a desired recording processing method from the above two kinds of recording processing methods. Therefore, in order to record a standard image signal and a high definition image signal, Since a device for recording the standard image signal and a device for recording the high-definition image signal must be prepared and the two types of devices must be used properly according to the image signal to be recorded, the burden on the operator was large. .

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a still video device capable of switching the recording processing system depending on the system of the image signal.

[0010]

The above objects are achieved by the present invention described in (1) to (10) below.

(1) A still video device having a recording system for recording an image signal corresponding to one screen on a recording medium, wherein the recording system is in accordance with a system of the image signal input to the recording system. A still video device having a recording mode switching means for switching a recording processing system.

(2) The recording mode switching means switches the recording processing method to a recording processing method for recording a standard image signal or a recording processing method for recording a high definition image signal. Still video device according to item 1.

(3) The image signal is composed of a luminance signal and a color difference signal, and in the recording processing method for recording the high definition image signal, the luminance signal and the color difference signal are respectively recorded on a recording medium. The still video device according to (2) above, which records on a plurality of tracks separately.

(4) The still video device according to any one of (1) to (3), wherein the recording mode switching means is configured to be operated by an artificial operation.

(5) The recording mode switching means is configured to discriminate a method of an image signal input to the recording system and automatically operate according to the method of the image signal. A still video device according to any one of (3) to (3).

(6) The still video device according to (5), wherein the method of the image signal is discriminated by measuring a synchronizing signal of the image signal.

(7) A still video device having a reproducing system for reproducing an image signal corresponding to one screen recorded on a recording medium, wherein the reproducing system reproduces according to a recording processing system of the image signal. A still video device having a reproduction mode switching means for switching a processing method.

(8) The reproduction mode switching means switches the reproduction processing method to a reproduction processing method for reproducing a standard image signal or a reproduction processing method for reproducing a high definition image signal. Still video device according to item 1.

(9) The still video device according to (7) or (8), wherein the reproduction mode switching means is configured to operate by an artificial operation.

(10) In the above-mentioned (7) or (8), the reproduction mode switching means is configured to discriminate a recording processing method of the image signal and automatically operate according to the recording processing method. Still video device as described.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The still video apparatus of the present invention will be described in detail below with reference to the preferred embodiments shown in the accompanying drawings. FIG. 1 is a block diagram showing a configuration example of a recording system of a still video device of the present invention. As shown in the figure, the still video device 1
Has a system control circuit 10 for controlling various functions of the still video device described later. The system control circuit 10 is usually composed of a microcomputer.

A magnetic disk drive mechanism 2 is installed in the still video device 1. The magnetic disk drive mechanism 2 has a spindle motor 5 that can rotate at high speed, and the rotation of the spindle motor 5 supplies a motor drive circuit 4 that supplies electric power to the spindle motor 5 to drive it.
It is controlled by the system control circuit 10 which controls the operation of the circuit 4.

The magnetic disk drive mechanism 2 is loaded with a magnetic disk 3 as a recording medium for recording images to be photographed, sounds, various data relating to the images, etc., for example, in a state of being housed in a case. The magnetic disk 3 is formed by forming a magnetic layer on the surface of a circular sheet material.
(Circular) tracks are concentrically formed. Also,
The center of the magnetic disk 3 is structured so as to fit into the rotary shaft of the spindle motor 5, and during recording and reproduction, the magnetic disk 3 is driven by the spindle motor 5 at a constant speed (3600 rpm for NTSC system, PAL).
In the case of the method, it is rotated at 3000 rpm).

A predetermined number of FG pulses corresponding to the number of rotations of the spindle motor 5 are output from the spindle motor 5, and one rotation of the magnetic disk 3 is started from the center of the magnetic disk 3 set on the rotation shaft of the spindle motor 5. 1 for each
One PG pulse is output. System control circuit 10
The spindle motor 5 based on these pulse signals.
Is controlled to rotate the magnetic disk 3 at a constant speed during recording and reproduction.

Further, the magnetic disk drive mechanism 2 includes
A magnetic head 6 is installed. This magnetic head 6
A stepping motor (not shown) moves the magnetic disk 3 in the radial direction continuously or intermittently (intermittently). That is, at the time of recording and reproducing, the stepping motor is driven to move the magnetic head 6 onto a predetermined track of the magnetic disk 3, and at the time of reproducing, the magnetic head 6 is placed at an appropriate position on the track and the maximum. The automatic tracking is performed to finely adjust the position of the magnetic head 6 so that the output of

The tracking drive circuit 7 controls the moving amount, moving speed and moving timing of the magnetic head 6. The operation of the tracking drive circuit 7 is controlled by the system control circuit 10.

An operation unit 8 is connected to the system control circuit 10. The operation unit 8 has, for example, a selection switch for selecting one of field recording and frame recording, a head feed switch for moving the magnetic head 6 to a predetermined track of the magnetic disk 3, and recording an image signal on the magnetic disk 3. A Rec switch for deleting, an erasing switch for erasing the image signal recorded on the magnetic disk 3 and the like (none of which are shown) are installed as necessary. Further, in the case of a still video device having both a recording system and a reproduction system, the operation unit 8 is also provided with a switch (not shown) for selecting either recording or reproduction.

A display unit (not shown) is connected to the system control circuit 10. Information such as field recording / frame recording, normal (standard image) / high-definition image related to a recording processing method to be described later, track number, presence / absence of recording of track, date of photographing, etc. is displayed on the display unit. , Necessary information on whether or not the magnetic disk 3 is loaded, information on the power source, information on flash light emission, current time, etc. are displayed by, for example, a liquid crystal or a light emitting element. Further, in the case of a still video device having both a recording system and a reproducing system, the display section also displays whether recording or reproducing.

When the still video device is a still video camera, it has an image pickup unit (not shown). This image pickup unit is composed of a lens system, an aperture stop, a mirror, an optical filter, a shutter, a solid-state image pickup device (CCD), etc. (not shown). When the shutter is opened, the image of the subject passes through the lens system, etc.
Image on top. The CCD may be either a black-and-white image or a color image, but in this embodiment, a color image will be described.

The CCD photoelectrically converts the formed image and outputs color signals (R, G, B). These color signals are amplified by an amplifier (not shown), and further, a luminance signal (Y) is obtained by a process / matrix circuit (not shown).
And two color difference signals (RY, BY).
Further, for the luminance signal, a horizontal and vertical synchronizing signal (S) corresponding to the standard image signal is generated by a synchronizing signal generating circuit (not shown)
Alternatively, horizontal and vertical synchronizing signals ( _SH ) corresponding to high definition image signals are added and output as a luminance signal (Y + S) or a luminance signal (Y + _SH ). In the case of a high-definition signal, the horizontal and vertical sync signals ( _SH ) are added to the two color difference signals (RY, BY), respectively. If the still video device does not have an image pickup unit, these signals are input from the external input terminal.

In this case, the still video device 1 of this embodiment is used.
Is a recording processing method for recording a standard image signal (standard TV signal) (hereinafter, referred to as a normal recording mode) and a high definition image according to the method of the image signal input to the recording system. The recording processing system for recording a signal (HDTV signal) (hereinafter, referred to as a high-definition recording mode) is switched to any one. In the following, description will be made for different cases. The recording mode switching means for switching the recording processing method and the operating method of the recording mode switching means will be described later.

[High-definition recording mode] In the high-definition recording mode, the terminals h of the changeover switches 51, 52, 53, 54 and 55 forming part of the recording mode switching means shown in FIG. Become. The terminal n of the changeover switch 52 is grounded, and the changeover switches 53, 54 and 5 are connected.
Each terminal h of 5 is grounded. The change-over switches 51 to 55 are connected to the system control circuit 10 respectively.
Controlled by.

As shown in FIG. 1, as an HDTV signal,
For example, when a high-definition signal is input, the luminance signal (Y + S _H ) passes through the low-pass filter 11A and is cut in a high range that may be noise (folding noise due to sampling). From the luminance signal (Y + S _H ), the horizontal and vertical synchronization signals (S _H ) are separated and extracted by the synchronization signal separation circuit 13 and input to the clock generation circuit 14. The clock generation circuit 14 generates a memory write clock signal that serves as a reference for writing to each memory, and the memory write clock signal is input to the memory control circuit 12 and the A / D converter 15A.

The luminance signal (Y) from which the horizontal and vertical synchronizing signals ( _SH ) have been separated is converted into a digital signal by the A / D converter 15A and temporarily stored in the Y memory 16A. The color difference signal (RY) (hereinafter referred to as the color difference signal (Pr)) is passed through the low-pass filter 11B and then A /
It is converted into a digital signal by the D converter 15B and temporarily stored in the Pr memory 16B. Similarly, the color-difference signal (BY) (hereinafter referred to as the color-difference signal (Pb)) passes through the low-pass filter 11C and then the A / D converter 16
Converted to digital signal by C, Pb memory 16C
Is temporarily stored in.

The memory control circuit 12 performs the following control on the basis of the memory write clock signal from the clock generation circuit 14 while timing the writing to each of the memories 16A to 16C. That is, based on the memory write clock signal from the clock generation circuit 14, A
As the / D converter 15A operates, the memory control circuit 12 operates the built-in write address counter to write the digital data of the luminance signal (Y) at a predetermined address of the Y memory 16A.

Further, the memory write clock signal from the clock generation circuit 14 is divided into 1/2 by the frequency divider 17A to activate the A / D converters 15B and 15C, and the memory control circuit 12 The built-in write address counter is activated to activate the Pr memory 16
The digital data of the color difference signal (Pr) and the color difference signal (Pb) are written in predetermined addresses of the B and Pb memories 16C, respectively. The synchronization signal ( _SH ) included in the input signal such as the luminance signal is not sampled and therefore is not written in the memory.

From the sync signal generating circuit 18, for example, NT
Horizontal and vertical synchronization signals (S) according to the SC system are output and input to the clock generation circuit 19. The clock generation circuit 19 generates a memory read clock signal which serves as a reference for reading from each memory, and the memory read clock signal is used as the memory control circuit 12 and the D / A.
Input to the converters 20A, 20B and 20C, respectively.

The memory control circuit 12 performs the following control on the basis of the memory read clock signal from the clock generation circuit 19 while timing the reading from each of the memories 16A to 16C. That is, based on the memory read clock signal from the clock generation circuit 19,
The memory control circuit 12 operates the read address counter incorporated therein to read the digital data of the luminance signal (Y) from a predetermined address of the Y memory 16A, and at the same time, the D / A converter 20A operates to read the data. The converted digital signal of the luminance signal (Y) is converted into an analog signal.

Further, based on the memory read clock signal from the clock generation circuit 19, the memory control circuit 12
Activates the built-in write address counter to read out the digital data of the color difference signal (Pr) and the color difference signal (Pb) from the predetermined addresses of the Pr memory 16B and the Pb memory 16C, respectively, and
The / A converters 20B and 20C operate to convert the read digital signal of each color difference signal into an analog signal.

In the memory control circuit 12, the mode switching between the memory writing control and the memory reading control is controlled by a mode switching command signal from the system control circuit 10. The horizontal and vertical sync signals ( _SH ) from the sync signal separation circuit 13 and the horizontal and vertical sync signals (S) from the sync signal generation circuit 18 are also input to the system control circuit 10, respectively. It is used as a timing signal for controlling the rotation phase of the spindle motor 5 on the basis of the above, and for other various operations.

In the case of recording such a high-definition image, the memory read clock signal from the clock generation circuit 19 has a smaller frequency than the memory write clock signal from the clock generation circuit 14, for example, 1/4. Has a frequency of. Therefore, the frequency of the read clock signal of the luminance signal is 1/4 of the frequency of the write clock signal, and the frequency of the read clock signal of both color difference signals is 1/2 of the frequency of the write clock signal. Thus, compared with the signal input to the recording system, the signal is expanded in the time axis and recorded.

The luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb), which are analog signals, are respectively
After the high frequency band is cut by the low pass filters 21A, 21B and 21C, the synchronizing signal adding circuits 22A, 22
Vertical and horizontal synchronizing signals (S) from the synchronizing signal generating circuit 18 are added by B and 22C.

Sync signal adding circuits 22A, 22B and 2
Terminals a, b and c of the changeover switch 23 are connected to 2C, respectively. The system control circuit 10 controls the switching of the terminals a, b, and c connected in the changeover switch 23, and sequentially outputs the luminance signal (Y + S), the color difference signal (Pr + S), and the color difference signal (Pb + S) to the recording processing circuit 24A. input. In the recording processing circuit 24A,
Each input signal is FM-modulated.

From the system control circuit 10, field recording / frame recording, field number in the case of frame recording, normal recording / high-definition recording, type of image signal to be recorded, that is, luminance signal (Y + S) / Color-difference signal (Pr + S) / color-difference signal (Pb + S), a component of one screen (for example, in the case of 4-division, upper left / lower left / upper right / lower right of the screen), track number, shooting year ID data signal related to image information such as date is output,
The ID recording processing circuit 25 DPSK-modulates a carrier (carrier wave) generated based on the horizontal synchronizing signal (S) from the synchronizing signal generating circuit 18 based on the ID data signal to obtain a DPSK signal.

The DPSK signal for this ID data is
The adder 26 synthesizes the FM-modulated image signal in the recording processing circuit 24. The image signal synthesized by the adder 26 is amplified by the recording amplifier 27 controlled by the system control circuit 10 and recorded by the magnetic head 6 on a predetermined track of the rotating magnetic disk 3.

In recording a high-definition image, since the image signal corresponding to one screen is divided into a plurality of tracks and expanded on the time axis and recorded, the data is stored in each of the memories 16A to 16C as follows. It will be divided.

FIG. 3 is a schematic diagram showing an example of a storage area pattern of image signals in the memories 16A to 16C. In the example shown in this figure, an image signal is recorded in a frame recording mode, and a luminance signal (Y) and a color difference signal (Pr) are recorded.
And a color difference signal (Pb) are recorded on a plurality of tracks. That is, one screen is composed of the first field and the second field, the luminance signal (Y) is divided into four for one screen, and the color difference signal (Pr) and the color difference signal (Pb) are each divided into two for one screen. Corresponding memories 16A-16
Stored in C. Note that FIG. 3 shows the arrangement of the storage area of the image signal in the memory and also corresponds to the configuration of the screen (still image) displayed on the display.

Regarding the luminance signal (Y), the screen has center lines E and F extending in the horizontal and vertical directions, respectively.
In the first field, the luminance signal Y ₁ corresponding to the upper left, the luminance signal Y ₂ corresponding to the upper right, the luminance signal Y ₃ corresponding to the lower left and the luminance signal Y ₄ corresponding to the lower right are respectively divided in the first field. , Y memory 16A in the first area, the second area, the third area, and the fourth area.

Regarding the color difference signal (Pr), the screen is divided into two by a center line G extending in the horizontal direction, and in the first field, the color difference signal Pr ₁ corresponding to the upper half and the color difference signal Pr corresponding to the lower half thereof. ₂ is stored in the fifth area and the sixth area of the Pr memory 16B, respectively.

Regarding the color difference signal (Pb), the screen is divided into two by a center line G extending in the horizontal direction, and in the first field, the color difference signal Pb ₁ corresponding to the upper half and the color difference signal Pb corresponding to the lower half thereof. ₂ is stored in the seventh area and the eighth area of the Pb memory 16C, respectively.

Similarly for the second field, the luminance signals Y ₅ , corresponding to the upper left, upper right, lower left and lower right of the screen,
Y ₆ , Y ₇ and Y ₈ are respectively the Y memory 16A.
Of the color difference signals Pr ₃ and Pr ₄ stored in the ninth, tenth, eleventh and twelfth areas of the screen of FIG.
The color difference signals Pb ₃ and Pb ₄ stored in the 13th and 14th areas of the
The 15th area and the 1st area of the Pb memory 16C, respectively.
It is stored in 6 areas.

FIG. 4 is a diagram showing an example of a track pattern formed on the magnetic disk 3. As shown in the figure, the above-mentioned image signals are recorded on 16 tracks which are continuously arranged in the radial direction of the magnetic disk 3. in this case,
The image signals belonging to the first field are recorded on eight consecutive tracks, and the image signals belonging to the second field are recorded on the other eight consecutive tracks. In the configuration shown, from the outer peripheral side of the magnetic disk 3 to the inner peripheral side,
Luminance signals Y ₁ , Y ₂ , Y ₃ , Y _{4 of} the first field, color difference signals Pr ₁ , Pr ₂ , color difference signals Pb ₁ , Pb ₂ , second
Field of the luminance signal _{Y 5, Y 6, Y 7} , Y 8, the color difference signals Pr _3, Pr _4, is continuously recorded by one track in the order of the color difference signals Pb _3, Pb _4.

FIG. 5 is a time chart showing the relationship between the luminance signal (Y) input to the recording system of the still video device and the luminance signal (Y) recorded on the track when recording a high definition image. . One screen is composed of the first field and the second field, of which FIG.
Shows the luminance signal of the first field. The luminance signal of the first field is composed of a large number of horizontal scanning lines H, and the luminance signal corresponding to one horizontal scanning line H is between two adjacent horizontal synchronizing signals S _Hh (hereinafter referred to as horizontal Exists in the synchronization period).

When recording the luminance signal, the changeover switch 2
The terminal a of 3 is brought into the connected state, and the magnetic head 6 is sequentially moved from the first track to the fourth track on the outer peripheral side of the magnetic disk 3. That is, when recording the luminance signal Y ₁ ,
When the magnetic head 6 records the luminance signal Y ₂ on the first track, the magnetic head 6 records on the second track, and when recording the luminance signal Y ₃ , the magnetic head 6 records on the third track. At the time of recording the luminance signal Y ₄ , the magnetic head 6 moves to the fourth position.
Recording is performed by moving to each track (see FIG. 4). Here, the Nth track does not mean the Nth track from the outermost periphery of the magnetic disk 3, but
It means a relative track number based on an arbitrary track.

As shown in FIG. 5, the frequency band of the luminance signals Y _{1 to} Y ₄ when written in the Y memory 16A is f.
When _H, to be extended 4 times longer when read from Y memory 16A, the frequency band of the luminance signal Y ₁ to Y ₄ to be recorded in the first through fourth track becomes f _H / 4. Due to the characteristics of the magnetic disk 3, the recordable band is limited. However, with such a configuration, it is possible to practically record a luminance signal in a band higher than that, and it is possible to record a high-definition image. It

FIG. 6 shows a color difference signal (Pr) input to the recording system of a still video device in recording a high definition image.
2 is a time chart showing the relationship between the color difference signal (Pr) recorded on the track. One screen is composed of the first field and the second field, of which,
FIG. 6 shows the color difference signal (Pr) of the first field. The color difference signal of the first field is composed of a large number of horizontal scanning lines H, and a color difference signal corresponding to one horizontal scanning line H exists within one horizontal synchronization period.

At the time of recording the color difference signal (Pr), the terminal b of the changeover switch 23 is brought into the connected state, the magnetic head 6 is sequentially moved to the fifth track and the sixth track, and the color difference signal Pr is accordingly recorded. ₁ is recorded on the fifth track, and the color difference signal Pr ₂ is recorded on the sixth track (see FIG. 4).

As shown in FIG. 6, the frequency band of the color difference signals Pr ₁ and Pr ₂ when written in the Pr memory 16B is f _H / 2, which is doubled in time when read from the Pr memory 16B. Therefore, the fifth and sixth
The frequency band of the color difference signals Pr ₁ and Pr ₂ recorded on the track is f _H / 4. Due to the characteristics of the magnetic disk 3, the band that can be recorded is limited. However, with such a configuration, it is possible to substantially record color difference signals in a band higher than that, and it is possible to record a high-definition image. It

At the time of recording the color difference signal (Pb), the terminal c of the changeover switch 23 is brought into the connected state, the magnetic head 6 moves to the seventh track and the eighth track, and although not shown, the color difference signal ( Pr), the color difference signal Pb ₁
Is recorded on the seventh track in the band of f _H / 4, and the color difference signal Pb ₂ is recorded on the eighth track in the band of f _H / 4.

Luminance signals Y _{5 to} Y in the second field
_8. The recording of the color difference signals Pr ₃ , Pr ₄ , Pb ₃ and Pb ₄ is the same as in the first field and is recorded on the (N + 8) th track (N = 1 to 8), respectively (FIG. 4). reference). The sync signal recorded on the magnetic disk 3 is not the sync signal ( _SH ) for high definition images, but is replaced with the sync signal (S) conforming to the NTSC system, for example. In this case, FIGS.
Only the horizontal sync signal _Sh is shown respectively.

[Normal Recording Mode] In the case of the normal recording mode, the changeover switches 51, 52, 53, 54 and 5 forming a part of the recording mode switching means shown in FIG.
The terminal n of 5 is connected. As shown in FIG. 1, as a standard TV signal, for example, composite video (NTS) is used.
When the C) signal is input, the decoder 46 causes the luminance signal (Y + S), the color difference signal (Pr), and the color difference signal (P
b) and separated.

The separated luminance signal (Y + S) passes through the low-pass filter 11A and is cut in a high frequency range which may be noise (aliasing noise due to sampling).
From the luminance signal (Y + S), the synchronization signal separation circuit 13
Thus, the horizontal and vertical sync signals (S) are separated and extracted, and input to the clock generation circuit 14. The clock generation circuit 14 generates a memory write clock signal that serves as a reference for writing to each memory, and the memory write clock signal is input to the memory control circuit 12 and the A / D converter 15A.

The luminance signal (Y) from which the horizontal and vertical synchronizing signals (S) have been separated is converted into a digital signal by the A / D converter 15A and temporarily stored in the Y memory 16A. The color difference signal (Pr) is converted into a digital signal by the A / D converter 15B after passing through the low-pass filter 11B, and is temporarily stored in the Pr memory 16B. Similarly, the color difference signal (Pb) is output to the low-pass filter 1
After passing 1C, it is converted into a digital signal by the A / D converter 16C and temporarily stored in the Pb memory 16C.

The memory control circuit 12 performs the following control on the basis of the memory write clock signal from the clock generation circuit 14 while timing the writing to each of the memories 16A to 16C. That is, based on the memory write clock signal from the clock generation circuit 14, A
As the / D converter 15A operates, the memory control circuit 12 operates the built-in write address counter to write the digital data of the luminance signal (Y) at a predetermined address of the Y memory 16A.

Further, the memory write clock signal from the clock generation circuit 14 is divided into 1/2 by the frequency divider 17A to activate the A / D converters 15B and 15C, and the memory control circuit 12 The built-in write address counter is activated to activate the Pr memory 16
The digital data of the color difference signal (Pr) and the color difference signal (Pb) are written in predetermined addresses of the B and Pb memories 16C, respectively. The synchronization signal (S) included in the input signal such as the luminance signal is not sampled,
Therefore, it is not written to the memory.

From the synchronizing signal generating circuit 18, for example, NT
Horizontal and vertical synchronization signals (S) according to the SC system are output and input to the clock generation circuit 19. The clock generation circuit 19 generates a memory read clock signal which serves as a reference for reading from each memory, and the memory read clock signal is used as the memory control circuit 12 and the D / A.
Input to the converters 20A, 20B and 20C, respectively.

The memory control circuit 12 performs the following control on the basis of the memory read clock signal from the clock generation circuit 19 while taking the timing of reading from the memories 16A to 16C.

That is, based on the memory read clock signal from the clock generation circuit 19, the memory control circuit 12 operates the read address counter incorporated therein to output the luminance signal (Y) from a predetermined address of the Y memory 16A. D / A while reading digital data
The converter 20A operates to read the luminance signal (Y)
The digital signal of is converted into an analog signal.

Further, based on the memory read clock signal from the clock generation circuit 19, the memory control circuit 12
Activates the built-in write address counter to read the digital data of the color difference signal (Pr) and the color difference signal (Pb) from the predetermined addresses of the Pr memory 16B and the Pb memory 16C, respectively. The memory read clock signal is frequency-divided by the frequency divider 17B into 1/2, and the D / A converters 20B and 20C are operated to convert the read digital signals of the respective color difference signals into analog signals.

In the memory control circuit 12, the mode switching between the memory write control and the memory read control is controlled by a mode switch command signal from the system control circuit 10. The horizontal and vertical sync signals (S) from the sync signal separation circuit 13 and the horizontal and vertical sync signals (S) from the sync signal generation circuit 18 are also input to the system control circuit 10, respectively. Based on this, the rotation phase of the spindle motor 5 is controlled, and it is also used as a timing signal for various other operations.

In the case of recording such a standard image, the memory read clock signal from the clock generation circuit 19 and the memory write clock signal from the clock generation circuit 14 have the same frequency. Therefore, the frequency of the read clock signal of the luminance signal and the frequency of the write clock signal are the same, the frequency of the read clock signal of both color difference signals and the frequency of the write clock signal are the same, The frequency of the write and read clock signals is twice the frequency of the write and read clock signals of both color difference signals.

The luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb), which are analog signals, are respectively
The high frequency band is cut by the low pass filters 21A, 21B and 21C, and then the vertical and horizontal synchronizing signals (S) from the synchronizing signal generating circuit 18 are added to the luminance signal (Y) by the synchronizing signal adding circuit 22A. It

The terminal a of the changeover switch 23 is in a connected state, and the luminance signal (Y + S) is input to the recording processing circuit 24A via the changeover switch 23 and FM-modulated. Further, the terminal n of the changeover switch 53 is connected to the synchronizing signal adding circuit 22B, the terminal n of the changing switch 54 is connected to the synchronizing signal adding circuit 22C, and the color difference signal (Pr) and the color difference signal (Pb) are , And is input to the C signal recording processing circuit 24B via the changeover switches 53 and 54, respectively. The input color difference signal (Pr) and color difference signal (Pb) are processed by the C signal recording processing circuit 24B.
It is line-sequentialized and FM-modulated, and is input to the adder 26 via the changeover switch 55.

Also, various ID data signals are output from the system control circuit 10 as in the case of the high definition recording mode, and the ID recording processing circuit 25 causes the horizontal synchronizing signal ( A carrier (carrier wave) generated based on S) is DPSK-modulated based on the ID data signal to obtain a DPSK signal.

A DPSK signal relating to this ID data,
The FM-modulated luminance signal (Y + S) and the line-sequential and FM-modulated color difference signals (Pr, Pb) are added by the adder 2
Synthesized by 6. The image signal synthesized by the adder 26 is amplified by the recording amplifier 27 controlled by the system control circuit 10 and recorded by the magnetic head 6 on a predetermined track of the rotating magnetic disk 3.

In this case, in the case of field recording, 1
The image signal corresponding to the screen is recorded on one track, and in the case of frame recording, the image signal for one field is recorded on one track (the image signal corresponding to one screen is recorded on two tracks).

Next, the recording mode switching means for switching to the above-mentioned high definition recording mode or normal recording mode will be described. In this case, in the present embodiment, the recording mode switching means for measuring the synchronizing signal separated from the luminance signal and automatically switching the recording processing method based on the result will be described.

FIG. 7 is a circuit diagram of the sync signal separation circuit 13 shown in FIG.
It is a block diagram of. As shown in the figure, the luminance signal (Y +
The composite sync signal separation circuit 71 separates the composite sync signal (C.Sync) from the luminance signal (Y + S) of the S _H ) or NTSC signal. From this composite sync signal, a vertical sync signal separation circuit 72 outputs a vertical sync signal (V.Sync), and a horizontal sync signal separation circuit 73 outputs a horizontal sync signal (H.Sync).
Are separated from each other. The composite sync signal, the vertical sync signal, and the horizontal sync signal thus separated are input to the system control circuit 10, respectively, and
The horizontal synchronizing signal is also input to the clock generation circuit 14.

FIG. 8 shows the luminance signal input to the recording system,
It is a time chart which shows the relationship with the separated horizontal synchronizing signal and vertical synchronizing signal. For synchronous signal separated from the luminance signal of HDTV signal (Y + S _H), between leading edge of one of the S _Hv two adjacent vertical sync signal S _Hv to the rising of the other S _Hv (vertical synchronization period) In the case of a sync signal having 562 or 563 horizontal sync signals S _Hh and separated from the luminance signal (Y + S) of the NTSC signal, from the rising _edge of one of the two adjacent vertical sync signals S _v , between to rising of the other S _v, 262 or 263 amino horizontal synchronizing signal S _h is present.

In this embodiment, this difference is utilized, that is, by counting the number of horizontal synchronizing signals in the vertical synchronizing period, whether the image signal input to the recording system is a high-definition signal or an NTSC signal. Is discriminated by the system control circuit 10 and the recording mode switching means is automatically operated. The number of horizontal synchronizing signals is counted for the signal input to the recording system, and the switching of the recording processing method is completed before actually recording the image signal.

FIG. 9 is a flow chart showing the control operation of the system control circuit 10 when the recording mode switching means is automatically operated. The flowchart will be described below.

As shown in FIG. 9, the sync signal separation circuit 13
The pulses of the vertical synchronizing signal and the horizontal synchronizing signal are detected over time based on the synchronizing signal input to the system control circuit 10 and whether or not there is a vertical synchronizing signal.
That is, it is determined whether or not the pulse of the vertical synchronizing signal is currently input (step 101).

When it is determined in step 101 that the vertical synchronizing signal is present, that is, when it is determined that the pulse of the vertical synchronizing signal is currently input, the counter is set to N.
= 0 is set (step 102).

Next, it is judged whether or not there is a horizontal synchronizing signal, that is, whether or not a pulse of the horizontal synchronizing signal is currently input (step 103). In step 103,
When it is determined that the horizontal synchronizing signal is present, that is, when it is determined that the pulse of the horizontal synchronizing signal is currently input, the counter N is incremented by 1 (step 104).

When it is judged in step 103 that there is no horizontal synchronizing signal, and after step 104 is executed, it is determined whether or not there is a vertical synchronizing signal, that is, whether or not a pulse of the vertical synchronizing signal is currently input. A judgment is made (step 105).

If it is determined in step 105 that there is no vertical synchronization signal, the process returns to step 103, steps 103 to 105 are repeatedly executed, and if it is determined in step 105 that there is a vertical synchronization signal, N is returned. > 412 (≈ (1125/2 + 525/2) /
It is determined whether or not 2) (step 106).

If N> 412 is determined in step 106, the recording processing method is set to the high-definition recording mode,
That is, the recording processing method for recording the high-definition signal is switched to (step 107). If N ≦ 412 is determined in step 106, the recording processing system is switched to the normal recording mode, that is, the recording processing system for recording the NTSC signal (step 10).
8). In this way, a predetermined image signal is recorded after switching the recording processing method.

Next, in the judgment of step 106, in the case of N> 412 and N ≦ 412, respectively,
A control operation when the recording mode is switched by the recording mode switching means to record an image signal on the magnetic disk 3 will be described.

FIG. 10 shows that in step 106,
FIG. 11 is a flowchart showing a control operation when N> 412 is determined, that is, when recording is performed in the high-definition recording mode, and FIG.
4 is a flowchart showing a control operation when it is determined to be 412, that is, when recording is performed in the normal recording mode. As shown in FIG. 10, when recording is performed in the high-definition recording mode, the terminals h of the changeover switches 51 to 55 are set to the connected state (step 201).

Next, clock generation circuits 14 and 19
The clocks generated in step 2 are switched for high definition (step 202). In this case, the clock generation circuit 14
The frequency of the clock generated by
4 times the frequency of the clock generated in.

Next, the low-pass filters 11A-1
The cutoff frequency of 1C is switched to high definition (step 203). Specifically, each low-pass filter 11
Cutoff frequencies of A to 11C are set for each A / D converter 15A.
Set to 1/2 of the sampling frequency of ~ 15C.

Next, the low-pass filters 21A-2
The cutoff frequency of 1C is switched to high definition (step 204). Specifically, the low pass filter 21B
And the cutoff frequencies of 21C are set to 1/2 of the sampling frequencies of the D / A converters 20B and 20C, respectively.

By executing the steps 201 to 204, the cutoff frequency of each low-pass filter 11A to 11C, the sampling frequency of each A / D converter 15A to 15C, the writing frequency to each memory 16A to 16C, each memory 16A to Read frequency from 16C,
Sampling frequency of each D / A converter 20A to 20C,
The cutoff frequencies of the low-pass filters 21A to 21C are set as shown in Table 1 below.

[0094]

[Table 1]

After setting each frequency as shown in Table 1 above, the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) are stored in the respective memories 16A to 16C (step 205). Next, after the terminal a of the selection switch 23 is connected (step 206), the luminance signal (Y) stored in the Y memory 16A is read and recorded on a predetermined track of the magnetic disk 3 (step 2).
07).

Then, after the terminal b of the selection switch 23 is set to the connected state (step 208), the Pr memory 16B
The color difference signal (Pr) stored in is read and recorded on a predetermined track of the magnetic disk 3 (step 209).
Next, after the terminal c of the selection switch 23 is connected (step 210), the color difference signal (Pb) stored in the Pb memory 16C is read and recorded on a predetermined track of the magnetic disk 3 (step 211).

In this way, among the image signals for one screen, the image signals belonging to the first field are recorded on eight tracks, and the steps 206 to 211 are repeatedly executed, whereby the second field is recorded. The belonging image signal is recorded on the other eight tracks, and as a result, the image signal for one screen is recorded in the track pattern shown in FIG.

Further, as shown in FIG. 11, when recording in the normal recording mode, the changeover switches 51 to 5
The terminals n of 5 are connected to each other (step 30
1). Next, the clocks generated by the clock generation circuits 14 and 19 are switched to standard ones (step 302). In this case, the frequency of the clock generated by the clock generation circuit 14 is made the same as the frequency of the clock generated by the clock generation circuit 19.

Next, each of the low pass filters 11A-1
The cutoff frequency of 1C is switched to the standard one (step 303). Specifically, each low pass filter 11A
~ 11C cutoff frequency for each A / D converter 15A ~
It is set to 1/2 of the sampling frequency of 15C.

Next, the low-pass filters 21A-2
The cutoff frequency of 1C is switched to the standard one (step 304). Specifically, the cutoff frequencies of the low pass filters 21B and 21C are set to 1/2 of the sampling frequencies of the D / A converters 20B and 20C, respectively.

By executing the steps 301 to 304, the cutoff frequency of each low-pass filter 11A to 11C, the sampling frequency of each A / D converter 15A to 15C, the writing frequency to each memory 16A to 16C, each memory 16A to Read frequency from 16C,
Sampling frequency of each D / A converter 20A to 20C,
The cutoff frequencies of the low-pass filters 21A to 21C are set as shown in Table 2 below.

[0102]

[Table 2]

After setting the frequencies as shown in Table 2, the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) are stored in the memories 16A to 16C, respectively (step 305).

Next, after the terminal a of the selection switch 23 is set in the connected state (step 306), each memory 16A to
Luminance signal (Y) and color difference signal (Pr) stored in 16C
And the color difference signal (Pb) are read at the same time, and the luminance signal (Y) is subjected to predetermined recording processing (luminance signal recording processing) by the recording processing circuit 24A to obtain the color difference signal (Pr).
And the color difference signal (Pb) is subjected to a predetermined recording process (color difference signal recording process) by the C signal recording processing circuit 24B and recorded on a predetermined track of the magnetic disk 3 (step 307).

In this way, of the image signals for one screen, the image signal belonging to the first field is recorded on one track, and the image signal belonging to the second field is recorded on the other one.
Recorded on a book track.

FIG. 2 is a block diagram showing a configuration example of a reproduction system of the still video device of the present invention. In the still video device 1 shown in the figure, a magnetic disk drive mechanism 2 including a magnetic disk 3, a motor drive circuit 4, a spindle motor 5, a magnetic head 6 and a tracking drive circuit 7, an operation unit 8, a display unit ( (Not shown) and the system control circuit 10 are the same as those of the recording system shown in FIG.

The still video device 1 of this embodiment has a reproduction mode switching means for switching the reproduction processing system according to the recording processing system of the image signal recorded on the magnetic disk 3. The reproduction mode switching means determines the recording processing system based on, for example, ID data, and when recording in the normal recording mode, a standard image signal (standard TV
Signal) is switched to a reproduction processing method (hereinafter referred to as a normal reproduction mode) for reproducing a high-definition image signal (HDTV signal). It is configured to switch to a system (hereinafter, referred to as high definition reproduction mode). Hereinafter, the reproduction mode switching means will be described separately for each case.

As described above, the ID data includes various kinds of information. In the present embodiment, the ID data is based on the information about the recording processing method indicating normal recording / high-definition recording. Then, the recording processing method of the image signal is determined.

[High-definition reproduction mode] During reproduction, the magnetic head 6 is moved to the rotating magnetic disk 3 at a predetermined track on which an image signal corresponding to one still image is recorded.
That is, the image signal and the DPSK signal are sequentially read from each track by moving in a predetermined order on the 16 tracks shown in FIG.

In this case, in this embodiment, of the image signals recorded on the 16 tracks corresponding to one still image, the luminance signals Y ₁ to Reading Y ₄ and Y memory 3
9A, and then the color difference signals Pr ₁ and Pr recorded on the tracks adjacent to the inner circumference side are written.
₂ is read and written to the Pr memory 39B, and then the color difference signals Pb ₁ and Pb ₂ recorded on the tracks adjacent to the inner peripheral side of these are read and written to the Pb memory 39C to write to the first field. after regeneration of the belonging image signals is carried out analogously to this luminance signal Y ₅ to Y ₈ belonging to the second field, the reproduction of the color difference signals Pr _3, Pr _4, Pb ₃ and Pb _4.

The image signal and the like read by the magnetic head 6 is first amplified by the reproduction amplifier 30.
The luminance signal (Y + S), the color difference signal (Pr + S), and the color difference signal (Pb + S) respectively pass through a high-pass filter (not shown) and are input to the reproduction processing circuit 31A of the image signal and FM demodulated.

The read DPSK signal passes through a band pass filter (not shown) and is input to the ID reproduction processing circuit 32 where it is DPSK demodulated to reproduce the ID data. This ID data is input to the system control circuit 10. Then, the system control circuit 10
Based on the D data, the recording processing method of the image signal read by the magnetic head 6 is determined, and control is performed to switch the reproduction processing method to the high-definition reproduction mode.

In this case, the changeover switches 61, 62 and 63 forming a part of the reproduction mode changeover means shown in FIG.
Are respectively controlled by the system control circuit 10, and the terminal h is brought into a connected state. The terminal n of the changeover switch 63 is grounded.

An envelope detection circuit 33 is connected to the output side of the reproduction amplifier 30, and the envelope detection circuit 33 detects the envelope (envelope) of the reproduction signal read by the magnetic head 6, The envelope detection signal according to the above is output to the system control circuit 10. In the system control circuit 10, the tracking drive circuit 7 is controlled so that the output of the envelope detection signal becomes maximum, and the magnetic head 6 is automatically tracked. Such automatic tracking of the magnetic head 6,
By controlling the rotational phase of the spindle motor 5 described later, a good still image can be obtained.

The luminance signal (Y + S), the color difference signal (Pr + S), and the color difference signal (Pb + S), which have been FM-demodulated by the reproduction processing circuit 31A, pass through the low-pass filter 34A and are cut in the high frequency range. Then, the horizontal and vertical sync signals (S) are separated and extracted by the sync signal separation circuit 36 and input to the system control circuit 10 and the clock generation circuit 37, respectively. Horizontal and vertical sync signals (S) input to the system control circuit 10
Is used for reading ID data, for example. Further, the clock generation circuit 37 generates a memory write clock signal as a reference for writing to the memory, and the generated memory write clock signal is supplied to the A / D converter 38.
It is input to each of A and the memory control circuit 35.

The luminance signal (Y) demodulated by the FM and separated from the horizontal and vertical synchronizing signals (S) is converted into a digital signal by the A / D converter 38A, and the Y memory 39
It is temporarily stored in a predetermined address of A. FM demodulated,
The color difference signal (Pr) from which the horizontal and vertical sync signals (S) have been separated is converted into a digital signal by the A / D converter 38A, and is passed through the switch 61 to the Pr memory 39B.
Is temporarily stored in. Similarly, the color difference signal (Pb) is
It is converted into a digital signal by the A / D converter 38A and is temporarily stored in the Pb memory 39C via the switch 62.

[0117] The system control circuit 10, an image signal read by the magnetic head 6, the luminance signal Y ₁ to Y _8, the color difference signals Pr ₁ to PR _4, one in which one or the like of the color difference signals Pb ₁ ~Pb ₄ Is determined from the reproduced ID data, and the operation of the memory control circuit 35 is controlled based on this. Based on the memory write clock signal from the clock generation circuit 37, the memory control circuit 35 causes each memory 39A to
The following control is performed with the timing of writing to 39C.

That is, based on the memory write clock signal from the clock generation circuit 37, the A / D converter 38
When A operates, the memory control circuit 35 operates a built-in write address counter to write the digital data of the luminance signal (Y) to a predetermined address of the Y memory 16A.

Further, the memory control circuit 35 operates the built-in write address counter on the basis of the memory write clock signal from the clock generation circuit 37 to set the predetermined addresses in the Pr memory 39B and the Pb memory 39C, respectively. Digital data of the color difference signal (Pr) and the color difference signal (Pb) is written. In addition,
The synchronization signal (S) included in the reproduction signal such as the luminance signal is
It is not sampled and therefore not written to memory.

The synchronizing signal generating circuit 40 outputs horizontal and vertical synchronizing signals ( _SH ) corresponding to the high-definition image signal and inputs them to the clock generating circuit 41. The clock generation circuit 41 generates a memory read clock signal which serves as a reference for reading from each memory, and the memory read clock signal is used as a reference for the memory control circuit 35 and D / D.
It is input to each A converter 42A. Further, this memory read clock signal is divided into 1/2 by the frequency divider 43B and then inputted to the D / A converters 42B and 42C, respectively.

The memory control circuit 35 performs the following control on the basis of the memory read clock signal from the clock generation circuit 41 while taking the timing of reading from the memories 39A to 39C.

That is, on the basis of the memory read clock signal from the clock generation circuit 41, the memory control circuit 35 operates the read address counter incorporated therein to output the luminance signal (Y) from a predetermined address of the Y memory 39A. D / A while reading digital data
The converter 42A operates to read the luminance signal (Y)
The digital signal of is converted into an analog signal.

Further, based on the memory read clock signal from the clock generation circuit 41, the memory control circuit 35
Activates the built-in write address counter to read out the digital data of the color difference signal (Pr) and the color difference signal (Pb) from the predetermined addresses of the Pr memory 39B and the Pb memory 39C, respectively.
The / A converters 42B and 42C operate to convert the read digital signal of each color difference signal into an analog signal.

In the memory control circuit 35, mode switching between writing control and reading control of the memory is controlled by a mode switching command signal from the system control circuit 10. Also, the horizontal and vertical synchronizing signals from the synchronizing signal separation circuit 36 (S), the horizontal and vertical synchronizing signals from the synchronizing signal generating circuit 40 and (S _H), respectively, are also inputted to the system control circuit 10, which It is used as a timing signal for controlling the rotation phase of the spindle motor 5 on the basis of the above, and for other various operations.

In the case of reproducing such a high-definition image, the memory read clock signal from the clock generation circuit 41 has a larger frequency, for example, four times the memory write clock signal from the clock generation circuit 37. Have a frequency. Therefore, the frequency of the read clock signal of the luminance signal is four times the frequency of the write clock signal, and the frequency of the read clock signal of both color difference signals is twice the frequency of the write clock signal, which causes the magnetic Compared to the signal read by the head 6, the signal is compressed on the time axis and reproduced in the original state (state at the time of input to the recording system).

The luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb), which are analog signals, are respectively
After the high frequency band is cut by the low pass filters 44A, 44B and 44C, the synchronizing signal adding circuits 45A and 45
The vertical and horizontal synchronizing signals ( _SH ) from the synchronizing signal generating circuit 40 are added by B and 45C. The luminance signal (Y + _SH ) and the color difference signal (P
r + S _H ) and the color difference signal (Pb + S _H ) are output as video signals through output circuits (not shown),
The still image is played on the connected display.

[Normal reproduction mode] In reproduction, the magnetic head 6 is positioned on a predetermined track on which an image signal corresponding to one still image is recorded, with respect to the rotating magnetic disk 3, and each magnetic disk 6 is moved. The image signal and the DPSK signal are sequentially read from the track.

The image signal and the like read by the magnetic head 6 is first amplified by the reproduction amplifier 30.
The luminance signal (Y + S) passes through a high-pass filter (not shown) and is input to the image signal reproduction processing circuit 31A,
The FM-demodulated color-difference signals (Pr, Pb) pass through a low-pass filter (not shown) and the C-signal reproduction processing circuit 31.
It is input to B and FM demodulated.

The read DPSK signal passes through a band pass filter (not shown) and is input to the ID reproduction processing circuit 32 where it is DPSK demodulated to reproduce the ID data. This ID data is input to the system control circuit 10. Then, the system control circuit 10
Based on the D data, the recording processing method of the image signal read by the magnetic head 6 is determined, and control is performed to switch the reproduction processing method to the normal reproduction mode. in this case,
The terminals n of the changeover switches 61, 62 and 63 forming a part of the reproduction mode changeover means shown in FIG. 2 are in the connected state.

Also, as in the case of the high definition reproduction mode,
In the system control circuit 10, the tracking drive circuit 7 is controlled so that the output of the envelope detection signal of the reproduction signal is maximized, and the magnetic head 6 is automatically tracked. Such automatic tracking of the magnetic head 6,
By controlling the rotational phase of the spindle motor 5 described later, a good still image can be obtained.

The luminance signal (Y + S) demodulated by the FM in the reproduction processing circuit 31A passes through the low pass filter 34A and is cut in the high frequency range. Then, the horizontal and vertical synchronizing signals are extracted from the signal by the synchronizing signal separating circuit 36. (S) is separated and extracted, and is input to each of the system control circuit 10 and the clock generation circuit 37. The horizontal and vertical synchronization signals (S) input to the system control circuit 10 are
For example, it is used for reading ID data. In addition, the clock generation circuit 37 generates a memory write clock signal that serves as a reference for writing to the memory, and the generated memory write clock signal is input to the A / D converter 38A and the memory control circuit 35, respectively. It

The luminance signal (Y) which has been FM demodulated and from which the horizontal and vertical synchronizing signals (S) have been separated is converted into a digital signal by the A / D converter 38A, and the Y memory 39
It is temporarily stored in a predetermined address of A.

The FM-demodulated color difference signal (Pr) is passed through the low pass filter 34B to cut the high frequency band, and then converted into a digital signal by the A / D converter 38B, and the Pr memory 39B through the switch 61. Is temporarily stored in. Similarly, the color difference signal (Pb) passes through the low-pass filter 34C and is cut in the high range, and then A
The signal is converted into a digital signal by the / D converter 38C and is temporarily stored in the Pb memory 39C via the switch 62.

The system control circuit 10 determines from the reproduced ID data whether the image signal read by the magnetic head 6 is an image signal belonging to the first field or an image signal belonging to the second field. Then, based on this, the operation of the memory control circuit 35 is controlled. Based on the memory write clock signal from the clock generation circuit 37, the memory control circuit 35 causes each memory 39A to
The following control is performed with the timing of writing to 39C.

That is, based on the memory write clock signal from the clock generation circuit 37, the A / D converter 38
When A operates, the memory control circuit 35 operates a built-in write address counter to write the digital data of the luminance signal (Y) to a predetermined address of the Y memory 16A.

Further, the memory write clock signal from the clock generation circuit 37 is divided into 1/2 by the frequency divider 43A to activate the A / D converters 38B and 38C, and the memory control circuit 35 The built-in write address counter is activated, and the Pr memory 39
The digital data of the color difference signal (Pr) and the color difference signal (Pb) are written in predetermined addresses of the B and Pb memories 39C, respectively. The synchronization signal (S) included in the reproduction signal such as the luminance signal is not sampled,
Therefore, it is not written to the memory.

The synchronizing signal generating circuit 40 outputs horizontal and vertical synchronizing signals corresponding to the standard image signal, for example, horizontal and vertical synchronizing signals (S) conforming to the NTSC system, and input to the clock generating circuit 41. The clock generation circuit 41 generates a memory read clock signal which serves as a reference for reading from each memory, and the memory read clock signal is input to the memory control circuit 35 and the D / A converter 42A. Further, this memory read clock signal is divided into 1/2 by the frequency divider 43B and then inputted to the D / A converters 42B and 42C, respectively.

The memory control circuit 35 performs the following control on the basis of the memory read clock signal from the clock generation circuit 41 while taking the timing of reading from each of the memories 39A to 39C. That is, based on the memory read clock signal from the clock generation circuit 41,
The memory control circuit 35 operates the built-in read address counter to read the digital data of the luminance signal (Y) from a predetermined address of the Y memory 39A, and the D / A converter 42A operates to read the digital data. The converted digital signal of the luminance signal (Y) is converted into an analog signal.

Further, based on the memory read clock signal from the clock generation circuit 41, the memory control circuit 35
Activates the built-in write address counter to read out the digital data of the color difference signal (Pr) and the color difference signal (Pb) from the predetermined addresses of the Pr memory 39B and the Pb memory 39C, respectively.
The / A converters 42B and 42C operate to convert the read digital signal of each color difference signal into an analog signal.

In the memory control circuit 35, the mode switching between the memory writing control and the memory reading control is controlled by a mode switching command signal from the system control circuit 10. The horizontal and vertical sync signals (S) from the sync signal separation circuit 36 and the horizontal and vertical sync signals (S) from the sync signal generation circuit 40 are also input to the system control circuit 10, respectively. Based on this, the rotation phase of the spindle motor 5 is controlled, and it is also used as a timing signal for various other operations.

In the case of reproducing such a standard image, the memory read clock signal from the clock generation circuit 41 and the memory write clock signal from the clock generation circuit 37 have the same frequency. Therefore, the frequency of the read clock signal of the luminance signal and the frequency of the write clock signal are the same, the frequency of the read clock signal of both color difference signals and the frequency of the write clock signal are the same, The frequency of the write and read clock signals is twice the frequency of the write and read clock signals of both color difference signals.

The luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb), which are analog signals, are respectively
The high frequency band is cut by the low pass filters 44A, 44B and 44C, and then the vertical and horizontal synchronizing signals (S) from the synchronizing signal generating circuit 40 are added to the luminance signal (Y) by the synchronizing signal adding circuit 45A. . The luminance signal (Y + S) and the color difference signal (P
r) and the color difference signal (Pb) are output as a composite video (NTSC) signal via the encoder 47, respectively, and a still image is reproduced on the connected display.

Next, the control operation when the reproduction processing system is switched by the reproduction mode switching means to reproduce the image signal from the magnetic disk 3 will be described. FIG. 12 is a flow chart showing the control operation when performing the reproduction in the high definition reproduction mode, and FIG. 13 is a flow chart showing the control operation when performing the reproduction in the normal reproduction mode.

As shown in FIG. 12, when reproduction is performed in the high-definition reproduction mode, the terminals h of the changeover switches 61 to 63 are connected to each other (step 401). Next, the synchronization signal generation circuit 40 is switched to high definition (step 402). Next, the clocks generated by the clock generation circuits 37 and 41 are switched for high definition (step 403). In this case, the frequency of the clock generated by the clock generation circuit 41 is set to four times the frequency of the clock generated by the clock generation circuit 37.

Next, each of the low pass filters 44A-4A
The cutoff frequency of 4C is switched to high definition (step 404). Specifically, each low pass filter 44
Cutoff frequencies of A to 44C are set for each D / A converter 42A.
Halves the sampling frequency of ~ 42C.

By executing steps 401 to 404, the cutoff frequency of each low pass filter 34A to 34C, the sampling frequency of each A / D converter 38A to 38C, the writing frequency to each memory 39A to 39C, each memory 39A to Read frequency from 39C,
The sampling frequency of each D / A converter 42A-42C,
The cutoff frequencies of the low pass filters 44A to 44C are set as shown in Table 3 below.

[0147]

[Table 3]

After setting each frequency as shown in Table 3 above, each track on which the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) are recorded is reproduced, and each is recorded in each of the memories 39A to 39A. It is stored in a predetermined address of 39C (step 405). Next, each memory 39A-3
The luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) stored in 9C are simultaneously read out and output to the monitor (step 406). In this way, the high definition image signal recorded in the track pattern shown in FIG. 4 is reproduced in the high definition recording mode.

Further, as shown in FIG. 13, when the reproduction is performed in the normal reproduction mode, the changeover switches 61 to 6
3 terminals n are connected to each other (step 50
1). Then, the synchronizing signal generating circuit 40 is switched to the standard one (step 502). Next, the clock generation circuit 3
The clocks generated at 7 and 41 are switched to the standard clocks (step 503). In this case, the frequency of the clock generated by the clock generation circuit 41 is made the same as the frequency of the clock generated by the clock generation circuit 37.

Next, each of the low pass filters 44A-4A
The cutoff frequency of 4C is switched to the standard (step 504). Specifically, each low pass filter 44A
~ 44C cutoff frequency for each D / A converter 42A ~
It is set to 1/2 of the sampling frequency of 42C.

By executing steps 501 to 504, the cutoff frequency of each low pass filter 34A to 34C, the sampling frequency of each A / D converter 38A to 38C, the writing frequency to each memory 39A to 39C, each memory 39A to Read frequency from 39C,
The sampling frequency of each D / A converter 42A-42C,
The cutoff frequencies of the low-pass filters 44A to 44C are set as shown in Table 4 below.

[0152]

[Table 4]

After setting each frequency as shown in Table 4, the track on which the image signal of the standard image is recorded is reproduced, and the luminance signal (Y) is subjected to a predetermined reproduction process (luminance signal) by the reproduction processing circuit 31A. The C signal reproduction processing circuit 31B performs a predetermined reproduction process (color difference signal reproduction process) on the color difference signal (Pr) and the color difference signal (Pb) to reproduce the luminance signal (Y) and the color difference signal (Y). Pr) and the color difference signal (Pb) are stored in respective addresses of the memories 39A to 39C (step 505).

Next, the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) stored in each of the memories 39A to 39C are read out simultaneously and output to the monitor as a composite video signal through the encoder 47 (step 506). . In this way, the standard image signal recorded in the normal recording mode is reproduced.

Next, another method for determining whether the image signal input to the recording system is a high definition image signal or a standard image signal will be described. Similarly to the present embodiment, the method described below also determines the image signal system by utilizing the fact that one horizontal synchronization period, one vertical synchronization period, etc. differ depending on the image signal system. The method of is mentioned.

An arbitrary time is set by the timer, and the number of pulses of the horizontal synchronizing signal within the set time is measured (counted). Then, a predetermined pulse number is set, and it is determined whether or not the measured pulse number is larger than the set value. In this case, in the high definition image signal and the standard image signal, it is preferable to set the intermediate pulse number as the set value.

For example, when discriminating between a high-definition signal and an NTSC signal, the time may be set to 1 msec and the pulse number set value α may be set to about 17 to 36. In this case, when the number of measured pulses is larger than α, it is discriminated as a high-definition signal, and when it is smaller than α, it is discriminated as an NTSC signal.

The time between two adjacent horizontal sync signals or the time between horizontal sync signals at both ends of three or more adjacent horizontal sync signals is measured. Then, a predetermined time is set, and it is determined whether or not the measured time is longer than the set value. In this case, in the high definition image signal and the standard image signal, it is preferable to set an intermediate time as the set value.

For example, when the time between two adjacent horizontal synchronizing signals is measured and the HDTV signal and the NTSC signal are discriminated, the time setting value β may be set to about 30 to 63 μsec. In this case, when the measured time is shorter than β, it is discriminated as a high-definition signal, and when it is longer than β, it is discriminated as an NTSC signal. In the case of the above methods and, the input image signal can be discriminated in a short time.

As described above, in this embodiment, the recording mode switching means is automatically operated by the mechanism for discriminating the system of the image signal input to the recording system without any manual (man-made) operation. Although the recording processing system is configured to be switched, the present invention may be configured to operate the recording mode switching unit by a manual (manual) operation. Also, a manual for the reproduction system (artificial)
The reproduction mode switching means may be operated by an operation.

Further, in the present embodiment, the setting of each frequency is performed as shown in Tables 1 to 4, but the setting of each frequency is not limited to this. It is possible to change the setting of each frequency depending on the method of the image signal input to the, the frequency band of the image signal, the screen division pattern (the number of divisions in the horizontal direction of the screen, the number of divisions in the vertical direction of the screen, etc.).

Further, in the present embodiment, the recording processing method and the reproduction processing method are respectively switched to the high definition mode and the normal mode.
The present invention may be configured such that the recording processing method and the reproduction processing method are switched to three or more, respectively.

In this embodiment, the decoder 46 is mounted as shown in FIG. 1, and the decoder 46 obtains the color difference signal from the NTSC signal.
The decoder 46 may be omitted, and the recording system may be configured to directly input the previously decoded color difference signal or the unencoded color difference signal to the recording system. Further, in this embodiment, the encoder 47 is mounted as shown in FIG. 2, but the encoder 47 may be omitted.

In the high definition recording mode of this embodiment,
The ratio of the number of tracks on which the luminance signal (Y) is recorded, the number of tracks on which the color difference signal (Pr) is recorded, and the number of tracks on which the color difference signal (Pb) is recorded for the image signal corresponding to one screen. Is set to 4: 2: 2, but is not limited to this and may be, for example, 4: 1: 1 or 2: 2: 2.

In this embodiment, the number of magnetic heads for recording and reproducing the image signal is one, but a plurality of magnetic heads may be provided in each of the recording system and the reproducing system. In such a case, each magnetic head may be, for example, a dedicated magnetic head provided for each of the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb), or an image signal for one field. Corresponding magnetic heads (in this embodiment, eight magnetic heads arranged in parallel) can be cited. Further, although the case of frame recording has been described in the present embodiment, the present invention can also be applied to an apparatus capable of field recording.

In the high definition recording mode of this embodiment,
Although the color difference signal (Pr) and the color difference signal (Pb) are recorded on different tracks, they may be recorded on the same one or two or more tracks. In this case, the color difference signal (P
r) and the color difference signal (Pb) are line-sequentially recorded, and the color difference signal (Pr) and the color difference signal (Pb) are each divided into a plurality of parts within one horizontal synchronization period (for example, divided into the first half and the second half) Then, any method of recording may be used.

Further, in the present embodiment, the image signals corresponding to one screen are recorded or reproduced in order from the track on the outer peripheral side of the magnetic disk 3, but the order is not limited to this. Further, in the high-definition recording mode of this embodiment, from the outer peripheral side of the magnetic disk 3 toward the inner peripheral side,
Luminance signals Y ₁ , Y ₂ , Y ₃ , Y _{4 of} the first field, color difference signals Pr ₁ , Pr ₂ , color difference signals Pb ₁ , Pb ₂ , second
Field of the luminance signal _{Y 5, Y 6, Y 7} , Y 8, the color difference signals Pr _3, Pr _4, but is continuously recorded by one track in the order of the color difference signals Pb _3, Pb _4, on the magnetic disk 3 The track pattern is not limited to this.

In the present invention, the image signal recording medium is
The recording medium is not limited to a magnetic recording medium such as a magnetic disk, and may be, for example, an optical recording medium or a magneto-optical recording medium. The still video device according to the present invention may have either one or both of the recording system and the reproducing system as described above. The still video device of the present invention has been described above based on the illustrated configuration example, but the present invention is not limited to this. In particular, regarding the circuit configurations of the recording system and the reproducing system, any one having the same function is included in the present invention.

[0169]

As described above, according to the still video apparatus of the present invention, image signals of different systems in the same apparatus,
For example, a high-definition image signal such as a high-definition signal and N
A standard image signal such as a TSC signal can be recorded and reproduced.

In particular, in the case of the still video apparatus of the present invention having a mechanism for discriminating the image signal system, the recording and reproduction processing system is automatically switched according to the image signal system without manual operation. Therefore, the labor of the operator is remarkably reduced, and the recording and reproducing processing method is not mistaken. The still video device of the present invention has a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a recording system of a still video device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a reproduction system of the still video device of the present invention.

FIG. 3 is a schematic diagram showing an example of a storage area pattern of image signals in each memory in the high definition recording mode.

FIG. 4 is a diagram showing an example of a track pattern formed on a magnetic disk in a high definition recording mode.

FIG. 5 is a time chart showing a relationship between a luminance signal (Y) input to a recording system of a still video device and a luminance signal (Y) recorded on a track in a high definition recording mode.

FIG. 6 is a time chart showing a relationship between a color difference signal (Pr) input to a recording system of a still video device and a color difference signal (Pr) recorded on a track in a high definition recording mode.

FIG. 7 is a block diagram showing a configuration example of a synchronization signal separation circuit.

FIG. 8 is a time chart showing the relationship between the luminance signal input to the recording system and the separated horizontal sync signal and vertical sync signal.

FIG. 9 is a flowchart showing a control operation when the recording mode switching means is automatically operated.

FIG. 10 is a flowchart showing a control operation when recording is performed in a high definition recording mode.

FIG. 11 is a flowchart showing a control operation when recording is performed in a normal recording mode.

FIG. 12 is a flowchart showing a control operation when reproduction is performed in a high definition reproduction mode.

FIG. 13 is a flowchart showing a control operation when reproduction is performed in a normal reproduction mode.

[Explanation of symbols]

 1 still video device 2 magnetic disk drive mechanism 3 magnetic disk 4 motor drive circuit 5 spindle motor 6 magnetic head 7 tracking drive circuit 8 operation unit 10 system control circuit 11A, 11B, 11C low-pass filter 12 memory control circuit 13 sync signal separation circuit 14 Clock generation circuit 15A, 15B, 15C A / D converter 16A Y memory 16B Pr memory 16C Pb memory 17A, 17B Divider 18 Sync signal generation circuit 19 Clock generation circuit 20A, 20B, 20C D / A converter 21A, 21B , 21C low-pass filter 22A, 22B, 22C sync signal adding means 23 changeover switch 24A recording processing circuit 24B C signal recording processing circuit 25 ID recording circuit 26 adder 27 recording amplifier 28 erasing signal generation Route 29 Changeover switch 30 Reproduction amplifier 31A Reproduction processing circuit 31B C signal reproduction processing circuit 32 ID reproduction processing circuit 33 Envelope detection circuit 34A, 34B, 34C Low-pass filter 35 Memory control circuit 36 Synchronous signal separation circuit 37 Clock generation circuit 38A, 38B, 38C A / D converter 39A Y memory 39B Pr memory 39C Pb memory 40 Synchronous signal generation circuit 41 Clock generation circuit 42A, 42B, 42C D / A converter 43A, 43B Frequency divider 44A, 44B, 44C Low pass filter 45A, 45B , 45C sync signal adding means 46 decoder 47 encoder 51-55 changeover switch 61-63 changeover switch 71 composite sync signal separation circuit 72 vertical sync signal separation circuit 73 horizontal sync signal separation circuit 1 1-108 step 201 to 211 301 to 307 step step 401 to 406 501 to 506 step step

Claims (10)

[Claims] 1. A still video device having a recording system for recording an image signal corresponding to one screen on a recording medium, wherein the recording system records according to a system of the image signal input to the recording system. A still video device having a recording mode switching means for switching a processing method. 2. The recording mode switching means switches the recording processing method to a recording processing method for recording a standard image signal or a recording processing method for recording a high definition image signal. Still video equipment. 3. The image signal is composed of a luminance signal and a color difference signal, and in a recording processing method for recording the high definition image signal, the luminance signal and the color difference signal are respectively recorded on a plurality of recording media. The still video device according to claim 2, wherein the still video device records the tracks separately. 4. The still video device according to claim 1, wherein the recording mode switching means is configured to operate by an artificial operation. 5. The recording mode switching means is configured to discriminate a system of an image signal input to the recording system and automatically operate according to the system of the image signal. A still video device according to any one of 1. 6. The still video device according to claim 5, wherein the system of the image signal is determined by measuring a synchronization signal of the image signal. 7. A still video device having a reproduction system for reproducing an image signal corresponding to one screen recorded on a recording medium, wherein the reproduction system reproduces according to a recording processing system of the image signal. A still video device having a reproduction mode switching means for switching a system. 8. The reproduction mode switching means switches the reproduction processing method to a reproduction processing method for reproducing a standard image signal or a reproduction processing method for reproducing a high definition image signal. Still video equipment. 9. The still video device according to claim 7, wherein the reproduction mode switching means is configured to operate by an artificial operation. 10. The still video according to claim 7, wherein the reproduction mode switching means is configured to determine a recording processing method of the image signal and automatically operate in accordance with the recording processing method. apparatus.