JPH06188871A - Frame aligner circuit - Google Patents

Abstract

PURPOSE:To provide a frame aligner circuit for which the scale of circuit constitution is small. CONSTITUTION:By a selection circuit (SEL) 9, frame information bar WSIGF for signals is inserted to the Fbit of reception signals WDATA from a transmission line and written to an elastic memory (ES) 5 at the timing of the signal WCK and a bar WR. The written signals are read at the timing of the signal RCK and the bar RR, outputted as the reception signals RDATA, also inputted to a latch circuit 10 to be latched by the signals RFPLT and thus, the frame information bar RSIGF for the signals is extracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame aligner circuit in a transmission device.

[0002]

2. Description of the Related Art A primary group of transmission devices (1,544 Mb /
s) In the interface etc., conventionally, in addition to the frame aligner circuit for matching the frame phase of the received signal sequence from the transmission line with the in-device reference phase from the network synchronizer, bit steal of the received signal from the transmission line is included. In order to identify the signal frame on the received signal that matches the in-apparatus reference phase, a frame aligner circuit has been provided for adjusting the signal frame information to the in-apparatus reference phase.

FIG. 2 is a block diagram showing an example of the configuration of this type of frame aligner circuit, and its operation will be described below with reference to the operation explanatory view shown in FIG.

The frame synchronization circuit 1 is used for a signal indicating the position of a reception frame phase bar W8K that matches the frame phase of the reception signal WDATA from the transmission line and the position of the signal frame (frame indicated by N in FIG. 3) of the reception signal WDATA. The frame information bar WSIGF is generated and output. The received frame phase bar W8K is divided by the 1/2 frequency dividing circuit 2 into two kinds of signal bars W4K1 and W4K2 having a cycle of two frames as shown in FIG. 3, and a selecting circuit (SEL) 3 Either one is selected by the signal bar W
It is output as 4K. In addition, in FIG. 3, the signal bar W4K
1 shows the case where the signal bar W4K2 is selected from the bars W4K2. Further, the in-device reference phase bar R8K from the network synchronizer is frequency-divided by the 1/2 frequency dividing circuit 7 and output as a signal bar R4K having a cycle of two frames as shown in FIG.

On the other hand, the reception signal WDATA from the transmission line is input to the terminal DI of the elastic memory (ES) 1, and the signal frame from the frame synchronization circuit 1 is input to the terminal DI of the elastic memory (ES) 2. Information bar W
SIGF is input. Further, the signal bar W4K from SEL3 is connected to each terminal bar WR of ES1 and ES2.
However, each terminal WCK has a writing clock WCK
The signal bar R4K from the 1/2 divider circuit 7 is provided in each terminal bar RR, and the read clock R is provided in each terminal RCK.
CK is input respectively.

ES1 is the received signal W input to the terminal DI
DATA is sequentially written into the built-in memory for 2 frames at the timing of the clock WCK input to the terminal WCK every time the signal bar W4K is input to the terminal bar WR, and each time the signal bar R4K is input to the terminal bar RR. The reception signals for two frames written in the memory are sequentially read at the timing of the clock RCK input to the terminal RCK, and the reception signal RD is output from the terminal DO.
Output to the device side as ATA.

On the other hand, in the same manner as in the case of ES1 described above, ES2 uses the signal frame information bar WSIGF input to the terminal ID based on the signal bar W4K and the clock WCK input to the terminal bar WR and the terminal WCK, respectively. Two frames are sequentially written in the built-in memory and a signal bar R4 is input to the terminal bar RR and the terminal RCK, respectively.
2 written to the memory based on K and clock RCK
The signal frame information bar WSIGF for the frame is read out, and the reception frame information bar RSIGF is output from the terminal DO.
Is output to the device side.

In this way, the received signal W from the transmission line is
DATA and signal frame information bar WSIGF are
As shown in FIG. 3, the signal bar R4K, that is, the in-apparatus reference phase bar R8K, is matched and output to the apparatus side as a reception signal RDATA and a signal frame information bar RSIGF.

The phase comparison circuit 4 receives the R comparison pulse from the R comparison pulse circuit 8 synchronized with the signal R4K and SE.
Compare the phase with the signal bar W4K output from L3,
Received signal bar WD written in ES1 and ES2 respectively
The write timing that allows the ATA and the signal frame information bar WSIGF to be reliably read at a predetermined read timing (signal bar R4K) is determined, and a signal bar W4K suitable for that is determined as the signal bars W4K1 and W4.
It instructs SEL3 to select from K2.

[0010]

However, in the frame aligner circuit having the above structure, the elastic memory for the received signal and the elastic memory for the frame information for the signal are separately provided, and therefore the scale of the circuit structure is large. There was a problem of getting bigger.

Further, when a part of the memory provided on another substrate or another device is used as the elastic memory, it is necessary to transfer the received signal and the signal frame information separately. The number of pins and the wiring pattern of the connector for connecting the terminals are increased, which is a problem particularly when the number of received signals is large.

In order to solve the above problems, it is an object of the present invention to provide a frame aligner circuit which inserts signal frame information into a received signal and collectively performs frame aligner in a common elastic memory. And

[0013]

In order to achieve the above object, the present invention provides a frame aligner circuit for performing a frame aligner for a received signal from a transmission line and signal frame information indicating the position of the signal frame. , The signal frame information is inserted into each frame synchronization bit (Fbit) of the received signal and written into the temporary storage memory at a predetermined write timing, and then read again at a predetermined read timing to obtain the frame synchronization bit. The inserted signal frame information is extracted.

[0014]

The frame aligner is performed by inserting the signal frame information into the frame synchronization bit of the received signal from the transmission line, and the received signal and the signal frame information are put together to perform the frame aligner. The received signal and the signal frame information are separately provided. It is possible to reduce the scale of the circuit configuration as compared with the conventional case in which the frame aligner is performed by the above circuit.

[0015]

1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of the operation of this embodiment.

In FIG. 1, 2 and 7 are 1/2 frequency divider circuits,
3 is a selection circuit (SEL), 4 is a phase comparison circuit, 5 is an elastic memory (ES), and 8 is an R comparison pulse circuit, all of which are the same as those denoted by the same reference numerals in FIG. Detailed description thereof will be omitted. Also, 1
Is a frame synchronization circuit for generating and outputting the signal bar WFP in addition to the above-mentioned signal frame information bar WSIGF and the signal bar W8K, and 9 is a reception signal WDATA from the transmission line or the frame synchronization circuit 1 based on the signal bar WFP. A selection circuit (SEL) for selecting any one of the signal frame information bars WSIGF from the above and outputting it to ES5, 10
Is the received signal RDATA output from ES5 and the signal RF
It is a latch circuit that latches based on PLT.

Next, the operation of this embodiment will be described with reference to FIGS.

The received signal WDATA from the transmission line input to the SEL 9 is composed of a plurality of frames including the signal frame shown in FIG. 4A, and a frame bit (Fbit) is inserted in each frame. There is. Similarly S
The signal frame information bar WSIG from the frame synchronization circuit 1 input to the EL 9 indicates the position of the signal frame. For example, as shown in FIG. 4A, the Fbit immediately before the signal frame changes to the signal frame. It is a pulse that becomes "0" only until the end. In addition, the signal bar WF from the frame synchronization circuit 1 that controls the operation of the SEL 9
P indicates the position of the F bit, and is a pulse which becomes "0" only in each F bit as shown in FIG. 4, for example.

Here, the SEL 9 selects and outputs the reception signal WDATA when the signal bar WFP is "1" and outputs the signal frame information bar W when the signal bar WFP is "0".
Controlled to select and output SIGF, the signal frame information bar WS is added to the Fbit on the received signal WDATA.
It functions to insert IGF. Therefore, from SEL9, as shown in FIG.
“0” is fixed to t and F immediately before the other frames
The received signal with "1" fixed to bit, that is, the received signal WDATAS in which the signal frame information is inserted is output, and is input to the terminal DI as the write data of ES5.

ES5, as described with reference to FIG. 2, receives the received signal WDATAS to the terminal bar WR and outputs the signal bar W4.
Each time K is input, two frames are sequentially written in the built-in memory at the timing of the clock WCK input to the terminal WCK, and the signal bar R4K is input to the terminal bar RR.
Clock R input to the terminal RCK every time
The reception signals for two frames written in the memory are sequentially read out at the timing of CK, and are output from the terminal DO as the reception signal RDATA on the device side and the latch circuit 10.
Output to.

In the latch circuit 10, a pulse for extracting the position of Fbit from the reception signal RDATA from the device side, for example, the reception signal RDA as shown in FIG.
A pulse RFPLT for latch which becomes "1" at the position of Fbit of TA is input. Therefore, from the output side of the latch circuit 10, as shown in FIG. 4B, the Fbit immediately before the signal frame of the reception signal RDATA is output.
A pulse that changes to “0” at the position of (“0”) and returns to “1” at the position of Fbit (“1”) immediately after the signal frame, that is, becomes “0” in the signal frame and other Frame information bar RSI for signals that becomes "1" in a frame
GF is output.

Since the above Fbit is used for monitoring the transmission line such as frame synchronization, transmission line error, and game alarm, it is considered unnecessary on the device side. There is no problem even if it is used to transfer the signal frame information.

[0023]

As described above in detail, according to the present invention, the Fbit in the received signal from the transmission line is used for the transfer of the signal frame information, and the received signal and the signal frame information are combined and combined. Since the frame aligner is used, it is not necessary to provide an elastic memory dedicated to signal frame information, and a circuit configuration is smaller and power consumption can be expected to be smaller than the conventional one.

Further, when the signal frame information needs to be transferred between boards or devices, it is expected that the number of connecting lines for transferring can be reduced as compared with the conventional case.

Further, even a device which does not require signal frame information can be used as a horizontal parity bit for error monitoring in reception signal transfer.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional frame aligner circuit.

FIG. 3 is an operation explanatory diagram of FIG. 2;

FIG. 4 is an operation explanatory diagram of FIG. 1.

[Explanation of symbols]

 1 frame synchronization circuit 2,7 1/2 frequency divider circuit 3,9 selection circuit (SEL) 4 phase comparison circuit 5 elastic memory (ES) 8 R comparison pulse circuit 10 latch circuit

Claims (1)

[Claims] 1. A frame aligner circuit for performing a frame aligner for a received signal from a transmission line and signal frame information indicating the position of the signal frame, wherein the signal frame information is provided in each frame synchronization bit of the received signal. A frame aligner circuit for extracting the signal frame information inserted in the frame synchronization bit by again reading at a predetermined read timing and writing the same in the temporary storage memory at a predetermined write timing.