JPH06187779A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make the read/write of data possible to be carried out even in the period of precharge and to attain reading out the data in the same word line serially. CONSTITUTION:A semiconductor storage device is provided with a memory cell group 3 integrating and forming a random accessable memory cell on a semiconductor substrate in matrix, a bit line BL commonly connecting plural pieces of memory cells in the memory cell group 3 and a sense amplifier 1 making these bit lines be a pair and sensing the potential difference between the bit lines BLi, /BLi made to be a pair. The data storage nodes Ai, /Ai of a register 4 with self sense amplifying ability are connected with the bit lines BLi, /BLi through transfer gates Q30, Q31, and the data of the register 4 are read out successively synchronizing with an external input trigger signal /CAS through an input/output line after the data are transferred from the memory cell to the register 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a randomly accessible semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, many new functions have been invented and developed in order to increase the speed of semiconductor memory devices. Page mode and nibble mode are typical modes devised for speeding up.

However, when changing the selected word line to the next word line in the page mode, and when changing the selected 4 bits to the next 4 bits in the nibble mode,
Be sure to precharge the bit lines and clock generator. Even in a very fast MOS dynamic RAM with an access time of 100 ns, 100 n is required for precharging the bit line and clock generator.
Also spend s. In page mode, between the column address input from the outside and the next column address,
The column address buffer and column decoder need to be reset and precharged. At present, when higher speed is required, the wasteful time required for the above-mentioned precharge becomes a problem.

[0004]

As described above, conventionally, the time required for precharging has been a factor that hinders the speedup of the semiconductor memory device. The present invention has been made in consideration of the above circumstances, and an object thereof is to enable reading and writing of data even during a precharge period.
It is to provide a semiconductor memory device that can be randomly accessed.

[0005]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention provides a memory cell array in which randomly accessible memory cells are integrated and formed in a matrix on a semiconductor substrate, a bit line in which a plurality of memory cells in these memory cell arrays are commonly connected, and these bit lines. And a sense amplifier that senses a potential difference between the paired bit lines, in a semiconductor memory device, wherein the first and second nodes that are the data storage nodes of the register having self-sense amplification capability are: Connected to a pair of bit lines via transfer gates respectively, after transferring data from randomly accessible memory cells to the register, the register data is sequentially read out via the input / output lines in synchronization with the external input trigger signal. It is characterized by

[0006]

According to the present invention, it is possible to externally read and write data even during the precharge period of the bit line, which was conventionally impossible to access data. That is, wasteful time is eliminated, continuous access is possible, and the speed of the semiconductor memory device is increased.

Further, by transferring the data of the randomly accessible memory cell to the register and then reading the data from the register in synchronization with the external input trigger signal, the data of the same word line can be serially read. .

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a MOS-dR according to an embodiment of the present invention.
It is a circuit diagram which shows the principal part structure of AM. This embodiment is an example applied to a dRAM having a folded bit line configuration, and in the figure, only the portion connected to the i-th pair of bit lines BLi and / BLi is shown.

The sense amplifier 1 is MOSFET-Q11.
To Q21 and pull-up capacitors C11 and C12. Q11 and Q12 are for drivers, and their sources are connected to the clock line φSE. Q13 and Q14 act as loads for active pull-up, and their drains are connected to the power supply VDD and their sources are connected to the bit lines BLi and / BLi, respectively. Q15, Q16 and C11, C12 form a pull-up circuit.

Q18 and Q19 are respectively Q13 and Q1.
For precharging the gate of Q4, Q17, Q
Reference numerals 20 and Q21 are for precharging the bit lines BLi, / BLi and the nodes of the sense amplifier, and their gates are all connected to the precharging clock line .phi.2.

Dummy cells 2 ₁ and 2 ₂ are connected to the bit lines BLi and / BLi, respectively. One dummy cell 2 ₁ is composed of MOSFET-Q22, Q23 and a capacitor C13, and the other dummy cell 2 ₂ is M
It is composed of OSFETs-Q24, Q25 and a capacitor C14. These dummy cells Q22 and Q25 are selected by the dummy word lines DWL1 and DWL2, respectively, and Q23 and Q24 are simultaneously selected by the clock line φ3. The reference potential terminals of the capacitors C13 and C14 are connected to the power source VDD or VSS or (1/2) VDD.

The memory cell group 3 is shown in FIG.
, WL2, WL (n-1) and 4 selected by WLn
Memory cells are shown. The reference potential terminals of the capacitors of these memory cells are also VDD, VSS or (1/2) V.
Connected to DD.

The latch type memory cell (register) 4 is M
It is composed of a flip-flop using OSFET-Q32 and Q33, and has a self-sense amplification function.
Q30 and Q31 connect the two nodes Ai and / Ai of the latch type memory cell 4 to the bit lines BLi and / BL, respectively.
It is a transfer gate connected to i. The gates of the MOSFETs-Q30 and Q31 as the transfer gates are controlled by the clock φ4.

Q34 and Q35 are bit lines BLi and / B.
I / O line I /
This is a transfer gate connected to O and / I / O. The gates of these MOSFETs-Q34 and Q35 are connected to the column selection line CSLi.

Next, the operation of the dRAM thus configured will be described with reference to FIGS. 2 and 3. Figure 2
6 is a signal waveform for explaining an operation of transferring data of a latch type memory cell to an input / output line during a bit line precharge period in addition to a normal access operation.

First, the level of the clock line φ 2 is (3/2)
It is about VDD and all bit lines are precharged. Now, paying attention to the i-th sense amplifier 1, VPP is applied to the node N13 of the capacitor C15 of the memory cell, and VSS and VDD are applied to Ai and / Ai of the latch type memory cell 4, respectively.
It is assumed that the initial voltage of is written.

In FIG. 2, when / RAS (first external input trigger signal) changes from VIH to VIL earlier than / CAS (second external input trigger signal), φ 2 becomes (3 /
2) When VDD drops to VSS and the level of the word line WL1 and dummy word line DW2 rises from VSS to (3/2) VDD, Q26 and Q25 become conductive, and the contents of C14 and C15 are changed to bit lines BLi and /, respectively. It is transmitted to BLi. Next, when the clock .phi.SE gradually falls from VDD-Vth to VSS and the sense amplifier 1 is activated, the level of the bit line / BLi from which the dummy cell is read falls to VSS. The level of the bit line BLi that has read the logic "1" is / BLi
It will drop slightly due to the coupling and racing of
When the clock .phi.1 rises from VSS to VDD and an active pull-up is applied and Q13 conducts, it returns to VPP again.

Next, the clock φ4 is changed from VSS to (3/2) V.
When the voltage reaches PP and Q30 and Q31 become conductive, the contents of the bit lines BLi and / BLi are transmitted to the nodes Ai and / Ai of the latch type memory cell 4. In the case of FIG. 2, since the state of Ai before being written was logic "0", the level of Ai has risen from VSS to VDD. / Ai is the opposite.

After that, for example, when the i-th column is selected and the level of CSLi rises from VSS to (3/2) VDD, the bit lines BLi and / BLi and the nodes Ai and / A.
i is connected to the I / O lines I / O and / I / O. I / O keeps VDD, / I / O drops from VDD to VSS, output buffer D
out outputs VOH of logic "1" from Hiz. In this state where the input / output lines are connected to the bit lines, it is possible to read and write data directly to the memory cells without using the latch type memory cells.

Next, when / CAS changes from VIL to VIH, clock φ4, word line WL1, dummy word line DWL1
Goes from (3/2) VDD to VSS, and bit line BLi
, / BLi and the latch type memory cell 4 are separated from each other, the clock φ2 rises from VSS to (3/2) VDD, and the precharge of the bit line is started.

That is, the second external input trigger signal (/ C
Transfer gates Q30 and Q31 in synchronization with AS).
Becomes non-conductive, and the bit lines BLi and / BLi are disconnected from the latch type memory cell 4.

Then, / CAS falls from VIH to VIL again, and when the jth column is selected, the data of the jth latch type memory cell (not shown) already separated from the bit line is written. Are transferred to the input / output line. In FIG. 2, the contents of the j-th latch type memory cell is Aj = VS
It indicates that S, / Aj = VDD.

As described above, the first external input trigger signal (/ RAS) controls reading of randomly accessible memory cells to the bit lines BL and / BL and the sensing operation of the bit line sense amplifier. The second external input trigger signal (/ CAS) controls reading of the data transferred to the latch type memory cell 4 from the output buffer via the input / output line. That is, after the data is transferred from the randomly accessible memory cell to the latch type memory cell 4, the data of the latch type memory cell 4 is transferred through the input / output lines I / O and / I / O in synchronization with / CAS. , Output buffer Dout
From i to j. Thus, continuous high-speed reading from the latch type memory cell 4 to the output buffer Dout can be performed.

FIG. 3 is a signal waveform for explaining the operation when the data written in the latch type memory cell is transferred to the memory cell. In FIG. 3, when / CAS changes from VIH to VIL earlier than / RAS, the clock φ2 becomes (3 /
2) From VDD to VSS, the bit line becomes floating. Then, the clock φ4 rises from VSS to (3/2) VDD earlier than the word line and the dummy word line. Since the latch type memory cell 4 is a static type memory cell, the MOSFET-Q30 and Q3 are driven by the clock φ4.
When 1 becomes conductive, the contents of Ai and / Ai are BLi and / BL
i, respectively, and the level of BLi changes from VDD to VSS
, And the level of / BLi keeps VDD. After that, when the word line WL1 and the dummy word line DWL2 are selected, the logic "1" which is the content of Ai is written in the capacitor C15 of the memory cell.

As described above, according to this embodiment, it is possible to obtain a dRAM capable of continuous high-speed access without wasting time only for precharging. The present invention is not limited to the above embodiments, but can be implemented with various modifications. For example, in the embodiment, the case of the folded bit line structure has been described, but the present invention can be applied in principle to a dRAM having a so-called open end type bit line structure. The present invention can also be applied to a static RAM.

[0026]

As described in detail above, according to the present invention, a register having a self-sense amplification capability is connected to a pair of bit lines via a transfer gate to allow random access from a memory cell to a register. After the transfer, the data in the register is sequentially read out via the input / output lines in synchronization with the external input trigger signal, so that the data can be externally read even during the precharge period of the bit line where the conventional data cannot be accessed. Read / write is possible.
That is, wasteful time is eliminated, continuous access is possible, and the speed of the semiconductor memory device is increased. Further, by transferring the data of the randomly accessible memory cell to the register and then reading the data from the register in synchronization with the external input trigger signal, the data of the same word line can be serially read.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a dRAM according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the dRAM according to the embodiment.

FIG. 3 is a signal waveform diagram for explaining the operation of the dRAM according to the embodiment.

[Explanation of symbols]

1 ... Sense amplifier 2 ₁ , 2 ₂ ... Dummy cell 3 ... Memory cell group 4 ... Latch type memory cell (register) BL, / BL ... Bit line WL1, WL2, WL (n-1), WLn ... Word line Q30, Q31 ... MOS transistor (transfer gate)

Claims (3)

[Claims] 1. A memory cell array in which randomly accessible memory cells are integrated and formed in a matrix on a semiconductor substrate, bit lines in which a plurality of memory cells in these memory cell arrays are commonly connected, and these bit lines. And a sense amplifier that senses a potential difference between the paired bit lines. In a semiconductor memory device, the first and second nodes that are data storage nodes of a register having self-sense amplification capability are The data of the register is connected to the pair of bit lines via transfer gates, and after the data is transferred from the randomly accessible memory cell to the register, the data of the register is transferred via the input / output line in synchronization with the external input trigger signal. A semiconductor memory device characterized by being sequentially read. 2. The external input trigger signal is composed of two kinds of signals, and the first external input trigger signal reads data of the randomly accessible memory cell to the bit line and sense operation of the sense amplifier. 2. The second external input trigger signal is used for sequentially reading the data transferred to the register via an input / output line. Semiconductor memory device. 3. Synchronizing with a second external input trigger signal,
3. The semiconductor memory device according to claim 2, wherein the MOS transistor forming the transfer gate is turned off, and the bit line and the register are disconnected.