JPH06187185A - Duplex device - Google Patents

Abstract

PURPOSE:To attain the time adjustment and mismatching detection of the operation of the central control unit of a duplex synchronizing operation. CONSTITUTION:In a system in which CPU 10 and 11, and IOP (input and output controller) 20 and 21 are duplexed, the 0 system CPU 10 is connected through a 0 system bus 30 with the 0 system TOP 20, the other 1 system CPU 11 is connected through a 1 system bus 41 with the 0 system IOP 20 the 0 system CPU 10, 0 system IOP 20, and 0 system MM (main storage) 15 are mounted on a 0 system case 1, and the 1 system CUP 11, IOP 21, and MM 16 are mounted on a 1 system case 2. A DLY (adjusting circuit) adjusts the time difference of control signals inputted from the both system CPU 10 and 11, and an MAT (mismatching circuit) operates the time adjustment and mismatching detection of the operation of the CPU of the duplex synchronizing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplexer, and more particularly, to a duplexer for detecting a synchronization mismatch and adjusting a synchronization between a central control unit and an input / output control unit which perform duplex synchronous operation in an information processing apparatus. .

[0002]

2. Description of the Related Art A dual central control unit and an input / output control unit are mounted in separate housings in respective systems, the central control units are operating synchronously, and the central control unit controls input / output of one system. In a system which takes an operation mode of accessing a device, conventionally, a mismatch of output buses is detected for each operation clock of a central control device.

Recently, the improvement of the processing capability of the central control unit and the speeding up of the operation clock have been unavoidable, and this tendency is particularly remarkable in the RISC processor.

It is impossible to check the coincidence / non-coincidence of all outputs for each clock of the central controller operating with a high-frequency clock when the housings to be mounted are different and there is a physical distance. In such a case, conventionally, the synchronous operation system of the central control device has been abandoned.

[0005]

In this conventional system, when the above-mentioned synchronous operation is not performed, the central control unit operates only one system, and the contents are copied to the main storage device of the other system. Since the amount of write data transferred to other systems is large, the number of interface signals between enclosures increases.

Further, a large-capacity FIFO buffer is required to realize high-speed large-capacity data transfer. However, the increase in the capacity of the FIFO buffer between the main storage devices causes an increase in the change time of the operating system, resulting in an increase in the reconfiguration time of the system, which causes a decrease in the reliability of the system. There was a point.

[0007]

The duplexer of the present invention comprises:
In the duplexer in which the central controller, the main storage device, and the input / output controller are duplexed as 0 system and 1 system,
The 0-system central control device and the 0-system input / output control device are connected by a 0-system bus, and the 1-system central control device and the 1-system input / output control device are connected by a 1-system bus, 0
The system central control device and the 0-system input / output control device, and the 1-system central control device and the 1-system input / output control device are separately mounted in the 0-system and 1-system housings, respectively. Each of the input / output control devices is an arbitration circuit that arbitrates a time difference between control signals input from the central control devices of both systems,
A holding circuit for holding the control signal and an address and data input from the central control unit of both systems, a mismatch detection circuit, and a response time adjusting circuit, and the operation time of the central control unit in the duplex synchronous operation. It is characterized by performing arbitration and inconsistency detection.

The arbitration circuit receives an input / output instruction signal of its own system and an input / output instruction signal of another system to delay the input / output instruction signal of its own system by n clocks.
After the clock, it is checked whether or not the input / output instruction signals of the other system come, and when the input / output instruction signals of the both systems are complete, the input / output instruction signals of the both systems are output to the mismatch detection circuit, When the input / output instruction signals of the system are not complete, a mismatch detection signal is output to the mismatch detection circuit.

Further, when the mismatch detection circuit receives the input / output instruction signals for both systems from the arbitration circuit, it checks whether the address and data held in the holding circuit match, and they match. Then, the reception end signal is transmitted to the response time adjusting circuit, and when the non-coincidence signal is received from the arbitration circuit, the non-coincidence signal and the reception end signal are transmitted to the response time adjusting circuit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the duplexer of the present invention.

As shown in FIG. 1, the system of the present embodiment has a central control unit (hereinafter CPU) 10 and a main memory (hereinafter M).
The M) 15 and the input / output control device (hereinafter, IOP) 20 are duplicated by the CPU 11, the MM 16, and the IOP 21, respectively.

0-system CPU 10 and 0-system IOP 20 are 0
Connected by system bus 30 and CPU 11 of system 1 and IO of system 0
It is connected to the P20 by the 1-system bus 40, and the 0-system CPU 10
And 0 system IOP20 and 0 system MM15 are 0 system housing 1
It is implemented on the 1st system CPU11, IOP21 and MM16
And are mounted on the 1-system housing 2.

FIG. 4A is a block diagram showing an example of the input / output control device in FIG. 1, and FIG. 4B is a diagram for explaining the operation of FIG.

As shown in FIG. 4, for example, the IOP 20 is a system interface unit (hereinafter referred to as SINTF) 100, which interfaces with the CPUs 10 and 11 (shown in FIG. 1) of both systems.
Other system interface unit (hereinafter referred to as MINTF) 110, arbitration circuit (hereinafter referred to as DLY) 50 that arbitrates a time difference between control signals input from both CPUs 10 and 11, and the above control signal is input from both system CPUs 10 and 11. An address buffer (hereinafter referred to as SBF) 60 that holds an address and data,
A data buffer (hereinafter referred to as MBF) 70, a mismatch detection circuit (hereinafter referred to as MAT) 80, and a response time adjustment circuit (hereinafter referred to as RD)
L) 90.

FIG. 2 is a diagram for explaining the synchronous operation operation of both central control units in FIG.

As shown in FIG. 2, the 0-system CPU 10 accesses the 0-system MM15, and the 1-system CPU 11 accesses the 1-system M15.
Instructions are executed in synchronization while accessing M16.

FIG. 3 is a diagram for explaining the operation of accessing the input / output control device when the central control device in FIG. 1 is in synchronous operation.

In this example, the 0-system CPU 10 and the 1-system CPU 10
Both of the PUs 11 are accessing the 0-system IOP 20. The IOP 20 is connected to an input / output device (not shown) by an input / output bus, but the connection between the input / output control device and the input / output device is a known technique, and a description thereof will be omitted here.

In FIG. 4, an input / output instruction signal from the 0-system CPU 10 is sent through the 0-system bus 30 to the SINTF100.
CPU 1 of the 1st system via the 1st system bus 41 on one side
The input / output instruction signal from 1 is received by the MINTF 10.

In this example, the 0 system CPU 10 is the 1 system C
Since the PU 1 is mounted on the housing 1 different from the housing 2, the above two input / output instruction signals do not arrive at exactly the same time. Therefore, the DLY 50 arbitrates this time difference.

That is, DLY50 is SINTF100
Receives the input / output instruction signal of its own system from MINTF1
10 receives the input / output instruction signal of the other system, the n-bit shift register delays the input / output instruction signal of the own system from the SINTF 100 by n clocks, and after this n clocks, MINT.
It is checked whether or not the input / output instruction signal of the other system comes from F110.

When the input / output instruction signals for both systems are complete, the signals for both systems are output to the MAT 80. If it does not arrive, it outputs a mismatch detection signal to the MAT 80.

The MAT 80 outputs the input / output instruction signals of both systems by DL.
It is checked whether the address and data information received from Y50 and held in the SBF 60 and MBF 70 match, and if they match, only the received signal is transmitted to the RDL 90. If a mismatch signal is received from the DLY 50, the mismatch detection signal and the reception end signal are transmitted to the RDL 90.

The RDL 90 transmits only the reception end signal to the SINTF 100 and the MINTF 110 when they do not match, and sends the mismatch detection signal and the reception end signal to each other when they do not match. At this time, when the distance between the housings of the two systems is large, the signal transmission to the own system is delayed by a delay period corresponding to the difference in the connection lengths, so that the CPU 10 of the 0 system and the CPU 1 of the 1 system are delayed.
The arrival times at 1 and CPU 10 and C
Enables the synchronous operation of the PU 11 to continue.

As described above, according to this embodiment, the outputs of the CPUs of the two systems mounted in separate housings and operating in synchronization are arbitrated to detect the coincidence / non-coincidence, and a circuit is arranged so that the response outputs arrive at the same time. With the configuration, if a mismatch occurs between both systems, the failure can be detected immediately.

[0026]

As described above, according to the present invention, since it is possible to synchronize the operation of the central control device which is duplicated and mounted in different housings and to detect the disagreement, a high performance and highly reliable duplexing is possible. This has the effect of realizing the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a duplexer of the present invention.

FIG. 2 is a diagram for explaining a synchronous operation operation of both central control devices in FIG.

FIG. 3 is a diagram for explaining an operation of accessing the input / output control device when the central control device in FIG. 1 is in synchronous operation.

4A is a block diagram showing an example of the input / output control device in FIG. 1, and FIG. 4B is a diagram for explaining the operation of FIG.

[Explanation of symbols]

 1, 20 system, 1 system housing 10, 110 system, 1 system central control unit (CPU) 15, 160 system, 1 system main memory (MM) 20, 210 system, 1 system Output control device (IOP) 30 Bus for connecting 0-system CPU and 0-system IOP 31 Bus for connecting 1-system CPU and 1-system IOP 40 40 Bus for connecting 0-system CPU and 1-system IOP 41 1 Bus for connecting system CPU and 0 system IOP 50 Arbitration circuit (DLY) 60 Address buffer (SBF) 70 Data buffer (MBF) 80 Mismatch detection circuit (MAT) 90 Response time adjustment circuit (RDL) 100 Own system interface Unit (SINTF) 110 Other system interface unit (MINTF)

Claims (3)

[Claims] 1. A duplexer in which a central control unit, a main storage unit, and an input / output control unit are duplicated as a 0-system and a 1-system, wherein the 0-system central control unit and the input / output control unit are a 0-system bus. And the 1-system central controller and the input / output controller are connected by a 1-system bus, and the 0-system central controller, the 0-system input / output controller and the 1-system central controller are connected. The 1-system input / output control device is separately mounted in the 0-system and 1-system chassis,
Each of the input / output control devices holds an arbitration circuit that arbitrates a time difference between control signals input from the central control devices of both systems, and a holding unit that holds the control signals and addresses and data input from the central control devices of both systems. A circuit, a mismatch detection circuit,
A duplexer, comprising a response time adjusting circuit, and performing time arbitration and non-coincidence detection of the operation of the central controller in duplex synchronous operation. 2. The arbitration circuit receives an input / output instruction signal of its own system and an input / output instruction signal of another system to delay the input / output instruction signal of its own system by n clocks, and after this n clocks, the other It is checked whether or not the input / output instruction signals of the systems are received. When the input / output instruction signals of the both systems are complete, the input / output instruction signals of the both systems are output to the mismatch detection circuit, and the input / output of the both systems is input. The duplexer according to claim 1, wherein a mismatch detection signal is output to the mismatch detection circuit when the instruction signals are not complete. 3. The mismatch detection circuit checks whether the address and data held in the holding circuit match when receiving the input / output instruction signals of the both systems from the arbitration circuit, and if there is a match. In this case, the reception end signal is transmitted to the response time adjusting circuit, and when the non-coincidence signal is received from the arbitration circuit, the non-coincidence signal and the reception end signal are transmitted to the response time adjusting circuit. Item 1. The duplexer according to Item 1 or 2.