JPH06187183A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To facilitate the countermeasure to the memory fault of a control program at a high speed, in a multiprocessor system which executes a data processing according to a control program. CONSTITUTION:The processor which develops the same control program according to the same address is equipped with an informing means 5 which communicates the error address of the control program to the other processor, transferring means 11 which reads the control program indicated by the error address from among the control program provided at its own processor when the error address is communicated from the other processor, and transfers it to the processor being the origin of communication, rewriting means 8 which rewrites the error control program provided at its own processor with the control program when the control program is transferred from the other processor, and resuming means 9 which instructs the resumption of the data processing when the control program is rewritten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a structure for executing data processing according to a control program, and more particularly to a multiprocessor system capable of coping with a memory failure of a control program at high speed and appropriately. Regarding

In a data processing system, data processing is executed while controlling a hardware mechanism according to a control program. From now on, it is necessary for the data processing system to have a mechanism for coping with the memory failure of the control program, but this mechanism needs to be constructed with a structure capable of coping with the memory failure as fast as possible. .

[0003]

2. Description of the Related Art In a conventional data processing system, an ECC mechanism is provided to cope with a correctable memory fault in order to cope with a memory fault occurrence in a control program loaded in a control memory.

When a memory failure that cannot be corrected by the ECC mechanism occurs, it is dealt with by reloading the control program from the external storage device, or the control program is loaded in the system storage in advance. , The control program on the system memory is written in the control memory.

This prior art is the same even when the data processing system has a multiprocessor configuration.

[0006]

[Problems to be Solved by the Invention] However, the ECC
If the mechanism is provided, there is a problem that the execution of data processing is delayed due to the check processing.

When a memory failure that cannot be corrected by the ECC mechanism occurs, if the method of coping by reloading the control program from the external storage device is adopted, this reloading takes time. There is a point. In addition, if a method is adopted in which the control program is loaded in the system memory in advance and the control program in the system memory is written into the control memory, the memory capacity of the system memory is used for that purpose. There is a problem that becomes.

In addition, the conventional technique has a problem in that the control program itself is normal and there is no means for appropriately dealing with a case where a failure occurs in the hardware mechanism itself. .

The present invention has been made in view of the above circumstances, and in a multiprocessor system having a configuration of executing data processing according to a control program, it is possible to quickly and appropriately cope with a memory failure of the control program. The purpose is to provide a new multiprocessor system.

[0010]

FIG. 1 shows the principle configuration of the present invention. 1a and 1b are processors, and 2 is a bus connecting between the processors 1a and 1b. The processors 1a and 1b execute data processing according to the same control program.

The processor 1a comprises a control memory 3 for developing a control program, a reading means 4, a notifying means 5, a managing means 6, a comparing means 7, a rewriting means 8 and a restarting means 9. On the other hand, the processor 1b includes a control memory 10 that expands a control program that is the same as the control program of the processor 1a according to the same address information, and a transfer unit 11. Here, the processor 1a may include the transfer unit 11 included in the processor 1b, and the processor 1b may include each unit included in the processor 1a.

The reading means 4 of the processor 1a detects whether or not there is an error in the control program read from the control memory 3 according to a parity check or the like. Notification means 5
Notifies the error address of the error control program detected by the reading means 4 to the transfer means 11 of the processor 1b. The management unit 6 manages the error address notified by the notification unit 5 as the previously detected error address. The comparing means 7 compares the error address detected by the reading means 4 with the error address managed by the managing means 6. The rewriting means 8 rewrites the error control program stored in the control memory 3 to the original one. The restarting means 9 gives an instruction to restart the data processing.

The transfer means 11 of the processor 1b transfers the correct control program to the rewriting means 8 of the processor 1b.

[0014]

In the present invention, the reading means 4 of the processor 1a is
When executing the data processing, the control programs are sequentially read from the control memory 3, and it is detected whether or not there is an error in the read control program according to a parity check or the like. 7 is notified of the error address of the control program in which the error occurred.

Upon receiving this error address, the comparison means 7 compares this error address with the previously detected error address managed by the management means 6 and activates the notifying means 5 when the two do not match. . On the other hand, when they match, it is determined that the fixed error is not the error of the control program itself but the fixed error of the hardware in response to the same error being repeated, and the fixed error is displayed to the host system. To do.

The notification means 5, when activated by the comparison means 7, notifies the transfer means 11 of the processor 1b of the error address detected by the reading means 4. Upon receiving this error address, the transfer means 11 of the processor 1b reads the control program pointed to by the error address notified from the control program managed by the control memory 10 of its own processor, and modifies the read control program. As the control program for the error, it is transferred to the rewriting means 8 of the processor 1a which is the notification source of the error address.

Upon receiving the correction control program, the rewriting means 8 corrects the control program by rewriting the error control program portion pointed to by the error address detected by the reading means 4 to the correction control program. To do. Then, when this correction process ends, the resuming means 9
Indicates restart of data processing from the modified control program-related part.

As described above, according to the present invention, in a multiprocessor system having a structure for executing data processing in accordance with a control program, when a failure occurs in the control program, a correct control program is copied from another processor and corrected. By doing so, since the memory failure of the control program is dealt with, the memory failure of the control program can be dealt with at high speed, unlike the prior art.

If the same error occurs repeatedly even after executing this recovery processing, the fixed failure display is executed so that the failure of the hardware mechanism itself can be appropriately dealt with. It becomes.

[0020]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 2 illustrates a system configuration example of a multiprocessor system to which the present invention is applicable.

In the figure, reference numeral 20 denotes a system processing unit (hereinafter sometimes abbreviated as SPU) which controls the control processing of the entire system and control processing of an input / output device, and 21 indicates an external storage device provided in the system processing unit 20. , 22 is an I / O device included in the system processing unit 20, 23 is a communication control device included in the system processing unit 20, and 24 is a plurality of I / O processing units (hereinafter abbreviated as IOP) that control the input / output devices. 25) I / O
An I / O device included in the processing unit 24, a communication control device 26 included in the I / O processing unit 24, and a plurality of instruction processing units (hereinafter sometimes abbreviated as IPU) 27 that control instruction processing.
Reference numeral 8 is a system memory accessible by the units 20, 24, 27, and 29 is a bus connecting the units 20, 21, 22 and the system memory 23.

In the multiprocessor system having this configuration, the system processing unit 20 and each I
The / O processing unit 24 has a configuration in which the same control program for controlling the control processing of the input / output device is expanded according to the same address information, and while controlling the hardware mechanism in accordance with this same control program, its own device. Subordinate I / O devices 22, 25 and communication control devices 23, 2
6 is adopted.

FIG. 3 shows an I / O processing unit 24.
FIG. 4 is a detailed device configuration diagram of the system processing unit 20, and FIG. 4 is a detailed device configuration diagram of the system processing unit 20. As shown in FIG. 3, the I / O processing unit 24 reads out the control memory 240 for developing the control program and the control memory 240 in order from the control memory 240 at the time of executing the data processing. The read mechanism 241 for detecting whether or not the read control program has an error, the control flag 242 for setting an error detection flag to that effect when the read mechanism 241 detects a control program error, and the read mechanism 241. When detecting a control program error, a first error address register 243 that latches the address information of the detected error control program and a second error address register 244 that latches the address information of the previously detected error control program. And the system processing unit 20 Al and correction data register 245 for storing the transferred come control program for modifying the control program failure to perform fault processing for error program 246
With.

On the other hand, the system processing unit 20
As shown in FIG. 4, the control memory 200 expands the control program, the error address register 201 latches the error address information of the control program transferred from the I / O processing unit 24, and the control memory 200. A correction data register 202 for storing the read control program and a failure program 203 for executing failure processing for a control program error are provided. Here, the control memory 200 has a configuration in which a control program for controlling the control processing of the entire system and a control program for controlling the control processing of the input / output device are developed, but as described above, The same address information as that of the control memory 240 of the I / O processing unit 24 is assigned to the control program for controlling the control processing of the input / output device.

FIG. 5 shows the I / O processing unit 24.
FIG. 6 shows an example of a processing flow executed by the fault program 246 included in the system processing unit 20.
An example of the processing flow which the fault program 203 with which this comprises is shown in figure. Next, according to these processing flows, the control memory 240 of the I / O processing unit 24 is
The operation processing of this embodiment, which is executed when an error occurs in the control program of the, will be described in detail.

First, according to the processing flow of FIG.
Fault program 2 provided in the O processing unit 24
The processing executed by 46 will be described. In the fault program 246 included in the I / O processing unit 24, the read mechanism 241 detects the control program error, and thus the error detection flag is set in the control flag 242 (at this time, the error address information is set in the first error address register 243). Will also be set) and will be started.

When the fault program 246 is activated in this way, as shown in the processing flow of FIG. 5, first, at step 1, the error occurrence control program is either the command section or the data section. If it is determined to be a data part, in response to the fact that this data part has unique data corresponding to the data processing history up to that point, it is impossible to apply the present invention, Proceeding to step 2, the system processing unit 20 is notified of an error in the data section and the processing is terminated. Upon receiving this data section error information, the system processing unit 20 executes, for example, a process of disconnecting the I / O processing unit 24 in which the error occurred.

On the other hand, if it is determined in step 1 that the error occurrence control program is the instruction part, the process proceeds to step 3 and the first error address register 24
3 and the error address information held by the second error address register 244 are judged to be the same, and when they are judged to be the same, the same error is repeated. Then, it is judged that the error is not the error of the control program itself but the fixed failure of the hardware, the process proceeds to step 4, the system processing unit 20 is notified of the hardware failure, and the processing is ended. When receiving this hardware failure information, the system processing unit 20
Performs, for example, a process of disconnecting the I / O processing unit 24 in which an error has occurred.

On the other hand, when it is determined in step 3 that the two error address information do not match, step 5
Then, the error program information of the first error address register 243 is designated to the fault program 203 of the system processing unit 20 to notify the error interrupt through a control line (not shown). Then, the error address information held in the first error address register 243 is set in the second error address register 244, and then in step 7, the system processing unit 20 responds to the error interrupt notification in step 5. Enter the waiting state for the transferred control program.

As will be understood from the processing flow of FIG. 6 described below, the fault program 203 of the system processing unit 20 specifies error address information from the fault program 246 of the I / O processing unit 24 to notify the error interrupt. When the error message is received, the control program indicated by the error address information is sent to the control memory 200 of the own unit.
Read from the I / O as a control program for correction
Modified data register 245 of processing unit 24
Works to transfer to.

Now, the I / O processing unit 2
The failure program 246 of No. 4 receives the processing end notification indicating the completion of transfer of the control program from the system processing unit 20 in step 7 of the processing flow of FIG. 5, proceeds to step 8, and moves to the first error address register 243. The control program of the control memory 240 indicated by the error address information held by the correction data register 24
By rewriting the control program stored in No. 5, the control program in which the error occurred is corrected. Then, in the following step 9, the error address information held by the first error address register 243 is reset and the error detection flag of the control flag 242 is reset,
Finally, in step 10, an instruction is given to restart the data processing that was interrupted due to the control program error.

Next, according to the processing flow of FIG. 6, the fault program 2 provided in the system processing unit 20.
The processing executed by 03 will be described. The fault program 203 provided in the system processing unit 20 is
In accordance with the processing of step 5 of the processing flow of FIG. 5 described above, it is activated when error address information is specified from the fault program 246 of the I / O processing unit 24 and a notification of an error interrupt is received.

When booted in this way, the fault program 203, as shown in the processing flow of FIG. 6, first of all, in step 1, the I / O processing unit 24.
The error address information held by the first error address register 243 is read into the error address register 201. Next, in step 2, the control program of the control memory 200 indicated by the error address information held by the error address register 201 is read and set in the correction data register 202. Then, in step 3, the control program held in the correction data register 202 is set to I
/ O processing unit 24 modified data register 2
45. And finally, in step 4, I /
The faulty program 246 of the O processing unit 24 is notified of the processing end and the processing ends.

In this way, when the control program indicated by the error address information is received according to the processing of the fault program 203 of the system processing unit 20, I
/ O processing unit 24 fault program 246
As described above, after the control program in which an error has occurred is corrected according to this control program, the restart of data processing is instructed.

[0035]

As described above, according to the present invention,
In a multiprocessor system with a configuration that executes data processing according to a control program, when a failure occurs in the control program, copy the correct control program from another processor and modify it to cope with the memory failure of the control program. Since such a configuration is adopted, it becomes possible to deal with the memory failure of the control program at a high speed unlike the prior art.

If the same error occurs repeatedly even after executing this recovery process, the fixed failure display is executed so that the failure of the hardware mechanism itself can be appropriately dealt with. It becomes.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a system configuration example of a multiprocessor system to which the present invention is applicable.

FIG. 3 is an example of the device configuration of an IOP.

FIG. 4 is an example of an SPU device configuration.

FIG. 5 is an example of a processing flow executed by a faulty program of an IOP.

FIG. 6 is an example of a processing flow executed by a faulty program of an SPU.

[Explanation of symbols]

 1a processor 1b processor 2 bus 3 control memory 4 reading means 5 notifying means 6 managing means 7 comparing means 8 rewriting means 9 restarting means 10 control memory 11 transfer means

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ikuko Igarashi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (3)

[Claims] 1. In a multiprocessor system including a plurality of processors, at least two of which execute data processing according to the same control program, a processor which develops the same control program, Notifying means (5) for notifying the other processor that develops the control program of the error address when detecting an error of the control program while adopting a configuration for developing the control program according to the same address information When the error address is notified from the notification means (5), the control program indicated by the error address is read from the control programs of the own processor and transferred to the processor that notified the error address. Means (11) and the transfer means (11) of another processor When the control program is transferred, rewriting means for rewriting the error control program with the own processor to the control program
(8) and resuming means (9) for instructing resumption of data processing from the control program-related part when the rewriting means (8) rewrites the control program. Processor system. 2. The multiprocessor system according to claim 1, wherein the processors that develop the same control program manage the error address of the previously detected control program, and when the error of the control program is detected. By adopting a configuration including a comparing means (7) for comparing the error address detected this time and the error address detected last time, when the comparing means (7) detects a match between the two, a fixed fault occurrence is displayed. Along with the above, the above comparison means (7)
The multiprocessor system is characterized in that, when detects a discrepancy between the two, the notification means (5) is activated. 3. The multiprocessor system according to claim 1 or 2, wherein not all processors that develop the same control program are provided with transfer means (11), but one or a plurality of stipulated rules are provided. A multiprocessor system characterized in that the processor comprises a transfer means (11).