JPH06180601A - Multiplex controller - Google Patents

Multiplex controller

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Publication number
JPH06180601A
JPH06180601A JP33146792A JP33146792A JPH06180601A JP H06180601 A JPH06180601 A JP H06180601A JP 33146792 A JP33146792 A JP 33146792A JP 33146792 A JP33146792 A JP 33146792A JP H06180601 A JPH06180601 A JP H06180601A
Authority
JP
Japan
Prior art keywords
condition
signal
output
satisfied
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33146792A
Other languages
Japanese (ja)
Other versions
JP2696050B2 (en
Inventor
Akio Kato
秋夫 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
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Priority to JP33146792A priority Critical patent/JP2696050B2/en
Publication of JPH06180601A publication Critical patent/JPH06180601A/en
Application granted granted Critical
Publication of JP2696050B2 publication Critical patent/JP2696050B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To prevent the continuity of the mismatching state of the output of each controller by matching the operating timing of each controller in a multiplex controller. CONSTITUTION:This device is constituted of plural controllers 23 which compare a process signal with a set value, and output a signal B indicating whether or not a condition is established, which are provided corresponding to plural sensors 3 provided at the same points of a plant, and a selecting circuit 9 which outputs a control command S to an equipment 11 to be controlled based on each controller output B. And also, each controller 23 is constituted of a comparator 25 for condition establishment and a comparator 27 for condition failure, discriminating circuit 29 for condition establishment which searches the logical sum of an output signal C of the comparator 25 for condition establishment with the controller output B of its own system, and outputs a discrimination signal E for condition establishment, and collating circuit 31 which fetches the discriminating signal E for condition establishment, an output signal D of the comparator 27 for condition failure, and the discrimination signals E for condition establishment of the other systems, searches the logical product of those signals, and outputs the signal B.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プラントからのプロセ
ス信号に基づいてプラントを制御する制御システムにお
いて、同一ポイントのプロセス信号を複数のセンサーで
検出し、各検出信号と設定値との比較に基づいて内部条
件を成立させて演算を行い、操作指令や操作量を出力す
る多重化制御装置に関する。
BACKGROUND OF THE INVENTION The present invention relates to a control system for controlling a plant based on a process signal from the plant, wherein process signals at the same point are detected by a plurality of sensors and each detected signal is compared with a set value. The present invention relates to a multiplex control device that establishes internal conditions based on which calculation is performed and outputs an operation command and an operation amount.

【0002】[0002]

【従来の技術】原子力発電所等の高い安全性および信頼
性が要求されるプラントでは、プラントの制御システム
の信頼性を向上させるために、プラントの状態量を検出
するセンサーから、このセンサーによって検出されたプ
ロセス量を入力する制御器までを多重化する場合が多
い。
2. Description of the Related Art In a plant requiring high safety and reliability such as a nuclear power plant, in order to improve the reliability of a plant control system, a sensor for detecting a state quantity of the plant is used to detect the state quantity of the plant. In many cases, even the controller for inputting the processed process amount is multiplexed.

【0003】図4はこのような多重化制御装置1の従来
例を示すもので、図4において、符号3-1〜3-nはプラ
ントの同一ポイントに設置されるセンサーである。各セ
ンサー3-1〜3-nによって検出されるプロセス信号p1
〜pn は、それぞれ対応する制御器5-1〜5-nに入力さ
れ、与えられた設定値rと比較器7-1〜7-nにて比較さ
れる。制御器5-1〜5-nは、比較器7-1〜7-nによる比
較結果に基づいて、例えばp≧rで条件成立(ONまたは
1)、p<rで条件不成立(OFF または0)、あるいは
p≦rで条件成立、p>rで条件不成立とする信号A1
〜An を出力する。選択回路9は制御器5-1〜5-nから
出力される信号A1 〜An を入力し、これらの信号A1
〜An の状態(ON/OFF 、1/0等)の一致により、操
作指令Sを被制御器11に出力する。
FIG. 4 shows a conventional example of such a multiplexing control apparatus 1, and in FIG. 4, reference numerals 3-1 to 3-n are sensors installed at the same point in the plant. Process signal p1 detected by each sensor 3-1 to 3-n
.About.pn are input to the corresponding controllers 5-1 to 5-n and compared with the given set value r by the comparators 7-1 to 7-n. Based on the comparison result by the comparators 7-1 to 7-n, the controllers 5-1 to 5-n satisfy the condition (ON or 1) when p ≧ r, and do not satisfy the condition (OFF or 0) when p <r. ), Or a signal A1 that satisfies the condition when p≤r and does not satisfy when p> r
~ An is output. The selection circuit 9 inputs the signals A1 to An output from the controllers 5-1 to 5-n and outputs the signals A1 to An.
The operation command S is output to the controlled device 11 when the states An to ON (ON / OFF, 1/0, etc.) match.

【0004】[0004]

【発明が解決しようとする課題】一般に冗長化された制
御装置に対応して個別に用意されたセンサーからのプロ
セス量は、センサーの取付位置や個々のセンサー特性等
の相違により異なっている。
Generally, the process amount from the sensor individually prepared corresponding to the redundant control device differs depending on the mounting position of the sensor, individual sensor characteristics and the like.

【0005】また、通常用いられている比較器には、セ
ンサーから入力するプロセス量の微小の変動により比較
結果がON/OFF または1/0を繰り返すいわゆるチャタ
リングを生ずることのないように、設定値を動作用(以
下、動作値という。)と復帰用(以下、復帰値とい
う。)に別け、この動作値と復帰値とに差を持たせるヒ
ステリシスが設けてある。
Further, a commonly used comparator has a set value so as not to cause so-called chattering in which the comparison result repeats ON / OFF or 1/0 due to a minute fluctuation of the process amount input from the sensor. Is provided for operating (hereinafter referred to as operating value) and for returning (hereinafter referred to as returning value), and a hysteresis is provided to make a difference between the operating value and the returning value.

【0006】このようなヒステリシスを有する比較器を
用いてプロセス量と設定値との比較を行うように制御装
置を構成した場合、通常冗長化された制御装置の各内部
条件や演算結果は、入力プロセス量の相違による多少の
動作タイミングのずれや演算結果に許容範囲内のバラツ
キは許容されるが、ほぼ同様な動作を行うことが理想的
である。
When the control device is configured to compare the process amount and the set value by using the comparator having such a hysteresis, each internal condition and the operation result of the redundant control device are normally input. Although some deviation in the operation timing due to the difference in the process amount and variation within the allowable range in the calculation result are allowed, it is ideal that almost the same operation is performed.

【0007】しかしながら、図4に示すような従来の多
重化制御方式では、図5に示すように、プロセス量pが
復帰値r1 と動作値r2 の中間に継続してある場合、各
制御器間の出力信号A1 〜An の不一致が継続すること
があり、この出力信号A1 〜An が示す条件の成立/不
成立によって積分器の動作開始等を行うようなケースで
は、継続した不一致状態によって各制御器内の演算結果
に許容値以上の差が生ずることになる。多重化制御装置
の操作指令や操作量出力は、選択回路9により3つのう
ち2つが一致する方をとる2 out of 3や、中間値選択
等で適宜選択され被制御器11に与えられるため安全上
の問題はないが、多重化制御装置1における各制御器5
-1〜5-nの動作が同様でないという制御上好ましくない
状態が継続する。
However, in the conventional multiplexing control system as shown in FIG. 4, when the process amount p continues between the return value r1 and the operation value r2 as shown in FIG. In some cases, the output signals A1 to An may continue to disagree with each other, and in the case where the operation of the integrator is started or not due to the satisfaction / dissatisfaction of the condition indicated by the output signals A1 to An, each controller may be affected by the continuous disagreement. Therefore, the difference between the allowable values will be generated. The operation command and the operation amount output of the multiplex control device are safety because they are given to the controlled device 11 by 2 out of 3 in which two out of three are matched by the selection circuit 9 or by an intermediate value selection or the like. Although there is no problem above, each controller 5 in the multiplexing control device 1
The control unfavorable state that the operations of -1 to 5-n are not the same continues.

【0008】本発明は、かかる従来の課題を解決するた
めになされたもので、プロセス量と設定値との比較によ
り内部条件の成立/不成立を決定する場合に、多重化制
御装置における各制御器の内部条件を同じタイミングで
成立または不成立させるようにして、不一致状態の継続
を防止し、各制御器が同様な動作を行う多重化制御装置
を提供することを目的とする。
The present invention has been made in order to solve such a conventional problem, and each controller in a multiplex control device is used when it is determined whether or not an internal condition is satisfied by comparing a process amount with a set value. It is an object of the present invention to provide a multiplexing control device in which the internal conditions are satisfied or not satisfied at the same timing to prevent the disagreement state from continuing and each controller performs the same operation.

【0009】[0009]

【課題を解決するための手段】すなわち、以上のような
課題を解決するため本発明の多重化制御装置は、プラン
トの同一ポイントに設置される複数のセンサーで検出さ
れるプロセス信号それぞれに対し、プロセス信号を条件
成立用設定値と比較し条件成立か否かの判定を行う条件
成立用比較器、プロセス信号を条件成立用設定値と有意
差を有する条件不成立用設定値と比較し条件成立か否か
の判定を行う条件不成立用比較器、および自己の条件成
立用比較器の出力信号と自己の条件不成立用比較器の出
力信号と自己の照合信号と他の条件判定情報とに基づい
て条件成立か否かの照合信号を出力する照合信号出力部
を備える複数の制御器と、複数の制御器からの出力信号
に基づいてプラントの操作信号を出力する選択回路とを
有することを特徴とする。
That is, in order to solve the above problems, the multiplexing control device of the present invention, for each process signal detected by a plurality of sensors installed at the same point of the plant, A comparator for condition satisfaction that compares the process signal with the set value for condition satisfaction to determine whether the condition is met, and a process signal is compared with the set value for condition satisfaction that has a significant difference from the set value for condition satisfaction The condition-based comparator that determines whether or not the condition is satisfied, and the output signal of the self-condition-based comparator, the output signal of the self-condition-unvalidated comparator, the self-matching signal, and other condition determination information. It is characterized by having a plurality of controllers provided with a collation signal output unit for outputting a collation signal indicating whether or not it is established, and a selection circuit for outputting a plant operation signal based on output signals from the plurality of controllers. To.

【0010】また本発明の多重化制御装置は、プラント
の同一ポイントに設置される複数のセンサーで検出され
るプロセス信号それぞれに対し、プロセス信号を条件成
立用設定値と比較し条件成立か否かの判定を行う条件成
立用比較器、プロセス信号を条件成立用設定値と有意差
を有する条件不成立用設定値と比較し条件成立か否かの
判定を行う条件不成立用比較器、自己の条件成立用比較
器の出力信号と自己の照合信号との論理和からなる条件
成立用判定信号を出力する条件成立用判定回路、および
自己の条件成立用判定回路の出力信号と自己の条件不成
立用比較器の出力信号と他の条件成立用判定回路の出力
信号とに基づいて条件成立か否かの照合信号を出力する
照合回路を備える複数の制御器と、複数の制御器からの
出力信号に基づいてプラントの操作信号を出力する選択
回路とを有することを特徴とする。
Further, the multiplex control apparatus of the present invention compares the process signal with the set value for condition satisfaction for each process signal detected by a plurality of sensors installed at the same point of the plant and determines whether the condition is satisfied or not. Comparator for condition satisfaction, which makes a judgment of the condition, Comparing the process signal with the setting value for condition satisfaction that has a significant difference from the setting value for condition satisfaction, and judging whether the condition is satisfied or not Determination circuit for outputting a condition satisfaction determination signal composed of the logical sum of the output signal of the self-comparison signal and its own verification signal, and the output signal of the self-condition satisfaction determination circuit and the self-conditional non-compliance comparator Based on the output signals from the plurality of controllers and the matching circuit that outputs the matching signal indicating whether or not the condition is satisfied based on the output signal of And having a selection circuit which outputs an operation signal of the plant.

【0011】さらにまた本発明の多重化制御装置は、プ
ラントの同一ポイントに設置される複数のセンサーで検
出されるプロセス信号それぞれに対し、プロセス信号を
条件成立用設定値と比較し条件成立か否かの判定を行う
条件成立用比較器、プロセス信号を前記条件成立用設定
値と有意差を有する条件不成立用設定値と比較し条件成
立か否かの判定を行う条件不成立用比較器、自己の条件
成立用比較器の出力信号と自己の照合信号との論理和と
自己の条件不成立用比較器の出力信号との論理積からな
る条件判定信号を出力する条件判定回路、および自己の
条件判定回路の出力信号と他の条件判定回路の出力信号
とに基づき条件成立か否かの照合信号を出力する照合回
路を備える複数の制御器と、複数の制御器からの出力信
号に基づいてプラントの操作信号を出力する選択回路と
を有することを特徴とする。
Furthermore, the multiplexing control device of the present invention compares the process signal with the set value for condition satisfaction for each process signal detected by a plurality of sensors installed at the same point of the plant, and determines whether or not the condition is satisfied. A comparator for satisfying the condition, a process signal that compares the process signal with a set value for the condition not satisfied having a significant difference from the set value for the condition satisfied, and a comparator for not satisfying the condition, A condition determination circuit that outputs a condition determination signal that is a logical product of an output signal of a condition satisfaction comparator and its own verification signal and a logical product of an output signal of its own condition disagreement comparator, and its own condition determination circuit Based on the output signal of the other condition determination circuit and the output signal of the other condition determination circuit, and a controller based on the output signals from the plurality of controllers, each of which has a matching circuit that outputs a verification signal indicating whether or not the condition is satisfied. And having a selection circuit for outputting a preparative operation signal.

【0012】[0012]

【作用】上記構成において、条件成立用比較器は、対応
するセンサーから入力したプロセス信号が条件成立用設
定値より大か小かにより条件成立か否かを判定する。同
時に、条件不成立用比較器は、同じプロセス信号が条件
不成立用設定値より大か小かにより条件成立か否かを判
定する。条件成立用設定値と条件不成立用設定値とは差
を設けてあり、例えば設定値以上で条件成立の場合、条
件成立用比較器で用いる設定値は条件不成立用比較器で
用いる設定値より大きな値とする。各制御器は、条件成
立用比較器による比較結果、条件不成立用比較器による
比較結果に加え、自らの制御器出力および他の制御器に
おける比較情報を考慮して、条件成立か否かの信号を出
力する。これにより、各制御器間の条件成立/不成立の
動作タイミングを同調させることができるとともに、入
力するプロセス値が設定値付近で変動するような場合で
も成立/不成立の繰り返しを避けることができる。
In the above structure, the condition satisfaction comparator determines whether or not the condition is satisfied depending on whether the process signal input from the corresponding sensor is larger or smaller than the condition satisfaction set value. At the same time, the condition non-compliance comparator determines whether or not the condition is met depending on whether the same process signal is larger or smaller than the condition non-compliance set value. There is a difference between the set value for condition fulfillment and the set value for condition not fulfillment.For example, when the condition is met at the set value or more, the set value used by the condition fulfillment comparator is larger than the set value used by the condition not fulfilled comparator. The value. Each controller considers the output of its own controller and the comparison information of other controllers, in addition to the comparison result by the comparator for condition satisfaction and the comparison result by the comparator for condition not satisfied, and outputs a signal indicating whether or not the condition is satisfied. Is output. This makes it possible to synchronize the operation timings of the satisfaction / non-establishment of conditions among the respective controllers, and avoid repetition of success / failure even when the input process value fluctuates near the set value.

【0013】また、条件成立用判定回路および照合回路
を設けた構成において、条件成立用判定回路は、条件成
立用比較器による判定結果と当該制御器から出力された
直前の判定結果の少なくとも一方が条件成立のとき条件
成立とする条件成立用判定信号を出力する。照合回路
は、条件成立用判定回路からの出力信号を入力するとと
もに、条件不成立用比較器の出力信号と、他の制御器の
条件成立用判定回路からの条件成立用判定信号とを入力
し、これらの入力信号がすべて条件成立のとき条件成立
として判定し、またいずれか1つでも条件不成立となっ
たときは条件不成立として判定する。これにより、各制
御器間の動作タイミングが一致するとともに、プロセス
信号の値変動による条件成立/不成立の判定繰り返しを
防ぐことができる。
Further, in the configuration provided with the condition satisfaction determination circuit and the collation circuit, the condition satisfaction determination circuit has at least one of the determination result by the condition satisfaction comparator and the immediately previous determination result output from the controller. When the condition is satisfied, a condition satisfaction determination signal indicating that the condition is satisfied is output. The matching circuit inputs the output signal from the condition satisfaction determination circuit, inputs the output signal of the condition failure comparator and the condition satisfaction determination signal from the condition satisfaction determination circuit of the other controller, When all of these input signals satisfy the condition, it is determined that the condition is satisfied, and when any one of them is not satisfied, it is determined that the condition is not satisfied. As a result, the operation timings of the respective controllers coincide with each other, and it is possible to prevent repetition of determination of condition satisfaction / non-establishment due to a value change of the process signal.

【0014】さらに、条件判定回路および照合回路を有
する構成において、条件判定回路は、条件成立用比較器
による判定結果と当該制御器から出力された直前の判定
結果の少なくとも一方が条件成立で、かつ条件不成立用
比較器による判定結果が条件成立のときに条件成立とす
る条件判定信号を出力する。そして照合回路は、条件判
定回路からの出力信号を入力するとともに、他の制御器
の条件判定回路より同様の条件判定信号を入力し、これ
らの入力信号のうち予め決められた数の入力信号が条件
成立のとき条件成立として判定するものである。これに
より、各制御器間の条件成立/不成立の動作タイミング
を同調させることができるとともに、プロセス信号の値
変動による条件成立/不成立の判定繰り返しを防ぐこと
ができる。
Further, in the configuration having the condition judging circuit and the collating circuit, the condition judging circuit is such that at least one of the judgment result by the condition satisfaction comparator and the immediately preceding judgment result output from the controller is satisfied, and When the result of the judgment by the comparator for not satisfying the condition is that the condition is satisfied, the condition judging signal that makes the condition satisfied is output. Then, the matching circuit inputs the output signal from the condition judging circuit and the same condition judging signal from the condition judging circuits of the other controllers, and a predetermined number of input signals among these input signals are input. When the condition is satisfied, it is determined that the condition is satisfied. This makes it possible to synchronize the operation timings of the conditions established / not established among the respective controllers, and it is possible to prevent repeated determinations of the conditions established / not established due to the change in the value of the process signal.

【0015】[0015]

【実施例】以下、図面に基づいて本発明の実施例を詳細
に説明する。なお、全図面を通して同一部分には同一符
号を付し、重複する説明は省略する。
Embodiments of the present invention will now be described in detail with reference to the drawings. Note that the same portions are denoted by the same reference symbols throughout the drawings, and overlapping description will be omitted.

【0016】図1は、本発明の多重化制御装置の一実施
例を示すものである。ここでは、同一ポイントに設置さ
れるセンサー3の数を3個として説明する。この多重化
制御装置21は、各センサー3-1〜3-3からプロセス信
号p1 〜p3 をそれぞれ入力する各制御器23-1〜23
-3と、これらの制御器23-1〜23-3からの出力信号B
1 〜B3 に基づいて操作指令Sを被制御器11に出力す
る選択回路9で構成される。
FIG. 1 shows an embodiment of the multiplexing controller of the present invention. Here, the number of sensors 3 installed at the same point will be described as three. The multiplex control device 21 has controllers 23-1 to 23 to which the process signals p1 to p3 are input from the sensors 3-1 to 3-3, respectively.
-3 and output signals B from these controllers 23-1 to 23-3
The selection circuit 9 outputs the operation command S to the controlled device 11 based on 1 to B3.

【0017】そして、各制御器23-1〜23-3には、動
作値と復帰値とにヒステリシスを持たせない比較器が条
件成立用25-1〜25-3と条件不成立用27-1〜27-3
とに別個に設けられている。条件成立用比較器25-1〜
25-3は、プラントから入力したプロセス信号p1 〜p
3 を動作値に対応する条件成立用設定値r2 と比較し、
例えばp≧r2 ならば条件成立(ON)、p<r2 ならば
条件不成立(OFF)と判定してその判定結果C1 〜C3 を
出力する。条件不成立用比較器27-1〜27-3は、プラ
ントから入力したプロセス信号p1 〜p3 を復帰値に対
応する条件不成立用設定値r1 と比較し、条件成立用比
較器25-1〜25-3と同様にp≧r1 ならば条件成立
(ON)、p<r1 ならば条件不成立(OFF)と判定してそ
の判定結果D1 〜D3 を出力する。この場合、r1 <r
2 である。
In each of the controllers 23-1 to 23-3, comparators that do not have hysteresis between the operating value and the return value are provided for satisfying the conditions 25-1 to 25-3 and not satisfying the conditions 27-1. ~ 27-3
And are separately provided. Conditional comparator 25-1 ~
25-3 is the process signals p1 to p input from the plant.
3 is compared with the set value r2 for satisfying the condition corresponding to the operation value,
For example, if p ≧ r2, the condition is satisfied (ON), and if p <r2, the condition is not satisfied (OFF), and the determination results C1 to C3 are output. The condition unsatisfied comparators 27-1 to 27-3 compare the process signals p1 to p3 input from the plant with the condition unsatisfied set value r1 corresponding to the return value, and the condition satisfied comparators 25-1 to 25- As in the case of 3, if p≥r1 is satisfied, the condition is satisfied (ON), and if p <r1 is satisfied, the condition is not satisfied (OFF), and the determination results D1 to D3 are output. In this case, r1 <r
It is 2.

【0018】各制御器23-1〜23-3には、さらに条件
成立用判定回路29-1〜29-3と、照合回路31-1〜3
1-3が設けられている。条件成立用判定回路29-1〜2
9-3はOR回路からなり、条件成立用比較器25-1〜2
5-3からの出力信号C1 〜C3 を入力するとともに、自
系の制御器23-1〜23-3からの直前の出力信号B1'〜
B3'を取り込み、信号C1 〜C3 と信号B1'〜B3'の論
理和からなる条件成立用判定信号E1 〜E3 を出力す
る。照合回路31-1〜31-3はAND回路からなり、条
件成立用判定回路29-1〜29-3からの条件成立用判定
信号E1 〜E3 と条件不成立用比較器27-1〜27-3か
らの出力信号D1 〜D3 を入力するとともに、他系の条
件成立用判定回路の出力信号(照合回路31-1の場合、
回路29-2と29-3からの信号E2 とE3 )を取り込
み、各入力信号(照合回路31-1の場合、D1 、E1 、
E2 、E3 )の論理積からなる信号B1 〜B3 を制御器
出力信号として選択回路9に出力する。
Each of the controllers 23-1 to 23-3 further includes a determination circuit 29-1 to 29-3 for condition satisfaction and a matching circuit 31-1 to 3-3.
1-3 are provided. Conditional determination circuit 29-1 to 29-2
Reference numeral 9-3 is an OR circuit, and comparators 25-1 to 25-2 for satisfying the condition.
The output signals C1 to C3 from 5-3 are input, and the output signals B1 'to B3' from the previous control signals 23-1 to 23-3 of the own system are input.
B3 'is taken in, and condition-satisfying determination signals E1 to E3 consisting of the logical sum of the signals C1 to C3 and the signals B1' to B3 'are output. The matching circuits 31-1 to 31-3 are AND circuits, and the condition satisfaction determination signals E1 to E3 from the condition satisfaction determination circuits 29-1 to 29-3 and the condition failure comparators 27-1 to 27-3. From the output signals D1 to D3 from the output signal of the determination circuit for satisfaction of the condition of the other system (in the case of the matching circuit 31-1,
The signals E2 and E3 from the circuits 29-2 and 29-3 are taken in and each input signal (D1, E1, in the case of the matching circuit 31-1)
The signals B1 to B3 formed by the logical product of E2 and E3) are output to the selection circuit 9 as controller output signals.

【0019】次に、上記構成の多重化制御装置21の動
作を説明する。なお、ここではプロセス値が設定値以上
のとき条件成立(=1)、設定値より小のとき条件不成
立(=0)の場合を例に挙げて説明する。
Next, the operation of the multiplexing control device 21 having the above configuration will be described. Here, a case where the condition is satisfied (= 1) when the process value is equal to or larger than the set value and the condition is not satisfied (= 0) when the process value is smaller than the set value will be described as an example.

【0020】条件成立用判定回路29-1〜29-3の出力
信号E1 〜E3 を論理式で表現すると、
When the output signals E1 to E3 of the condition satisfaction determination circuits 29-1 to 29-3 are expressed by logical expressions,

【数1】E1 =C1 +B1' E2 =C2 +B2' E3 =C3 +B3' となる。また、照合回路31-1〜31-3すなわち制御器
23-1〜23-3の出力信号B1 〜B3 を論理式で表現す
ると、
## EQU1 ## E1 = C1 + B1 'E2 = C2 + B2' E3 = C3 + B3 '. Further, when the output signals B1 to B3 of the matching circuits 31-1 to 31-3, that is, the controllers 23-1 to 23-3 are expressed by logical expressions,

【数2】B1 =E1 ・E2 ・E3 ・D1 B2 =E1 ・E2 ・E3 ・D2 B3 =E1 ・E2 ・E3 ・D3 となる。[Equation 2] B1 = E1 * E2 * E3 * D1 B2 = E1 * E2 * E3 * D2 B3 = E1 * E2 * E3 * D3.

【0021】ここで、各センサー3-1〜3-3の検出値で
あるプロセス信号p1 〜p3 がすべて条件成立用設定値
r2 以上の場合、条件成立用比較器25-1〜25-3の出
力信号C1 〜C3 は、
Here, when the process signals p1 to p3 which are the detection values of the respective sensors 3-1 to 3-3 are all equal to or more than the set value r2 for satisfying the condition, the comparators 25-1 to 25-3 for satisfying the condition. The output signals C1 to C3 are

【数3】C1 =C2 =C3 =1 となるため、(数1)より、直前の制御器出力B1'〜B
3'の状態にかかわらず、条件成立用判定信号E1 〜E3
は、
[Equation 3] Since C1 = C2 = C3 = 1, from (Equation 1), the immediately preceding controller outputs B1 ′ to B are obtained.
Regardless of the 3'state, the judgment signals E1 to E3 for satisfaction of the condition are established.
Is

【数4】E1 =E2 =E3 =1 となる。またこの場合、条件不成立用比較器27-1〜2
7-3の出力信号D1 〜D3 は当然、
## EQU4 ## E1 = E2 = E3 = 1. Further, in this case, the comparators 27-1 to 27-2 for not satisfying the condition
The output signals D1 to D3 of 7-3 are naturally

【数5】D1 =D2 =D3 =1 であるから、(数2)、(数4)より、各制御器23-1
〜23-3の出力B1 〜B3 はすべて
## EQU5 ## Since D1 = D2 = D3 = 1, from (Equation 2) and (Equation 4), each controller 23-1
Outputs B1 to B3 of ~ 23-3 are all

【数6】B1 =B2 =B3 =1(成立) となる。## EQU6 ## B1 = B2 = B3 = 1 (established).

【0022】また、プロセス信号p1 〜p3 がいずれか
1つでも条件不成立用設定値r1 未満の場合、条件不成
立用比較器27-1〜27-3の出力信号D1 〜D3 のいず
れかが0となるため、(数2)と(数1)より、条件成
立用判定回路29-1〜29-3の出力信号E1 〜E3 のい
ずれかが0となり、したがって(数2)より制御器出力
B1 〜B3 はすべて
If any one of the process signals p1 to p3 is less than the set value r1 for unsatisfied condition, one of the output signals D1 to D3 of the comparators 27-1 to 27-3 for unsatisfied condition is 0. Therefore, according to (Equation 2) and (Equation 1), one of the output signals E1 to E3 of the determination circuit 29-1 to 29-3 for condition satisfaction becomes 0, and therefore from (Equation 2) the controller output B1 to B3 is all

【数7】B1 =B2 =B3 =0(不成立) となる。## EQU7 ## B1 = B2 = B3 = 0 (not established).

【0023】さらにまた、プロセス信号p1 〜p3 が条
件不成立用設定値r1 以上で条件成立用設定値r2 未満
の場合、条件成立用比較器25-1〜25-3と条件不成立
用比較器27-1〜27-3のそれぞれの出力信号C1 〜C
3 、D1 〜D3 は、
Furthermore, when the process signals p1 to p3 are equal to or more than the set value r1 for not satisfying the condition and less than the set value r2 for satisfying the condition, the comparators for condition satisfaction 25-1 to 25-3 and the comparator for condition not satisfied 27- Output signals C1 to C of 1 to 27-3
3, D1 to D3 are

【数8】C1 =C2 =C3 =0 D1 =D2 =D3 =1 となるが、条件成立用判定回路29-1〜29-3の出力信
号E1 〜E3 は、(数1)に示すように、直前の制御器
出力B1'〜B3'に依存する。すなわちB1'〜B3'が0な
らばE1 〜E3 は0となり、(数2)より、照合回路3
1-1〜31-3の出力信号B1 〜B3 は0となる。一方、
B1'〜B3'が1ならばE1 〜E3 は1となり、(数2)
より、照合回路31-1〜31-3の出力信号B1 〜B3 は
1となる。したがって、プロセス信号p1 〜p3 が条件
不成立用設定値r1 以上条件成立用設定値r2 未満にあ
る場合、前の制御状態が維持され、制御器出力B1 〜B
3 は変化しない。
[Equation 8] C1 = C2 = C3 = 0 D1 = D2 = D3 = 1, but the output signals E1 to E3 of the condition determination determination circuits 29-1 to 29-3 are as shown in (Equation 1). , B3 'depending on the immediately preceding controller outputs B1' to B3 '. That is, if B1 'to B3' are 0, E1 to E3 are 0, and according to (Equation 2), the matching circuit 3
The output signals B1 to B3 of 1-1 to 31-3 are zero. on the other hand,
If B1 'to B3' is 1, E1 to E3 will be 1 (Equation 2)
Accordingly, the output signals B1 to B3 of the matching circuits 31-1 to 31-3 become 1. Therefore, when the process signals p1 to p3 are equal to or greater than the condition satisfaction setting value r1 and less than the condition satisfaction setting value r2, the previous control state is maintained and the controller outputs B1 to B3.
3 does not change.

【0024】以上の説明からも明らかなように、上記実
施例によれば、プラントからのプロセス値p1 〜p3 が
条件成立用設定値r2 に近付く方向で大きくなった場
合、すべての制御器内の信号C1 〜C3 が条件成立とな
ったときのみ、制御器出力B1〜B3 は同一タイミング
で条件成立となり、逆にこの条件成立の状態からいずれ
か1つのプロセス値が条件不成立用設定値r1 未満に減
少した場合には、直ちに制御器出力B1 〜B3 はすべて
同時に不成立となる。このように、各制御器が出力する
内部条件B1 〜B3 は同時タイミングで成立/不成立と
なり、常に一致する。また、プロセス値p1 〜p3 が条
件不成立用設定値r1 以上条件成立用設定値r2 未満に
ある場合には、各制御器の出力信号B1 〜B3 の状態は
変化せず、プロセス値の変動による成立/不成立の繰り
返しを起こすことはない。
As is clear from the above description, according to the above embodiment, when the process values p1 to p3 from the plant become large in the direction of approaching the condition-satisfying set value r2, Only when the conditions of the signals C1 to C3 are satisfied, the controller outputs B1 to B3 are satisfied at the same timing, and conversely, one of the process values becomes less than the condition non-establishment setting value r1 from the condition of this condition being satisfied. When it decreases, the controller outputs B1 to B3 are all immediately disabled at the same time. In this way, the internal conditions B1 to B3 output by the respective controllers are satisfied / not satisfied at the same timing and always match. If the process values p1 to p3 are equal to or more than the set value r1 for not satisfying the condition and less than the set value r2 for satisfying the condition, the states of the output signals B1 to B3 of the respective controllers do not change and are satisfied by the change of the process value. / It does not cause repeated failure.

【0025】図2は、本発明の他の実施例を示すもの
で、図1に示す実施例と異なる点は、条件成立用判定回
路29-1〜29-3の代わりに条件判定回路41-1〜41
-3を設け、照合回路43-1〜43-3をAND回路ではな
くOR回路としたことである。条件判定回路41-1〜4
1-3は、条件成立用比較器25-1〜25-3の出力信号C
1 〜C3 と自系の直前の制御器出力信号B1'〜B3'との
論理和である信号E1 〜E3 と条件不成立用比較器27
-1〜27-3の出力信号D1 〜D3 との論理積を条件判定
信号F1 〜F3 として出力する。照合回路43-1〜43
-3は自系と他系のすべての条件判定信号F1 、F2 、F
3 を入力し、その論理和を制御器出力B1〜B3 として
出力する。
FIG. 2 shows another embodiment of the present invention, which is different from the embodiment shown in FIG. 1 in that instead of the condition satisfaction judging circuits 29-1 to 29-3, the condition judging circuit 41- 1 to 41
-3 is provided, and the matching circuits 43-1 to 43-3 are not OR circuits but OR circuits. Condition determination circuits 41-1 to 4
1-3 are output signals C of the comparators 25-1 to 25-3 for condition satisfaction.
Signals E1 to E3 which are the logical sum of 1 to C3 and the controller output signals B1 'to B3' immediately before the own system and the comparator 27 for not satisfying the condition.
-1 to 27-3 and the logical product of the output signals D1 to D3 are output as the condition determination signals F1 to F3. Collation circuit 43-1 to 43
-3 is all condition judgment signals F1, F2, F of own system and other system
3 is input and the logical sum thereof is output as controller outputs B1 to B3.

【0026】この構成においては、条件判定回路41-1
〜41-3からの条件判定信号F1 〜F3 のを論理式で表
現すると、
In this configuration, the condition judging circuit 41-1
When the condition judgment signals F1 to F3 from ~ 41-3 are expressed by a logical expression,

【数9】F1 =D1 ・E1 F2 =D2 ・E2 F3 =D3 ・E3 であり、制御器出力B1 〜B3 は、[Equation 9] F1 = D1.E1 F2 = D2.E2 F3 = D3.E3 and the controller outputs B1 to B3 are

【数10】B1 =F1 +F2 +F3 B2 =F1 +F2 +F3 B3 =F1 +F2 +F3 で表される。このように、制御器出力B1 〜B3 はすべ
て同等となるため、各制御器は同一タイミングで動作す
る。なお、本実施例では、プロセス値p1 〜p3のいず
れかが条件成立用設定値r2 以上となったとき、(数
1)、(数9)より条件判定信号F1 〜F3 のいずれか
が1となり、(数10)より制御器出力B1〜B3 はす
べて1(条件成立)となる。また、プロセス値p1 〜p
3 のすべてが条件不成立用設定値r1 未満となったと
き、(数9)より条件判定信号F1 〜F3 がすべて0と
なり、(数10)より制御器出力B1 〜B3 はすべて0
(条件不成立)となる。さらに、プロセス信号p1 〜p
3 が条件成立用設定値r2 以上から未満に減少した場
合、条件成立用比較器25-1〜25-3の出力信号C1 〜
C3は1から0に変化するが、直前の制御器出力B1'〜
B3'は1であるから、(数1)より信号E1 〜E3 は1
のままであり、(数9)から明らかなように、条件不成
立用比較器27-1〜27-3の出力信号D1 〜D3 のすべ
てが0に変化しない限り、制御器出力B1 〜B3 は1の
まま変化しない。また、プロセス信号p1 〜p3 が条件
不成立用設定値r1 未満から以上に増大したとき、条件
不成立用比較器27-1〜27-3の出力信号D1 〜D3 が
0から1に変化するが、プロセス信号p1 〜p3 が条件
成立用設定値r2 未満であれば条件成立用比較器25-1
〜25-3の出力信号C1 〜C3 は0から1に変化せず、
(数1)より信号E1 〜E3 も0のままである。したが
って、信号D1 〜D3 と信号E1 〜E3 の論理積である
信号F1 〜F3 も0のまま変動せず、プロセス信号p1
〜p3 のいずれかが条件成立用設定値r2 以上とならな
い限り、制御器出力B1 〜B3 は0のままである。
## EQU10 ## B1 = F1 + F2 + F3 B2 = F1 + F2 + F3 B3 = F1 + F2 + F3 In this way, the controller outputs B1 to B3 are all equal, so that the controllers operate at the same timing. In this embodiment, when any one of the process values p1 to p3 is equal to or more than the condition setting set value r2, one of the condition determination signals F1 to F3 becomes 1 from (Equation 1) and (Equation 9). , (Equation 10), all the controller outputs B1 to B3 are 1 (condition is satisfied). Also, the process values p1 to p
When all of 3 become less than the set value r1 for not satisfying the condition, the condition determination signals F1 to F3 all become 0 from (Equation 9), and the controller outputs B1 to B3 all become 0 from (Equation 10).
(The condition is not satisfied). Furthermore, the process signals p1 to p
When 3 is decreased from the condition-satisfying set value r2 to less than the condition-satisfaction setting value r2, the output signals C1 to
C3 changes from 1 to 0, but the previous controller output B1 '~
Since B3 'is 1, the signals E1 to E3 are 1 from (Equation 1).
As is clear from (Equation 9), the controller outputs B1 to B3 are 1 unless all the output signals D1 to D3 of the condition non-satisfying comparators 27-1 to 27-3 change to 0. It remains unchanged. Further, when the process signals p1 to p3 increase from less than the set value r1 for not satisfying the condition to more than, the output signals D1 to D3 of the comparators 27-1 to 27-3 for not satisfying the condition change from 0 to 1, but If the signals p1 to p3 are less than the condition setting set value r2, the condition satisfaction comparator 25-1
The output signals C1 to C3 of ~ 25-3 do not change from 0 to 1,
According to (Equation 1), the signals E1 to E3 also remain 0. Therefore, the signals F1 to F3, which are the logical product of the signals D1 to D3 and the signals E1 to E3, remain unchanged at 0 and the process signal p1
The controller outputs B1 to B3 remain 0 unless any of .about.p3 exceeds the setting value r2 for condition satisfaction.

【0027】このように、この実施例においては、プロ
セス値p1 〜p3 のいずれかが条件成立用設定値r2 以
上となったとき、制御器出力B1 〜B3 は同一タイミン
グで条件成立となり、プロセス値p1 〜p3 のすべてが
条件不成立用設定値r1 未満になったとき、制御器出力
B1 〜B3 は同一タイミングで条件不成立となる。
As described above, in this embodiment, when any one of the process values p1 to p3 becomes equal to or more than the set value r2 for satisfying the condition, the controller outputs B1 to B3 satisfy the condition at the same timing and the process value When all of p1 to p3 become less than the set value r1 for not satisfying the condition, the controller outputs B1 to B3 are not satisfied at the same timing.

【0028】図3は、本発明のさらに他の実施例を示す
もので、図2に示す実施例のOR論理の照合回路43-1
〜43-3の代わりに、ここでは2 out of 3論理の照合
回路51-1〜51-3を設けている。
FIG. 3 shows still another embodiment of the present invention. The OR logic matching circuit 43-1 of the embodiment shown in FIG.
.. 43-3 are replaced by 2 out of 3 logic collating circuits 51-1 to 51-3.

【0029】この照合回路51-1〜51-3においては、
出力信号B1 〜B3 は、
In the matching circuits 51-1 to 51-3,
The output signals B1 to B3 are

【数11】B1 =F1 ・F2 +F2 ・F3 +F3 ・F1 =B2 =B3 となり、各制御器は同一タイミングで動作する。また、
この実施例では、2系統のプロセス信号が条件成立用設
定値r2 以上あるいは条件不成立用設定値r1 未満とな
ったとき、制御器出力B1 〜B3 は条件成立あるいは条
件不成立となる。
[Equation 11] B1 = F1.multidot.F2 + F2.multidot.F3 + F3.multidot.F1 = B2 = B3, and each controller operates at the same timing. Also,
In this embodiment, when the process signals of the two systems are equal to or more than the set value r2 for satisfying the condition or less than the set value r1 for not satisfying the condition, the controller outputs B1 to B3 are satisfied or not satisfied.

【0030】なお、上記実施例以外にも、設定値の異な
る2つの比較器による判定結果と、自系の制御器出力
と、他系の制御器における判定情報に基づいて、各制御
器間の動作タイミングを同調させるよう各制御器を構成
することができる。そのような制御器で構成される多重
化制御装置も本発明に含まれる。
In addition to the above-mentioned embodiment, based on the judgment result by the two comparators having different set values, the output of the controller of the own system, and the judgment information of the controller of the other system, the controller among the controllers is determined. Each controller can be configured to synchronize the operation timing. The present invention also includes a multiplex control device including such a controller.

【0031】[0031]

【発明の効果】以上説明したように、本発明によれば、
単一系のプロセス値のみ変化し、単一系の制御器の比較
器が動作した場合でも、常に各制御器の出力信号は同一
タイミングで条件成立/不成立となるので、多重化制御
装置における各制御器間の内部条件を一致させることが
できる。
As described above, according to the present invention,
Even when only the process value of the single system changes and the comparator of the controller of the single system operates, the output signal of each controller always satisfies / is not satisfied at the same timing. It is possible to match the internal conditions between the controllers.

【0032】特に、内部条件により積分動作を開始する
等の制御を行う場合、積分動作開始タイミングを合わせ
ることができるため、内部演算結果に許容値以上の差が
発生することがなく、安定した制御動作を行う信頼性の
高い多重化制御装置を得ることができる。
In particular, when performing control such as starting the integration operation according to internal conditions, the integration operation start timing can be adjusted so that there is no difference in the internal calculation result beyond the allowable value and stable control is achieved. It is possible to obtain a highly reliable multiplexing control device which operates.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の多重化制御装置を示すブロ
ック図である。
FIG. 1 is a block diagram showing a multiplexing controller according to an embodiment of the present invention.

【図2】本発明の他の実施例の多重化制御装置の主要部
分を示す回路である。
FIG. 2 is a circuit showing a main part of a multiplexing controller according to another embodiment of the present invention.

【図3】本発明のさらに他の実施例の多重化制御装置の
主要部分を示す回路である。
FIG. 3 is a circuit showing a main part of a multiplexing controller according to still another embodiment of the present invention.

【図4】多重化制御装置の従来例を示すブロック図であ
る。
FIG. 4 is a block diagram showing a conventional example of a multiplexing control device.

【図5】設定値にヒステリシスのある動作値と復帰値を
持つ比較器の動作を説明する図である。
FIG. 5 is a diagram illustrating an operation of a comparator having an operation value having a hysteresis in a set value and a return value.

【符号の説明】[Explanation of symbols]

3………センサー 9………選択回路 11………被制御器 21………多重化制御装置 23………制御器 25………条件成立用比較器 27………条件不成立用比較器 29………条件成立用判定回路 31………照合回路 41………条件判定回路 43………照合回路 51………照合回路 3 ... Sensor 9 ... Selection circuit 11 ... Controlled device 21 ... Multiplexing control device 23 ... Controller 25 ... Comparator for condition satisfaction 27 ... Comparator for condition failure 29 .... Confirmation circuit for condition establishment 31 ..... Collation circuit 41 .... Condition determination circuit 43 ..... Collation circuit 51 .... Collation circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 プラントの同一ポイントに設置される複
数のセンサーで検出されるプロセス信号それぞれに対
し、前記プロセス信号を条件成立用設定値と比較し条件
成立か否かの判定を行う条件成立用比較器、前記プロセ
ス信号を前記条件成立用設定値と有意差を有する条件不
成立用設定値と比較し条件成立か否かの判定を行う条件
不成立用比較器、および自己の条件成立用比較器の出力
信号と自己の条件不成立用比較器の出力信号と自己の照
合信号と他の条件判定情報とに基づいて条件成立か否か
の照合信号を出力する照合信号出力部を備える複数の制
御器と、 前記複数の制御器からの出力信号に基づいて、前記プラ
ントの操作信号を出力する選択回路とを有することを特
徴とする多重化制御装置。
1. For each of the process signals detected by a plurality of sensors installed at the same point in the plant, the process signal is compared with a set value for satisfying the condition to determine whether the condition is satisfied or not. A comparator, a comparator for condition not fulfilling which judges whether or not the condition is satisfied by comparing the process signal with a set value for condition not fulfilling which is significantly different from the set value for fulfilling the condition, and a comparator for fulfilling its own condition. A plurality of controllers having a collation signal output section for outputting a collation signal indicating whether or not the condition is satisfied based on the output signal, the output signal of the self-condition non-conforming comparator, the self collation signal, and other condition judgment information; And a selection circuit that outputs an operation signal of the plant based on output signals from the plurality of controllers.
【請求項2】 プラントの同一ポイントに設置される複
数のセンサーで検出されるプロセス信号それぞれに対
し、前記プロセス信号を条件成立用設定値と比較し条件
成立か否かの判定を行う条件成立用比較器、前記プロセ
ス信号を前記条件成立用設定値と有意差を有する条件不
成立用設定値と比較し条件成立か否かの判定を行う条件
不成立用比較器、自己の条件成立用比較器の出力信号と
自己の照合信号との論理和からなる条件成立用判定信号
を出力する条件成立用判定回路、および自己の条件成立
用判定回路の出力信号と自己の条件不成立用比較器の出
力信号と他の条件成立用判定回路の出力信号とに基づい
て条件成立か否かの照合信号を出力する照合回路を備え
る複数の制御器と、 前記複数の制御器からの出力信号に基づいて、前記プラ
ントの操作信号を出力する選択回路とを有することを特
徴とする多重化制御装置。
2. For the satisfaction of a condition, for each process signal detected by a plurality of sensors installed at the same point of the plant, the process signal is compared with a set value for satisfaction of the condition to determine whether or not the condition is satisfied. Comparator, Comparing the process signal with the setting value for not satisfying the condition having a significant difference from the setting value for satisfying the condition to determine whether or not the condition is satisfied, output of the comparator for satisfying condition Signal for determining whether the condition is satisfied, which is a logical sum of the signal and its own collation signal, and the output signal of the determination circuit for determining whether the condition is satisfied and the output signal of the comparator for not satisfying the condition Based on the output signal of the determination circuit for condition satisfaction, a plurality of controllers including a verification circuit that outputs a verification signal indicating whether or not the conditions are satisfied, and the controller based on output signals from the plurality of controllers. Multiplexing control apparatus characterized by having a selection circuit for outputting a preparative operation signal.
【請求項3】 プラントの同一ポイントに設置される複
数のセンサーで検出されるプロセス信号それぞれに対
し、前記プロセス信号を条件成立用設定値と比較し条件
成立か否かの判定を行う条件成立用比較器、前記プロセ
ス信号を前記条件成立用設定値と有意差を有する条件不
成立用設定値と比較し条件成立か否かの判定を行う条件
不成立用比較器、自己の条件成立用比較器の出力信号と
自己の照合信号との論理和と自己の条件不成立用比較器
の出力信号との論理積からなる条件判定信号を出力する
条件判定回路、および自己の条件判定回路の出力信号と
他の条件判定回路の出力信号とに基づき条件成立か否か
の照合信号を出力する照合回路を備える複数の制御器
と、 前記複数の制御器からの出力信号に基づいて、前記プラ
ントの操作信号を出力する選択回路とを有することを特
徴とする多重化制御装置。
3. For the satisfaction of a condition, for each process signal detected by a plurality of sensors installed at the same point of the plant, the process signal is compared with a set value for satisfaction of the condition to determine whether or not the condition is satisfied. Comparator, Comparing the process signal with the setting value for not satisfying the condition having a significant difference from the setting value for satisfying the condition to determine whether or not the condition is satisfied, output of the comparator for satisfying condition Condition judgment circuit that outputs a condition judgment signal that is a logical product of the logical sum of the signal and its own collation signal and the output signal of the own condition non-satisfaction comparator, and the output signal of the own condition judgment circuit and other conditions Based on the output signal of the determination circuit, a plurality of controllers including a matching circuit that outputs a matching signal indicating whether or not the condition is satisfied, based on the output signals from the plurality of controllers, the operation signal of the plant Multiplexing control apparatus characterized by having a selection circuit for force.
JP33146792A 1992-12-11 1992-12-11 Multiplex controller Expired - Fee Related JP2696050B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33146792A JP2696050B2 (en) 1992-12-11 1992-12-11 Multiplex controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33146792A JP2696050B2 (en) 1992-12-11 1992-12-11 Multiplex controller

Publications (2)

Publication Number Publication Date
JPH06180601A true JPH06180601A (en) 1994-06-28
JP2696050B2 JP2696050B2 (en) 1998-01-14

Family

ID=18243975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33146792A Expired - Fee Related JP2696050B2 (en) 1992-12-11 1992-12-11 Multiplex controller

Country Status (1)

Country Link
JP (1) JP2696050B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106448776A (en) * 2016-10-10 2017-02-22 中广核工程有限公司 Nuclear power station default value setting system and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106448776A (en) * 2016-10-10 2017-02-22 中广核工程有限公司 Nuclear power station default value setting system and method

Also Published As

Publication number Publication date
JP2696050B2 (en) 1998-01-14

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