JPH06177806A - Power sum fixed agc circuit - Google Patents

Power sum fixed agc circuit

Info

Publication number
JPH06177806A
JPH06177806A JP4325243A JP32524392A JPH06177806A JP H06177806 A JPH06177806 A JP H06177806A JP 4325243 A JP4325243 A JP 4325243A JP 32524392 A JP32524392 A JP 32524392A JP H06177806 A JPH06177806 A JP H06177806A
Authority
JP
Japan
Prior art keywords
level
control signal
received
signal
proportional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4325243A
Other languages
Japanese (ja)
Other versions
JP2952797B2 (en
Inventor
Kazushi Takahashi
一志 高橋
Masayasu Miyake
正泰 三宅
Katsuhiro Asano
勝洋 浅野
Tetsuya Sasaki
哲也 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP4325243A priority Critical patent/JP2952797B2/en
Publication of JPH06177806A publication Critical patent/JPH06177806A/en
Application granted granted Critical
Publication of JP2952797B2 publication Critical patent/JP2952797B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To efficiently perform automatic gain control (AGC) and the maximum ratio synthesization of diversity received waves. CONSTITUTION:Levels (logarithmic values) alpha1 and alpha2 of received waves A and B are detected by logarithmic amplifiers 108 and 109 and with these values as inputs, control signals C1 and C2, which are proportional to a received value level (true value) and fix the sum, are outputted from ROM 203 and 204. Then, AGC is performed by controlling variable attenuators 110 and 111 corresponding to these control signals. Since the amplification factors of respective received waves are proportional to the input levels, the maximum ratio synthesization can be performed by diversity synthesization weighted by the signal levels after the AGC.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ダイバーシチ合成受信
を行うシステム用の、電力和一定自動利得制御回路に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant power sum automatic gain control circuit for a system for diversity combining reception.

【0002】[0002]

【従来の技術】陸上移動通信に於いては、フェージング
による受信電力の低下および波形歪のために符号誤り率
の劣化が生じるので、自動利得制御回路とダイバーシチ
技術による改善が行われる。図3は、このようなフェー
ジング対策を施した従来の受信回路の一部を示したもの
で、スペースダイバーシチによって受信した受信波A、
B(ここでは2波とする)の中心周波数をf0とする
と、これをそれぞれバンドパスフィルタ(BPF)30
1、302によって帯域制限し、信号成分のみを取り出
す。続いて周波数変換器303、304によってそれぞ
れ局部発信器305、306からの周波数f1、f1+Δ
fの単周波信号との差をとって、中心周波数がf0−f
1、f0−(f1+Δf)の中間周波信号に変換し、これ
らを自動利得制御回路(AGC)307で増幅する。こ
こで2つの中間周波信号は、その信号スペクトルが重な
らないように、2つの局部発信器305、306の発信
周波数の差Δfを定めておく。
2. Description of the Related Art In land mobile communications, a reduction in received power due to fading and a deterioration in a code error rate due to waveform distortion occur. Therefore, improvements are made by an automatic gain control circuit and a diversity technique. FIG. 3 shows a part of a conventional receiving circuit in which such a fading countermeasure is taken. The received wave A received by space diversity,
Assuming that the center frequency of B (two waves in this case) is f0, this is respectively a bandpass filter (BPF) 30
The band is limited by 1, 302, and only the signal component is extracted. Subsequently, the frequency converters 303 and 304 respectively generate frequencies f1 and f1 + Δ from the local oscillators 305 and 306, respectively.
By taking the difference from the single frequency signal of f, the center frequency is f0-f
It is converted into an intermediate frequency signal of 1, f0- (f1 + Δf), and these are amplified by an automatic gain control circuit (AGC) 307. Here, the difference Δf between the transmission frequencies of the two local oscillators 305 and 306 is set so that the signal spectra of the two intermediate frequency signals do not overlap.

【0003】図4は、自動利得制御回路307の構成を
示すブロック図で、2つの入力I1、I2はそのまま加算
され、可変利得増幅器401で増幅された後、信号分配
器402で2分される。その一方は検波回路403で検
波され、時定数回路404で平滑されて入力信号I1+
I2の電力に比例した信号が取り出される。この信号は
直流増幅器405で増幅された後、可変利得増幅器40
1に入力されてこの増幅器の増幅率を調整する。このフ
ィードバック回路により、信号分配器402から取り出
された出力信号のレベルは、入力のある域値以上で一定
となるように制御される。
FIG. 4 is a block diagram showing the configuration of the automatic gain control circuit 307. The two inputs I1 and I2 are added as they are, amplified by the variable gain amplifier 401, and then divided by the signal distributor 402. . One of them is detected by the detection circuit 403, smoothed by the time constant circuit 404, and input signal I1 +
A signal proportional to the power of I2 is taken out. This signal is amplified by the DC amplifier 405 and then amplified by the variable gain amplifier 40.
Input to 1 to adjust the amplification factor of this amplifier. By this feedback circuit, the level of the output signal taken out from the signal distributor 402 is controlled so as to be constant above a certain threshold value of the input.

【0004】図3に戻って、可変利得制御回路307の
出力は2分され、それぞれ周波数変換器308、310
へ加えられた局部発信器309、311からの周波数f
2、f2ーΔfの単周波信号によりベースバンド信号a、
bに変換される。ここで
Returning to FIG. 3, the output of the variable gain control circuit 307 is divided into two, and the frequency converters 308 and 310, respectively.
Frequency f from local oscillators 309, 311 added to
2, the baseband signal a by a single frequency signal of f2-Δf,
converted to b. here

【数1】f0=f1+f2 である。## EQU1 ## f0 = f1 + f2.

【0005】上記の構成で、2つの周波数変換器30
3、304がほぼ同一構成のものであれば、自動利得制
御のための増幅器は共用していることから、雑音発生量
は両信号経路とも同一と見なせ、かつ自動利得制御回路
307の入力点における受信波AおよびBのS/N比と
ベースバンド信号aおよびbのS/N比とはほぼ同じで
ある。一方、ダイバーシチ合成は出力S/Nのもっとも
良い最大比合成が通常用いられ、この最大比合成は各受
信波にそのS/N比に比例した重みを乗じて加算するこ
とで行われる。従って、上記のように雑音電力が2つの
信号に対して同じであると、上記ベースバンド信号a、
bに、それらの電力に比例した係数を乗じることによ
り、最大比合成が行える。
With the above structure, two frequency converters 30 are provided.
If 3 and 304 have almost the same configuration, since the amplifier for automatic gain control is shared, the noise generation amount can be regarded as the same in both signal paths, and the input point of the automatic gain control circuit 307 can be considered. The S / N ratios of the received waves A and B and the S / N ratios of the baseband signals a and b are substantially the same. On the other hand, as for diversity combining, maximum ratio combining with the best output S / N is usually used, and this maximum ratio combining is performed by multiplying each received wave by a weight proportional to the S / N ratio and adding. Therefore, if the noise power is the same for the two signals as described above, then the baseband signal a,
Maximum ratio combining can be performed by multiplying b by a coefficient proportional to their power.

【0006】[0006]

【発明が解決しようとする課題】上記した従来の技術で
は、受信波を中間周波数帯へ変換するための局部発信器
と、中間周波数からベースバンドへ変換するための局部
発信器とを、受信波1つごとに1組設ける必要があり、
装置の小型・経済化の点で不利である。また図4の可変
利得増幅器401は、2つの信号の帯域を加えた広帯域
の信号を増幅する広帯域増幅器とする必要があるが、こ
のような広帯域増幅器のゲインを広いレンジで変化させ
るのは容易ではない。
In the above-mentioned conventional technique, a local oscillator for converting a received wave to an intermediate frequency band and a local oscillator for converting an intermediate frequency to a baseband are used. It is necessary to provide one set for each,
It is disadvantageous in terms of downsizing and economy of the device. Further, the variable gain amplifier 401 in FIG. 4 needs to be a wide band amplifier that amplifies a wide band signal obtained by adding two signal bands, but it is not easy to change the gain of such a wide band amplifier in a wide range. Absent.

【0007】このために自動利得制御回路307を2つ
に分けて、各受信波対応に自動利得制御を行えば、これ
らの欠点は除去できるが、この場合には各受信波の受信
レベルが違うと各自動利得制御後の各受信波のレベルは
それらのS/N比とは比例しなくなる。すなわちダイバ
ーシチ合成を、ベースバンド信号レベルに比例した重み
を用いて行っても、この重みはS/N比に比例しないの
で、最大比合成を行うことはできない。
Therefore, if the automatic gain control circuit 307 is divided into two and automatic gain control is performed for each received wave, these drawbacks can be eliminated, but in this case, the received level of each received wave is different. And the level of each received wave after each automatic gain control is no longer proportional to their S / N ratio. That is, even if diversity combining is performed using a weight proportional to the baseband signal level, this weight is not proportional to the S / N ratio, so maximum ratio combining cannot be performed.

【0008】本発明の目的は、その出力レベルに比例し
た重み付けで最大比合成が行え、かつとくに広帯域の可
変利得増幅器を必要としない電力和一定自動利得制御回
路を提供するにある。
It is an object of the present invention to provide a constant power sum automatic gain control circuit which can perform maximum ratio combining by weighting in proportion to its output level and which does not require a variable gain amplifier having a wide band in particular.

【0009】[0009]

【課題を解決するための手段】上記の目的は、ダイバー
シチ受信された複数の受信波の各々をその入力レベルに
応じた増幅率で増幅するための電力一定和自動利得制御
回路に於いて、各受信波のレベルを検出するためのレベ
ル検出手段と、各受信波の制御信号を、該制御信号の和
が一定でかつ上記レベル検出手段により検出された当該
受信波のレベルに比例した値となるように設定するため
の制御信号生成手段と、各受信波を上記制御信号生成手
段により生成された対応制御信号に比例した増幅率で増
幅するための利得可変増幅器とから構成することにより
達成され、また上記制御信号生成手段を、上記検出され
た各受信波のレベルをディジタル化するためのA/D変
換手段と、該手段によりディジタル化されたレベルによ
りアクセスされて上記制御信号に対応するディジタル制
御信号を出力する読み出し専用メモリと、該メモリから
出力されたディジタル制御信号をアナログ値に変換する
ためのD/A変換手段とから構成することにより達成さ
れる。
The above object is to provide a constant power sum automatic gain control circuit for amplifying each of a plurality of diversity-received received waves with an amplification factor according to the input level thereof. The level detection means for detecting the level of the received wave and the control signal of each received wave have a value in which the sum of the control signals is constant and which is proportional to the level of the received wave detected by the level detecting means. And a variable gain amplifier for amplifying each received wave with an amplification factor proportional to the corresponding control signal generated by the control signal generating means. Further, the control signal generating means is accessed by A / D converting means for digitizing the level of each of the detected received waves and the digitized level by the means. A read only memory which outputs a digital control signal corresponding to the serial control signals, is accomplished by a digital control signal output from the memory to configure and a D / A converting means for converting the analog value.

【0010】[0010]

【作用】各受信波の増幅率をその受信レベルに比例した
値とし、かつ各増幅率の和が一定となるように制御する
から、自動利得制御回路出力における各受信波のレベル
とそのS/N比との比は各受信波について一定であり、
したがって自動利得制御回路出力における各受信波レベ
ルに比例した重みでダイバーシチ合成を行えば、最大比
合成を行うことになる。また、制御信号生成に読み出し
専用メモリ(ROM)を利用することで、回路の簡略化
が図れる。
Since the amplification factor of each reception wave is set to a value proportional to the reception level and the sum of the amplification factors is controlled to be constant, the level of each reception wave at the output of the automatic gain control circuit and its S / The ratio with the N ratio is constant for each received wave,
Therefore, if diversity combining is performed with a weight proportional to each received wave level at the output of the automatic gain control circuit, maximum ratio combining is performed. Further, the circuit can be simplified by using the read-only memory (ROM) for generating the control signal.

【0011】[0011]

【実施例】以下、本発明を実施例により詳細に説明す
る。図1は本発明の回路の一実施例を示すもので、従来
例と同様に、2波のスペースダイバーシチ受信を行う場
合を示している。同図において、各受信波A,Bはとも
に中心周波数f0をもち、バンドパスフィルタ(BP
F)101、102によってそれぞれ帯域制限を受けた
のち、1つの局部発振器105からの周波数f1の単周
波信号により周波数変換器103、104にて中心周波
数f0−f1の中間周波数帯の信号に変換される。次にこ
の中間周波数帯の各信号は信号分配器106、107で
それぞれ2分され、その一方が対数増幅器108、10
9で増幅されて制御部200へ入力される。この対数増
幅器(LOG Amp)108、109は、0〜ー70d
bm程度の入力P1およびP2を、それらの対数値、即ちデ
シベル値に比例した2〜0v程度の電圧信号α1、α2に
変換するもので、増幅率制御のための入力レベル検出器
の役割を持っている。ここで
EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 1 shows an embodiment of the circuit of the present invention, and shows the case of performing space diversity reception of two waves as in the conventional example. In the figure, each of the received waves A and B has a center frequency f0, and a band pass filter (BP)
F) After being band-limited by 101 and 102, respectively, a single frequency signal of frequency f1 from one local oscillator 105 is converted by the frequency converters 103 and 104 into an intermediate frequency band signal of center frequency f0-f1. It Next, each signal in this intermediate frequency band is divided into two by signal distributors 106 and 107, one of which is logarithmic amplifier 108, 10.
It is amplified in 9 and input to the control unit 200. The logarithmic amplifiers (LOG Amps) 108 and 109 are 0 to -70d.
It converts the inputs P1 and P2 of about bm into voltage signals α1 and α2 of about 2 to 0 V proportional to their logarithmic value, that is, the decibel value, and has a role of an input level detector for controlling the amplification factor. ing. here

【数2】αi=klog Pi,i=1,2, k:定数 である。## EQU2 ## αi = klog Pi, i = 1, 2, k: a constant.

【0012】図2は制御部200の詳細構成を示したも
ので、入力レベルの検出値α1、α2はA/D変換器20
1、202により8ビットにディジタル化され、それぞ
れバッファメモリ210、211を介してROM20
3、204への読みだし信号として入力される。ROM
203、204から読みだされた信号はそれぞれD/A
変換器205、206と時定数回路212、213でア
ナログ信号に変換されたのち、バッファアンプ214、
215から制御信号C1,C2として出力される。ここで
制御信号C1、C2と入力α1、α2との関係が
FIG. 2 shows the detailed structure of the control unit 200. The detected values α1 and α2 of the input level are the A / D converter 20.
1 and 202 are digitized into 8 bits and are transmitted to the ROM 20 via the buffer memories 210 and 211, respectively.
It is input as a read signal to 3,204. ROM
The signals read from 203 and 204 are respectively D / A
After being converted into an analog signal by the converters 205 and 206 and the time constant circuits 212 and 213, a buffer amplifier 214,
215 outputs the control signals C1 and C2. Here, the relationship between the control signals C1 and C2 and the inputs α1 and α2 is

【数3】 C1=P1/(P1+P2) C2=P2/(P1+P2) となるようにROM203、204の値を設定してお
く。
## EQU00003 ## Values of the ROMs 203 and 204 are set so that C1 = P1 / (P1 + P2) C2 = P2 / (P1 + P2).

【0013】図1へ戻って、制御部200から入力電力
に応じて変化する制御信号C1、C2が出力されると、こ
の制御信号によって可変減衰器(VCA)110、11
1の減衰率が制御され、その出力は入力電力に制御信号
をかけた値に比例する。次にこの出力が増幅器112、
113で増幅され、周波数変換器114、115で局部
発振器116からの周波数f2の単周波信号によりベー
スバンドへ変換されて、ベースバンド信号a、bとな
る。ここで周波数f1、f2 は(数1)の関係を満たす
ものとする。
Returning to FIG. 1, when the control unit 200 outputs control signals C1 and C2 that change according to the input power, the control signals cause the variable attenuators (VCA) 110 and 11 to operate.
An attenuation factor of 1 is controlled and its output is proportional to the input power times the control signal. This output is then the amplifier 112,
The signal is amplified by 113 and is converted by the frequency converters 114 and 115 into a baseband by the single frequency signal of the frequency f2 from the local oscillator 116 to become baseband signals a and b. Here, it is assumed that the frequencies f1 and f2 satisfy the relationship of (Equation 1).

【0014】本実施例によると、(数3)からAccording to this embodiment, from (Equation 3)

【数4】 C1+C2=1 C1/C2=P1/P2 が成り立つので、ベースバンド信号a、bの電力比は受
信波のそれと同じで、その和は一定となる。従ってベー
スバンド信号aおよびbのレベルが各受信波A,BのS
/N比を表しているとして、そのレベルに比例した重み
付けで両者を合成すれば、最大比合成が行える。
Since C1 + C2 = 1 C1 / C2 = P1 / P2 holds, the power ratio of the baseband signals a and b is the same as that of the received wave, and the sum thereof is constant. Therefore, the levels of the baseband signals a and b are S of the received waves A and B, respectively.
Assuming that the / N ratio is represented, the maximum ratio combination can be performed by combining the two with weighting proportional to the level.

【0015】[0015]

【発明の効果】本発明によれば、自動利得制御のための
制御信号を定めるROMをICで構成できるから、回路
構成が簡単になり、自動利得制御と最大比合成によるダ
イバーシチ合成とを併用した受信システムの実現を容易
とすることができる。
According to the present invention, since the ROM for determining the control signal for the automatic gain control can be constructed by the IC, the circuit configuration becomes simple, and the automatic gain control and the diversity combining by the maximum ratio combining are used together. The reception system can be easily realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電力和一定自動利得制御回路の一実施
例を示すブロック図である。
FIG. 1 is a block diagram showing an embodiment of a constant power sum automatic gain control circuit of the present invention.

【図2】図1の制御部の詳細構成図である。FIG. 2 is a detailed configuration diagram of a control unit in FIG.

【図3】従来のダイバーシチ最大比合成と自動利得制御
とを併用したシステムの構成例を示す図である。
FIG. 3 is a diagram showing a configuration example of a system in which conventional maximum diversity ratio combining and automatic gain control are used together.

【図4】図3の自動利得制御回路の構成図である。4 is a configuration diagram of the automatic gain control circuit of FIG.

【符号の説明】[Explanation of symbols]

108 対数増幅器 109 対数増幅器 110 可変減衰器 111 可変減衰器 200 制御部 201 A/D変換器 202 A/D変換器 203 ROM 204 ROM 205 D/A変換器 206 D/A変換器 108 logarithmic amplifier 109 logarithmic amplifier 110 variable attenuator 111 variable attenuator 200 control unit 201 A / D converter 202 A / D converter 203 ROM 204 ROM 205 D / A converter 206 D / A converter

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々木 哲也 東京都港区虎ノ門二丁目3番13号 国際電 気株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tetsuya Sasaki 2-3-3 Toranomon, Minato-ku, Tokyo Kokusai Electric Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ダイバーシチ受信された複数の受信波の
各々をその入力レベルに応じた増幅率で増幅するための
電力一定和自動利得制御回路に於いて、各受信波のレベ
ルを検出するためのレベル検出手段と、各受信波の制御
信号を、該制御信号の和が一定でかつ上記レベル検出手
段により検出された当該受信波のレベルに比例した値と
なるように設定するための制御信号生成手段と、各受信
波を上記制御信号生成手段により生成された対応制御信
号に比例した増幅率で増幅するための利得可変増幅手段
とから成ることを特徴とする電力和一定自動利得制御回
路。
1. A constant power sum automatic gain control circuit for amplifying each of a plurality of diversity-received received waves with an amplification factor according to an input level thereof for detecting the level of each received wave. Control signal generation for setting the level detection means and the control signal of each received wave so that the sum of the control signals is constant and has a value proportional to the level of the received wave detected by the level detection means. And a variable gain amplifying means for amplifying each received wave with an amplification factor proportional to the corresponding control signal generated by the control signal generating means.
【請求項2】 前記制御信号生成手段は、前記検出され
た各受信波のレベルをディジタル化するためのA/D変
換手段と、該手段によりディジタル化されたレベルによ
りアクセスされて前記制御信号に対応するディジタル制
御信号を出力する読みだし専用メモリと、該メモリから
出力されたディジタル制御信号をアナログ値に変換する
ためのD/A変換手段とから構成したことを特徴とする
請求項1記載の電力和一定自動利得制御回路。
2. The control signal generation means is an A / D conversion means for digitizing the level of each of the detected received waves, and the control signal is accessed by the digitized level by the means. 2. A read-only memory for outputting a corresponding digital control signal, and a D / A conversion means for converting the digital control signal output from the memory into an analog value. Automatic gain control circuit with constant power sum.
JP4325243A 1992-12-04 1992-12-04 Automatic gain control circuit with constant power sum Expired - Fee Related JP2952797B2 (en)

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JP4325243A JP2952797B2 (en) 1992-12-04 1992-12-04 Automatic gain control circuit with constant power sum

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JP4325243A JP2952797B2 (en) 1992-12-04 1992-12-04 Automatic gain control circuit with constant power sum

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JPH06177806A true JPH06177806A (en) 1994-06-24
JP2952797B2 JP2952797B2 (en) 1999-09-27

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4810055A (en) * 1986-10-02 1989-03-07 Toray Industries, Inc. Heat resisting plastic optical fiber and method for its manufacture
WO2000039976A1 (en) * 1998-12-25 2000-07-06 Sanyo Electric Co., Ltd. Diversity receiver free from decoding error, and clock regeneration circuit for diversity receiver
JP2003529951A (en) * 1998-11-30 2003-10-07 アイティーティー・マニュファクチュアリング・エンタープライゼズ・インコーポレーテッド Digital broadcasting system and method
JP2008205701A (en) * 2007-02-19 2008-09-04 Matsushita Electric Ind Co Ltd Digital broadcasting receiver and reception control method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01174126A (en) * 1987-12-28 1989-07-10 Nec Corp Signal synthesizing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01174126A (en) * 1987-12-28 1989-07-10 Nec Corp Signal synthesizing circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4810055A (en) * 1986-10-02 1989-03-07 Toray Industries, Inc. Heat resisting plastic optical fiber and method for its manufacture
JP2003529951A (en) * 1998-11-30 2003-10-07 アイティーティー・マニュファクチュアリング・エンタープライゼズ・インコーポレーテッド Digital broadcasting system and method
WO2000039976A1 (en) * 1998-12-25 2000-07-06 Sanyo Electric Co., Ltd. Diversity receiver free from decoding error, and clock regeneration circuit for diversity receiver
US6901124B1 (en) 1998-12-25 2005-05-31 Sanyo Electric Co., Ltd. Diversity receiving apparatus that prevents judgement errors during decoding and a clock generating circuit for a diversity circuit that prevents judgement errors during decoding
JP2008205701A (en) * 2007-02-19 2008-09-04 Matsushita Electric Ind Co Ltd Digital broadcasting receiver and reception control method

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