JPH06176113A - Analysis method for temperature in heating object - Google Patents
Analysis method for temperature in heating objectInfo
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- JPH06176113A JPH06176113A JP4329137A JP32913792A JPH06176113A JP H06176113 A JPH06176113 A JP H06176113A JP 4329137 A JP4329137 A JP 4329137A JP 32913792 A JP32913792 A JP 32913792A JP H06176113 A JPH06176113 A JP H06176113A
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- calculation
- temperature
- elements
- analysis
- temperature rise
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体LSIチップの内
部構造の熱設計などに用いる温度解析方法に係り、特
に、多数の微小な発熱素子を有する物体内部の温度分布
を電子計算機を用いて解析する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temperature analysis method used for thermal design of the internal structure of a semiconductor LSI chip, and in particular, it analyzes the temperature distribution inside an object having a large number of minute heating elements using an electronic computer. On how to do.
【0002】[0002]
【従来の技術】従来の発熱物体内部の温度解析方法とし
ては,例えば,第28回日本伝熱シンポジウム講演論文
集,第3巻,第709頁(平成3年5月発行)に記載の
ように、物体内部を多数の細かい計算要素及び計算節点
に分割し、エネルギ方程式や運動方程式を差分法や有限
要素法により離散化し、計算節点の温度を未知数とした
一次元連立方程式のマトリックスを反復法や直接法によ
り解いていた。計算要素及び計算節点はすべての発熱素
子の近傍の領域を細かく分割していた。2. Description of the Related Art As a conventional method for analyzing the temperature inside a heat-generating object, for example, as described in the 28th Japan Heat Transfer Symposium Proceedings, Volume 3, page 709 (published in May 1991). , The inside of the object is divided into many fine calculation elements and calculation nodes, the energy equation and the motion equation are discretized by the difference method and the finite element method, and the matrix of the one-dimensional simultaneous equations in which the temperature of the calculation node is an unknown number is repeated or It was solved by the direct method. The calculation elements and calculation nodes finely divided the area in the vicinity of all the heating elements.
【0003】[0003]
【発明が解決しようとする課題】上記の従来技術を用い
て、多数の微小な発熱素子を有する物体内部の温度分布
を解析する場合、各々の発熱素子ごとにその近傍の領域
の計算要素及び計算節点を細かく分割しているため、多
数の発熱素子を有する物体の全体の計算要素及び計算節
点の分割数は膨大なものとなり、電子計算機の大記憶容
量を必要とし、また計算時間が長くかかり、計算費用が
大きいという問題があった。When the temperature distribution inside an object having a large number of minute heating elements is analyzed using the above-mentioned conventional technique, the calculation elements and calculation of the area in the vicinity of each heating element are performed. Since the nodes are finely divided, the total number of calculation elements and calculation nodes of an object having a large number of heating elements becomes enormous, which requires a large memory capacity of an electronic computer and also takes a long calculation time. There was a problem that the calculation cost was large.
【0004】本発明の目的は、多数の微小な発熱素子を
有する物体内部の温度分布を解析する場合に、電子計算
機の記憶容量を小さくし、また計算時間を短くするよう
な温度解析方法を提供することにある。An object of the present invention is to provide a temperature analysis method for reducing the storage capacity of an electronic computer and shortening the calculation time when analyzing the temperature distribution inside an object having a large number of minute heating elements. To do.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は理論解析を行い1個の微小な発熱素子で
発熱した熱が物体全体に広がる際の温度上昇分布の計算
式を発熱素子の寸法構造や発熱量の関数としてあらかじ
め求めておく。多数の発熱素子の有する物体の全体を粗
く計算要素及び計算節点で分割し、与えられた発熱条件
及び構造条件に対して、各々の発熱素子からの影響によ
る温度上昇値を前述の計算式を用いて計算し、それを加
え合わせ、与えられた温度境界条件を満足するように補
正することによりすべての発熱素子の影響を含んだ温度
分布を求める。さらに、指定された局所領域についての
み、細かい計算要素及び計算節点の分割を行い、精度の
良い温度分布の解析を行うものである。また、1個の発
熱素子で発熱した時の温度上昇分布の計算式の代わり
に、1個の発熱素子のみで発熱した時の温度上昇分布を
電子計算機の数値解析で求める。また、その際に、1次
元解析,2次元解析,3次元解析を複合して数値解析す
る。In order to achieve the above object, the present invention carries out theoretical analysis to calculate a temperature rise distribution when heat generated by one minute heating element spreads over the entire object. It is obtained in advance as a function of the dimensional structure of the heating element and the amount of heat generation. Roughly divide the entire body of a large number of heating elements by calculation elements and calculation nodes, and use the above formula to calculate the temperature rise value due to the influence of each heating element for given heating and structural conditions. Then, the temperature distribution including the influence of all the heating elements is obtained by correcting the values so as to satisfy the given temperature boundary conditions. Furthermore, only the designated local region is divided into fine calculation elements and calculation nodes to analyze the temperature distribution with high accuracy. Further, instead of the calculation formula of the temperature rise distribution when the heat is generated by one heating element, the temperature rise distribution when the heat is generated by only one heating element is obtained by the numerical analysis of the electronic computer. At that time, numerical analysis is performed by combining one-dimensional analysis, two-dimensional analysis and three-dimensional analysis.
【0006】[0006]
【作用】多数の発熱素子を有する物体の全体を細い計算
要素及び計算節点で分割することがないため、計算機の
記憶容量が小さくてすむ。また、多数の発熱素子の有す
る物体の温度分布計算は、あらかじめ求めておいた計算
式あるいは数値解析結果を用いた計算と、その加え合わ
せ、その補正により計算するものであり、計算時間が短
く、計算費用を安くすることができる。さらに、必要と
する局所領域については精度の良い温度分布を求めるこ
とができる。Since the whole body having a large number of heating elements is not divided by thin calculation elements and calculation nodes, the storage capacity of the computer can be small. Further, the temperature distribution calculation of an object having a large number of heating elements is a calculation using a calculation formula or a numerical analysis result which has been obtained in advance, and in addition, the calculation is performed by the correction, and the calculation time is short, The calculation cost can be reduced. Furthermore, a highly accurate temperature distribution can be obtained for the required local region.
【0007】[0007]
【実施例】以下、本発明の一実施例を図1から図11に
より説明する。ここでは、動作時の半導体LSIチップ
内部の温度分布を解析する例について説明する。図3は
LSIチップの一部分(領域の寸法が100μm×60
μm)の電子デバイス配置の平面図である。図4は図3
に示したI−I断面の断面図である。電子デバイスの中
で主な発熱素子として、トランジスタ素子1,2と抵抗
素子3がある。図3の場合には、29個の発熱素子があ
る。トランジスタ素子として、シリコン基板4の表層部
に直接に形成した素子1とシリコン基板4の表層部にお
いてSiO2 絶縁膜5で囲んだシリコン直方体領域6の
内部に形成した素子2の2種類がある。抵抗素子3はS
iO2 絶縁膜7の中に形成されている。それらの上層に
は多層のアルミ配線層8が形成されている。図5はLS
Iチップを冷却構造物に組み込んだ状態の垂直断面図を
示す。LSIチップ9は冷却構造物10を有するパッケ
ージ11の内部に収納し、ボ−ド12に取り付ける。図
4のシリコン基板4の上面が、図5のLSIチップ9の
下面13に対応しており、発熱素子1,2,3で発生し
た熱は、シリコン基板4の内部を熱伝導し、冷却構造物
10に伝わり、空気中に放熱される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Here, an example of analyzing the temperature distribution inside the semiconductor LSI chip during operation will be described. FIG. 3 shows a part of an LSI chip (area size is 100 μm × 60
FIG. 3 is a plan view of an electronic device arrangement of μm). 4 is shown in FIG.
It is sectional drawing of the II cross section shown in FIG. The main heating elements in the electronic device are the transistor elements 1 and 2 and the resistance element 3. In the case of FIG. 3, there are 29 heating elements. There are two types of transistor elements: an element 1 formed directly on the surface layer portion of the silicon substrate 4 and an element 2 formed inside a silicon rectangular parallelepiped region 6 surrounded by the SiO 2 insulating film 5 on the surface layer portion of the silicon substrate 4. The resistance element 3 is S
It is formed in the iO 2 insulating film 7. A multilayer aluminum wiring layer 8 is formed above them. Figure 5 is LS
The vertical cross-sectional view of the state which assembled the I chip in the cooling structure is shown. The LSI chip 9 is housed inside a package 11 having a cooling structure 10 and attached to a board 12. The upper surface of the silicon substrate 4 of FIG. 4 corresponds to the lower surface 13 of the LSI chip 9 of FIG. 5, and the heat generated in the heating elements 1, 2, and 3 is conducted to the inside of the silicon substrate 4, and the cooling structure is obtained. It is transmitted to the object 10 and radiated into the air.
【0008】このようなLSIチップ内部の温度分布を
電子計算機を用いて計算する場合の解析方法を次に示
す。図6に本実施例の解析方法のフロ−チャートを示
す。ステップ1:作業者は、計算対象の構造,物性値,
境界条件,発熱条件,詳細な解析を必要とする局所領域
の位置のデ−タを電子計算機に入力する。ステップ2:
電子計算機の内部で解析領域を自動的に計算要素及び計
算節点に分割する。図1は計算要素及び計算節点に分割
した後の平面図、図2は図1に示したI−I断面の垂直
断面図である。解析領域の全体を各方向に5等分に粗く
分割した計算節点14と詳細な解析を必要とする局所領
域15の内部について細かく分割した計算節点16と、
入力した発熱素子1,2,3の周囲の節点17を合わせ
て、全体の計算節点とする。なお、電子デバイスの位置
はすべてシリコン基板の表面位置とし、その厚さを無視
する。全体の温度分布にほとんど影響しないアルミ配線
層8を無視する。ステップ3:詳細を後述するように、
あらかじめ、1個の微小な発熱素子で発熱した熱が大き
な物体内部の全体に熱伝導で広がる際の温度分布の計算
式を発熱量や素子寸法の関数として求めておく。各節点
における温度上昇値は、その計算式を用い、すべての発
熱素子からの影響を加え合わせて計算する。ステップ
4:詳細を後述するように、各節点における温度上昇値
を用い、境界条件を満足するように各節点の温度を計算
する。ステップ5:詳細な解析を必要とする局所領域の
内部で、有限要素法や差分法を用いた精度の良い解析を
行う。この解析において、上記の方法で求めた局所領域
の周囲の温度を境界条件に用いる。ステップ6:最後に
計算結果を出力する。An analysis method for calculating such a temperature distribution inside the LSI chip by using an electronic computer will be described below. FIG. 6 shows a flow chart of the analysis method of this example. Step 1: The worker determines the structure to be calculated, the physical property value,
Boundary conditions, heat generation conditions, and local region position data that require detailed analysis are input to a computer. Step 2:
The analysis area is automatically divided into calculation elements and calculation nodes inside the electronic computer. FIG. 1 is a plan view after division into calculation elements and calculation nodes, and FIG. 2 is a vertical cross-sectional view of the I-I section shown in FIG. Computational nodes 14 that are roughly divided into five equal parts in each direction, and computational nodes 16 that are finely divided inside the local region 15 that requires detailed analysis,
The nodes 17 around the input heating elements 1, 2 and 3 are combined to make a total calculation node. All electronic device positions are on the surface of the silicon substrate, and their thickness is ignored. Ignore the aluminum wiring layer 8 that has little effect on the overall temperature distribution. Step 3: As detailed below,
In advance, a calculation formula of a temperature distribution when heat generated by one minute heating element spreads through heat conduction throughout a large object is obtained as a function of the amount of heat generation and the element size. The temperature rise value at each node is calculated by using the calculation formula and adding the influences from all the heating elements. Step 4: As will be described later in detail, the temperature increase value at each node is used to calculate the temperature at each node so as to satisfy the boundary condition. Step 5: Perform accurate analysis using a finite element method or a difference method inside a local region that requires detailed analysis. In this analysis, the temperature around the local region obtained by the above method is used as the boundary condition. Step 6: Finally, output the calculation result.
【0009】1個の微小な発熱素子で発熱した熱が物体
内部の全体に広がる際の温度上昇値の計算式と、すべて
の発熱素子からの影響を加え合わせる計算について次に
説明する。図7に示すように、微小な発熱素子18が無
限物体4の表面の半球形状であり、発熱量がQ(W)と
すると、その素子から距離r(m)だけ離れた位置の温
度が発熱素子の影響によって温度上昇する値ΔT(℃)
は、理論解析により次式で計算される。A formula for calculating a temperature rise value when heat generated by one minute heating element spreads throughout the object and a calculation for adding influences from all the heating elements will be described below. As shown in FIG. 7, if the minute heating element 18 has a hemispherical shape on the surface of the infinite object 4 and the heat generation amount is Q (W), the temperature at a position separated by a distance r (m) from the element generates heat. Value that temperature rises due to the influence of the element ΔT (℃)
Is calculated by the following formula by theoretical analysis.
【0010】[0010]
【数1】 [Equation 1]
【0011】ここで、kはシリコン基板の材料の熱伝導
率(W/mK)、πは円周率である。Here, k is the thermal conductivity (W / mK) of the material of the silicon substrate, and π is the circular constant.
【0012】発熱素子の内部に入らない位置の節点につ
いて、すべての発熱素子の影響を加え合わせた温度上昇
値は次式となる。For a node at a position that does not enter the inside of the heating element, the temperature rise value obtained by adding the effects of all the heating elements is given by the following equation.
【0013】[0013]
【数2】 [Equation 2]
【0014】ここで、i=1〜Nは各発熱素子の番号で
あり、Qiは各発熱素子の発熱量(W)、riは各発熱
素子からの距離(m)である。Here, i = 1 to N are the numbers of the heating elements, Qi is the heat generation amount (W) of each heating element, and ri is the distance (m) from each heating element.
【0015】微小な発熱素子がシリコン基板の表層部に
直接に形成したトランジスタ素子1のように、図8の直
方体形状19の発熱素子の内部に入る位置の節点におけ
る、すべての発熱素子の影響を加え合わせた温度上昇値
は次式となる。Like the transistor element 1 in which minute heating elements are formed directly on the surface layer of the silicon substrate, the influence of all the heating elements at the node where the heating elements having the rectangular parallelepiped shape 19 in FIG. The added temperature rise value is given by the following equation.
【0016】[0016]
【数3】 [Equation 3]
【0017】ここで、jは自分自身の発熱素子の番号、
a,b,cはその発熱素子の縦,横,高さ(m)であ
る。Where j is the number of the heating element of its own,
a, b, and c are the length, width, and height (m) of the heating element.
【0018】微小な発熱素子がSiO2 絶縁膜で囲んだ
シリコン直方体領域6の内部に形成したトランジスタ素
子2のように、図9の直方体形状19の発熱素子の内部
に入る位置の節点における、すべての発熱素子の影響を
加え合わせた温度上昇値は次式となる。Like the transistor element 2 in which a minute heating element is formed inside the silicon rectangular parallelepiped region 6 surrounded by the SiO 2 insulating film, all of the nodes at the positions inside the rectangular parallelepiped shape 19 heating element shown in FIG. The temperature rise value, which is obtained by adding the influence of the heating element of, is given by the following equation.
【0019】[0019]
【数4】 [Equation 4]
【0020】ここで、KはSiO2 絶縁膜の材料の熱伝
導率(W/mK)、l,m,nはシリコン直方体領域6
の縦,横,高さ(m)、tは絶縁膜の厚さ(m)であ
る。Here, K is the thermal conductivity (W / mK) of the material of the SiO 2 insulating film, and l, m, and n are silicon rectangular parallelepiped regions 6
The vertical, horizontal, and height (m), and t are the thickness (m) of the insulating film.
【0021】微小な発熱素子がSiO2 絶縁膜の中の抵
抗素子3のように、図10の直方体形状19の発熱素子
の内部に入る位置の節点における、すべての発熱素子の
影響を加え合わせた温度上昇値は次式となる。Like the resistance element 3 in the SiO 2 insulating film, the effect of all the heat generating elements at the node where the minute heat generating element enters the inside of the heat generating element of the rectangular parallelepiped shape 19 in FIG. 10 is added. The temperature rise value is given by the following equation.
【0022】[0022]
【数5】 [Equation 5]
【0023】ここで、tは発熱素子の底部の絶縁膜の厚
さ(m)である。Here, t is the thickness (m) of the insulating film at the bottom of the heating element.
【0024】以上の計算式を用いると、各節点におけ
る、すべての発熱素子からの影響を加え合わせた温度上
昇値を計算することができる。By using the above formula, it is possible to calculate the temperature rise value in which the influences from all the heating elements are added together at each node.
【0025】各節点における温度上昇値を用い、境界条
件を満足するように各節点の温度を計算する方法につい
て次に説明する。境界条件として、指定した面の温度を
固定する場合には、次のようにする。前記の計算式を用
いて、指定した面に含まれるすべての節点の平均温度上
昇値を計算し、固定温度との差を補正温度差とする。そ
の補正温度差をすべての節点における温度上昇値に加え
て、各節点の温度を計算できる。A method of calculating the temperature of each node so as to satisfy the boundary condition by using the temperature rise value at each node will be described below. As a boundary condition, if you want to fix the temperature of the specified surface, do as follows. The average temperature rise value of all the nodes included in the specified surface is calculated using the above calculation formula, and the difference from the fixed temperature is taken as the corrected temperature difference. The temperature difference at each node can be calculated by adding the corrected temperature difference to the temperature rise values at all nodes.
【0026】境界条件として、指定した面の熱伝達率を
固定する場合には、次のようにする。指定した面の温度
は、次の式で求まる。As a boundary condition, when the heat transfer coefficient of the designated surface is fixed, the following is performed. The temperature of the specified surface is calculated by the following formula.
【0027】[0027]
【数6】 [Equation 6]
【0028】ここで、Qiは各発熱素子の発熱量
(W)、Tsは冷却空気温度(℃)、Aは指定した面の
面積(m2)αは熱伝達率(W/m2K)である。あと
は、指定した面の温度をこの式で求まる温度に固定する
場合と同じである。Here, Qi is the heat generation amount (W) of each heating element, Ts is the cooling air temperature (° C.), A is the designated surface area (m 2 ) α is the heat transfer coefficient (W / m 2 K). Is. The rest is the same as when fixing the temperature of the specified surface to the temperature obtained by this formula.
【0029】境界条件として、指定した面を断熱面とす
る場合には、次のようにする。指定した面を対称面とし
て、反対側にも仮想の物体を考え、仮想の物体の中にあ
る発熱素子からの影響も加え合わせて温度上昇値を計算
することにより、各節点の温度を計算できる。As a boundary condition, when the designated surface is to be an adiabatic surface, the following is performed. The temperature of each node can be calculated by considering the virtual surface on the opposite side with the specified surface as the symmetry surface and calculating the temperature rise value by adding the influence from the heating element in the virtual surface. .
【0030】本実施例による半導体LSIチップ内部の
温度分布を解析した結果の例を図11に示す。図3,図
4に示した構造を対象とし、境界条件としてシリコン基
板の下面の温度を20℃に固定した。FIG. 11 shows an example of the result of analyzing the temperature distribution inside the semiconductor LSI chip according to this embodiment. Targeting the structures shown in FIGS. 3 and 4, the temperature of the lower surface of the silicon substrate was fixed at 20 ° C. as a boundary condition.
【0031】次に本実施例の効果を示す。図1は本発明
を適用し、計算要素及び計算節点に分割した後の平面図
である。図12は同じ計算対象について、従来技術によ
る計算要素及び計算節点に分割した後の平面図である。
本発明により計算要素及び計算節点の分割数を大幅に低
減できることがわかる。Next, the effect of this embodiment will be shown. FIG. 1 is a plan view after applying the present invention and dividing into calculation elements and calculation nodes. FIG. 12 is a plan view after the same calculation target is divided into calculation elements and calculation nodes according to the related art.
It can be seen that the present invention can significantly reduce the number of divisions of calculation elements and calculation nodes.
【0032】以上の説明は温度分布計算について示した
が、速度分布計算や応力計算の場合にも、同様の解析方
法が適用される。Although the above description has been made with reference to the temperature distribution calculation, the same analysis method can be applied to velocity distribution calculation and stress calculation.
【0033】本発明の第2の実施例を図13,図14に
より説明する。図13はLSIチップの一部分で同じ構
造のトランジスタ素子が複数個で並列した場合の断面斜
視図である。シリコン基板4の表層部においてSiO2
絶縁膜5で囲んだシリコン直方体領域6の内部に形成し
たトランジスタ素子2が形成されている。このようなL
SIチップ内部の温度分布を電子計算機を用いて計算す
る場合の解析方法を次に示す。図14に本実施例の解析
方法のフロ−チャートを示す。ステップ1:作業者は、
解析に必要なデ−タを電子計算機に入力する。ステップ
2:電子計算機の内部で、1個の微小な発熱素子がシリ
コン基板にある場合について、1個の発熱素子の近傍の
みを細かく計算要素及び計算節点に分割する。ステップ
3:有限要素法を用いた数値解析で、1個の微小な発熱
素子のみ発熱した時の温度上昇分布を計算する。素子構
造が異なる発熱素子についてその1個の発熱素子が発熱
した時の温度上昇分布を求める数値解析を繰返す。ステ
ップ4:各節点における温度上昇値は、その計算結果を
用い、すべての発熱素子からの影響を加え合わせて計算
する。その際、素子構造が同じものについては、数値解
析で求めた温度上昇値が素子の発熱量に比例するとして
計算する。ステップ5:各節点における温度上昇値を用
い、境界条件を満足するように各節点の温度を計算し、
最後に計算結果を出力する。A second embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a cross-sectional perspective view when a plurality of transistor elements having the same structure are arranged in parallel in a part of an LSI chip. In the surface layer portion of the silicon substrate 4, SiO 2
The transistor element 2 formed inside the silicon rectangular parallelepiped region 6 surrounded by the insulating film 5 is formed. L like this
An analysis method for calculating the temperature distribution inside the SI chip by using an electronic computer will be described below. FIG. 14 shows a flow chart of the analysis method of this example. Step 1: The worker
Input the data required for analysis into the computer. Step 2: Inside the electronic computer, when one minute heating element is present on the silicon substrate, only the vicinity of one heating element is finely divided into calculation elements and calculation nodes. Step 3: Calculate the temperature rise distribution when only one minute heating element generates heat by numerical analysis using the finite element method. Numerical analysis for obtaining the temperature rise distribution when one heating element generates heat is repeated for heating elements having different element structures. Step 4: The temperature rise value at each node is calculated by using the calculation result and adding the influences from all the heating elements. At that time, in the case where the element structure is the same, it is calculated that the temperature rise value obtained by the numerical analysis is proportional to the heat generation amount of the element. Step 5: Using the temperature rise value at each node, calculate the temperature of each node so as to satisfy the boundary condition,
Finally, the calculation result is output.
【0034】本発明の第3の実施例を次に説明する。図
3と図4に示したLSIチップ内部の温度分布を電子計
算機を用いて計算する場合の解析方法を次に示す。本実
施例では、計算対象を三つの領域群に分け、各々の領域
群について、1次元解析,2次元解析,3次元解析を適
用する。微小な発熱素子がシリコン基板の表層部に直接
に形成したトランジスタ素子1の近傍の領域は、発熱素
子を中心として半径方向に広がる1次元解析を行う。微
小な発熱素子がSiO2 絶縁膜で囲んだシリコン直方体
領域6の内部に形成したトランジスタ素子2の近傍の領
域は、3次元解析を行う。抵抗素子3の発熱素子の近傍
の領域は、細長い発熱素子を中心軸として半径方向に広
がる2次元解析を行う。シリコン基板の表層部について
は3次元解析を行う。シリコン基板の表層部から離れた
位置から下面までの領域については深さ方向の1次元解
析を行う。1次元解析,2次元解析,3次元解析を複合
して計算対象の全体を同時に数値解析する。本実施例に
よれば、計算対象の全体を3次元解析のための細かい計
算要素及び計算節点で分割することがないため、計算要
素及び計算節点の分割数を低減できる。A third embodiment of the present invention will be described next. An analysis method for calculating the temperature distribution inside the LSI chip shown in FIGS. 3 and 4 using an electronic computer will be described below. In this embodiment, the calculation target is divided into three area groups, and one-dimensional analysis, two-dimensional analysis and three-dimensional analysis are applied to each area group. A region in the vicinity of the transistor element 1 in which minute heating elements are directly formed on the surface layer of the silicon substrate is subjected to a one-dimensional analysis that spreads in the radial direction with the heating elements as the center. A three-dimensional analysis is performed on a region in the vicinity of the transistor element 2 formed inside the silicon rectangular parallelepiped region 6 in which the minute heating element is surrounded by the SiO 2 insulating film. A region of the resistance element 3 in the vicinity of the heating element is subjected to a two-dimensional analysis that spreads in the radial direction with the elongated heating element as the central axis. Three-dimensional analysis is performed on the surface layer of the silicon substrate. One-dimensional analysis in the depth direction is performed on the region from the position away from the surface layer of the silicon substrate to the lower surface. Simultaneous numerical analysis of the entire calculation target by combining 1-dimensional analysis, 2-dimensional analysis and 3-dimensional analysis. According to the present embodiment, the whole calculation target is not divided by fine calculation elements and calculation nodes for three-dimensional analysis, so that the number of divisions of calculation elements and calculation nodes can be reduced.
【0035】[0035]
【発明の効果】本発明によれば、多数の発熱素子を有す
る物体の全体を細かい計算要素及び計算節点で分割する
ことがないため、計算要素及び計算節点の分割数を大幅
に低減でき、計算機の記憶容量が小さくてすむ。また、
多数の発熱素子の有する物体の温度分布計算は、あらか
じめ求めておいた計算式あるいは数値解析結果を用いた
計算、その加え合わせ、その補正により計算するもので
あり、計算時間が短く、計算費用を安くすることがで
き、早く計算結果を得ることができる。According to the present invention, since the whole body having a large number of heating elements is not divided by fine calculation elements and calculation nodes, the number of divisions of calculation elements and calculation nodes can be greatly reduced, and the computer The storage capacity of is small. Also,
To calculate the temperature distribution of an object with many heating elements, the calculation formulas or numerical analysis results that have been obtained in advance are used, their additions are made, and the corrections are made. It can be cheaper and the calculation result can be obtained quickly.
【図1】本発明の第1の実施例の計算要素及び計算節点
の平面図。FIG. 1 is a plan view of calculation elements and calculation nodes according to a first embodiment of this invention.
【図2】図1のI−I断面の断面図。FIG. 2 is a cross-sectional view taken along the line II of FIG.
【図3】LSIチップの一部分の電子デバイス配置の平
面図。FIG. 3 is a plan view of an electronic device arrangement of a part of an LSI chip.
【図4】図3のI−I矢視断面図。FIG. 4 is a cross-sectional view taken along the line II of FIG.
【図5】LSIチップ冷却構造物の断面図。FIG. 5 is a sectional view of an LSI chip cooling structure.
【図6】第1の実施例の解析方法のフロ−チャート。FIG. 6 is a flowchart of the analysis method of the first embodiment.
【図7】半球形状の発熱素子を示す説明図。FIG. 7 is an explanatory diagram showing a hemispherical heating element.
【図8】基板に直接に形成した直方体形状の発熱素子を
示す説明図。FIG. 8 is an explanatory diagram showing a rectangular parallelepiped heating element formed directly on a substrate.
【図9】絶縁膜で囲んだ内部に形成した直方体形状の発
熱素子を示す説明図。FIG. 9 is an explanatory diagram showing a rectangular parallelepiped-shaped heating element formed inside an insulating film.
【図10】絶縁膜の中に形成した直方体形状の発熱素子
を示す説明図。FIG. 10 is an explanatory diagram showing a rectangular parallelepiped heating element formed in an insulating film.
【図11】温度分布の解析結果を示す斜視図。FIG. 11 is a perspective view showing an analysis result of temperature distribution.
【図12】従来技術の計算要素及び計算節点の平面図。FIG. 12 is a plan view of a conventional calculation element and calculation node.
【図13】LSIチップの一部分の断面斜視図。FIG. 13 is a cross-sectional perspective view of a part of an LSI chip.
【図14】第2の実施例の解析方法のフロ−チャート。FIG. 14 is a flowchart of the analysis method of the second embodiment.
1,2…トランジスタ素子、3…抵抗素子、4…シリコ
ン基板、5,7…SiO2 絶縁膜、6…シリコン直方体
領域、9…LSIチップ。1,2 ... transistor elements 3 ... resistance element, 4 ... silicon substrate, 5, 7 ... SiO 2 insulating film, 6 ... silicon cuboid region, 9 ... LSI chip.
Claims (1)
計算対象とし、前記計算対象を多数の計算要素及び計算
節点に分割し、電子計算機を用いた温度分布の数値解析
において、最初に1個の発熱素子が発熱した時の温度上
昇分布を求め、次にその温度上昇分布を用いて複数の発
熱素子が同時に発熱した場合の温度分布を求めることを
特徴とする発熱物体内部の温度解析方法。1. A solid or fluid containing a plurality of heating elements inside is a calculation object, and the calculation object is divided into a large number of calculation elements and calculation nodes, and in a numerical analysis of temperature distribution using an electronic computer, first, A temperature analysis inside a heating object, characterized in that a temperature rise distribution when one heating element generates heat is obtained, and then a temperature distribution when a plurality of heating elements simultaneously generate heat is obtained using the temperature rise distribution. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4329137A JPH06176113A (en) | 1992-12-09 | 1992-12-09 | Analysis method for temperature in heating object |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4329137A JPH06176113A (en) | 1992-12-09 | 1992-12-09 | Analysis method for temperature in heating object |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06176113A true JPH06176113A (en) | 1994-06-24 |
Family
ID=18218049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4329137A Pending JPH06176113A (en) | 1992-12-09 | 1992-12-09 | Analysis method for temperature in heating object |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06176113A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007083535A1 (en) * | 2006-01-23 | 2007-07-26 | Matsushita Electric Industrial Co., Ltd. | Device, method and program for predicting housing surface temperature, and recording medium |
JP2008275579A (en) * | 2007-04-05 | 2008-11-13 | Sharp Corp | Heat conductivity computing method, heat conductivity computing device, heat conductivity computing program, thermal analysis method, thermal analysis device and thermal analysis program |
JP2014059238A (en) * | 2012-09-18 | 2014-04-03 | Kajima Corp | Thermal analysis device and thermal analysis method and thermal analysis program |
CN111044167A (en) * | 2018-10-12 | 2020-04-21 | 维谛技术有限公司 | Method and device for determining temperature of capacitor core |
-
1992
- 1992-12-09 JP JP4329137A patent/JPH06176113A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007083535A1 (en) * | 2006-01-23 | 2007-07-26 | Matsushita Electric Industrial Co., Ltd. | Device, method and program for predicting housing surface temperature, and recording medium |
GB2450259A (en) * | 2006-01-23 | 2008-12-17 | Matsushita Electric Ind Co Ltd | Device,method and program for predicting housing surface temperature,and recording medium |
JP2008275579A (en) * | 2007-04-05 | 2008-11-13 | Sharp Corp | Heat conductivity computing method, heat conductivity computing device, heat conductivity computing program, thermal analysis method, thermal analysis device and thermal analysis program |
JP2014059238A (en) * | 2012-09-18 | 2014-04-03 | Kajima Corp | Thermal analysis device and thermal analysis method and thermal analysis program |
CN111044167A (en) * | 2018-10-12 | 2020-04-21 | 维谛技术有限公司 | Method and device for determining temperature of capacitor core |
CN111044167B (en) * | 2018-10-12 | 2021-10-26 | 维谛技术有限公司 | Method and device for determining temperature of capacitor core |
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