JPH06175926A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a CPU system in which it is possible to facilitate a countermeasure to a wide range application by the same hardware by varying the capacity distribution of a synchronizing memory among a cache memory, cache tag memory, and high speed memory. CONSTITUTION:This device is equipped with a decoder 18 which decodes the combination of the 2 bits of instruction signals SEL1 and SEL0 from an outside, and bus switches which switch memories 81-84 to be connected with the buses of a CPU 1 according to the decoded result of the decoder 18, and decide the memory among the memories 81-84 to be assigned as the high speed memory, and the residual memories to be assigned as the cache memory and the cache tag memory. Then, the synchronizing memory which supplies a command to the CPU 1 synchronously with the operation clock of the CPU 1, or transfers data is prepared as the memories 81-84. The function can be changed according to the instruction signals SEL1 and SEL0 from the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU system having a hierarchical memory, and more particularly to an improved CPU / memory interface.

[0002]

2. Description of the Related Art FIG. 10 shows an example of a conventional CPU system of this type. This conventional example is a typical hierarchical memory system, which uses a small-capacity high-speed memory as a cache of a large-capacity low-speed memory. In FIG. 10, reference numeral 1 is a CPU, 2 is a low-speed memory system for storing instructions to be executed by the CPU, data to be processed, etc., and is generally composed of an inexpensive memory such as a DRAM with a unit cost per bit. A cache memory 3 stores a part of the information stored in the low-speed memory system 2, and is generally composed of a high-speed memory having a high bit unit price such as SRAM. 4 is a cache tag memory that stores address information indicating which address of the low-speed memory system 2 the information stored in the cache memory 3 corresponds to, 5 is a cache memory controller that controls the cache memory 3 and the cache tag memory 4, Reference numerals 51, 52 and 53 are circuits built in the cache memory controller 5, 51 is a gate for inputting the upper address information AddHi from the cache tag memory 4 under the control of the / RD signal output from the CPU 1, and 52 is output by the CPU 1. A gate for outputting the upper address information AddHi to the cache tag memory 4 under the control of the / WR signal, and 53 compares the upper address in the address ADDR output by the CPU 1 with the upper address AddHi stored in the cache tag memory, and Key indicating whether or not Cash hit signal
It is a comparator that outputs Hit.

Next, the operation will be described. The cache memory 3 is mapped with a part of the contents of the low-speed memory system 2, and the cache tag memory 4 has address information indicating to which part of the low-speed memory system 2 the contents held in the cache memory 3 correspond. Holding

When the CPU 1 reads an instruction or data, the CPU 1 fetches the contents of the cache memory 3 into the CPU 1 in synchronization with its operation clock and the contents of the cache tag memory 4 in the cache memory controller 5.
Take in. Contents of cache tag memory 4 and CPU 1
If the information of the address output by the CPU 1 matches, the CPU 1 continues the process by using the fetched contents of the cache memory 3. If the contents of the cache tag memory 4 do not match the address information output by the CPU 1, the CPU 1 suspends the process and reads the contents of the low-speed memory system 2.
The read data is written in the cache memory 3,
The address is also written in the cache tag memory 4.

On the other hand, when the CPU 1 writes data, the CPU 1 requests the low speed memory system 2 to write the data at the same time as writing the data to the cache memory 3 and the address to the cache tag memory 4. When the low speed memory system 2 can accept the write request of the CPU, the CPU 1 continues the process of writing the data to the low speed memory system 2. If the low-speed memory system 2 cannot accept the write request from the CPU 1, the CPU 1 suspends the process until the write request can be accepted.

As described above, the hierarchical memory system has a CP
This is a method for realizing a memory that looks high speed and has a large capacity by utilizing that the address referenced by U is local in terms of time and space, and is small between the CPU and the large capacity low speed memory. By providing a high-capacity high-speed memory and using this small-capacity high-speed memory as a cache of a large-capacity low-speed memory, the access gap between the both is filled, and it is as if the high-speed and large-capacity memory actually exists for the CPU. It is a technique that can be shown.

However, in this method,

(1) When there is no instruction or data that the CPU wants to read in the cache memory, the performance is deteriorated because the low-speed memory system reads.

(2) It is impossible to predict whether there is an instruction or data that the CPU wants to read in the cache memory, so the processing time cannot be clearly defined. This is an obstacle for real-time processing systems.

(3) In the case of writing, if the writing request of the low-speed memory system cannot be accepted, the processing of the CPU is suspended and the performance deteriorates. This deteriorates the response such as the exception processing which needs to save the contents of the CPU at high speed.

(4) Further, when the cache is of the write-through type, the write data is written to the cache and is transferred to the low-speed memory system at the same time, so the bus usage rate of the low-speed memory system becomes high.

There are problems such as However, the present inventor has already developed a system capable of simultaneously solving various problems of such a hierarchical memory system.

FIG. 5 shows a conventional CPU system described in the specification filed as Japanese Patent Application No. 4-83362 already developed by the present inventor. This CPU system has a normal hierarchical memory system composed of a low-speed memory and a cache memory, a high-speed memory that operates at the same timing as the cache memory, and a high-speed memory when the CPU exchanges instructions and data with the high-speed memory. When the CPU accesses the high-speed memory by additionally providing a decoder for determining whether or not it has been accessed, the CPU accesses only the high-speed memory area and the CPU accesses the area other than the high-speed memory. In this case, it can operate like a normal hierarchical memory.

In the figure, 1 is a CP for executing data processing in accordance with a series of instructions described as a program.
U and 2 are low-speed memory systems that store instructions to be executed by the CPU, data to be processed, etc.
Generally, the memory is configured with a low bit unit price. 3 is a cache memory that stores a part of the information stored in the low-speed memory system 2, and this is a cache memory.
Generally, it is composed of a memory such as a RAM, which has a high unit price of bits but can be accessed at high speed. 4 is a cache tag memory that stores address information indicating which address in the low-speed memory system 2 the information stored in the cache memory 3 corresponds to, and 6 is a high-speed memory that operates at the same timing as the cache memory 3. This has the same access speed and the same capacity as the cache memory 3.

Further, 8 is a decoder which decodes the upper address output from the CPU 1 and controls the chip selection input / CE of the cache memory 3 and the cache tag memory 4, and 9 is a high-speed signal obtained by inverting the signal HSEL output from the decoder 8. Outputs memory selection signal / HSEL, and uses this high-speed memory selection signal / HSEL to select chip of high-speed memory 6 / CE
7 is a synchronous memory controller for controlling the cache memory 3, the cache tag memory 4 and the high speed memory 6, and 71 is for controlling the / RD signal output from the CPU 1 to output the upper address information AddHi from the cache tag memory 4. Input gate, 72 is CPU
1 is a gate for outputting the upper address information AddHi to the cache tag memory 4 under the control of the / WR signal, and 73 is a higher address in the address ADDR output by the CPU 1 and an upper address AddHi stored in the cache tag memory. When a comparison is made, a cache hit signal Hit indicating whether or not they match is output, and when the high-speed memory 6 is in the chip selection state by the high-speed memory selection signal / HSEL output from the inverter 9, the outputs are matched. It is a comparator that has the function of fixing the state.

Next, the operation will be described. In this conventional example, the high speed memory 6 and the cache memory 3 are address buses,
The data bus is shared, and read / write is performed by the read (/ RD) and write (/ WR) signals synchronized with the operation clock of the CPU 1. The selection of the high speed memory or the cache memory is performed by the decoder 8 decoding the upper address output by the CPU 1 and controlling the chip selection input (/ CE).

When transferring instructions and data to the CPU, the CPU
1 accesses the synchronous memory in synchronization with the operation clock,
When it coincides with the high-speed memory 6 area, the synchronous memory controller 7 always outputs a coincidence signal, and the CPU 1 continues the process using the instruction and data read from the high-speed memory 6.

On the other hand, when the instruction and data are transferred to the CPU 1, if the area accessed by the CPU 1 is not the high-speed memory 6 area, the contents of the cache memory 3 are fetched by the CPU and the contents of the cache tag memory 4 are output by the CPU. It is compared with the upper address. If these match,
The CPU 1 continues the process using the fetched contents of the cache memory 3, and when they do not match, the CPU 1 suspends the internal process and activates the / MemRD signal to request the low-speed memory system 2 for instructions and data. When the low-speed memory system 2 prepares instructions and data accordingly, R
The DBusy signal is made inactive, and the transfer of instructions and data to the CPU is completed. At the same time, instructions and data are written in the cache memory 3 and addresses are written in the cache tag memory 4.

At the time of data transfer from the CPU 1 to the synchronous memory, the CPU 1 accesses the synchronous memory in synchronization with the operation clock, and if it is the high speed memory 6 area, the data output from the CPU 1 is written in the high speed memory 6, Mem
The WR signal remains inactive and does not request the low speed memory system 2 to write.

On the other hand, when the CPU 1 transfers data to the synchronous memory, if it is not in the high speed memory area, the CPU 1
The data output by is written in the cache memory 3,
The address is written in the cache tag memory 4, and at the same time, the / MemWR signal is activated to request the low speed memory system 2 to write data.

If the low speed memory system 2 is writable /
The WRBusy signal is made inactive, and the CPU 1 receives this signal and transfers the data to the low-speed memory system 2 to continue the processing.

The above operation will be described below by focusing on the control signal of the CPU. That is, in the case of an instruction or data transfer to the CPU 1, when the high speed memory selection signal is inactive, the CPU 1 transfers the contents of the cache memory 3 to the CPU and the contents of the cache tag memory 4 to the synchronous memory controller 7. Control signal is generated so that the synchronous memory controller 7 compares the contents of the cache tag memory 4 with the upper address of the CPU 1,
If they match, the match signal is activated and sent to the CPU 1. The CPU 1 continues the internal processing and generates a control signal to the low-speed memory system 2 so that reading is not performed, and if they do not match, the match signal is inactive. Then C
The data is sent to PU1, and CPU1 generates a control signal to suspend internal processing and transfer an instruction or data from low-speed memory system 2 to CPU1.

When the high speed memory selection signal is active in the case of an instruction or data transfer to the CPU1, the CPU1
Generates a control signal to transfer the contents of the high-speed memory 6 to the CPU 1, and the synchronous memory controller 7 fixes the coincidence signal to active at this time and sends it to the CPU 1.
PU1 continues internal processing and generates a control signal to the low-speed memory system 2 so that reading is not performed.

When data is written from the CPU 1 and the high speed memory selection signal is inactive, the CPU
1 generates a control signal so that the data output from the CPU 1 is written in the cache memory 3, the address output from the CPU 1 is written in the cache tag memory 4, and the data is written in the low speed memory system 2. .

When the high speed memory selection signal is active when writing data from the CPU 1, the CPU 1
The control signal is generated so that the data output from 1 is written in the high speed memory 6, and the control signal is generated so that the data is not written in the low speed memory system 2.

FIG. 6 shows another conventional example developed by the inventor of the present invention. In the figure, the same reference numerals as those in FIG. 5 indicate the same elements. In this conventional example, two synchronous memories, two cache memories, two cache memories, and two high-speed memories are provided so that the synchronous memory is separated for instructions and data. In the figure, 31 and 32 are cache memories for instructions and data, 41 and 42 are cache tag memories for instructions and data, and 6 respectively.
Reference numerals 1 and 62 are high-speed memories for instructions and data, respectively. 8 is a cache memory 31, 3 output by the CPU 1.
2 and a decoder for controlling the chip selection input / CE of the cache tag memories 41 and 42, and 9 outputs a high-speed memory selection signal / HSEL that is the signal HSEL output from the decoder 8 and outputs a high-speed memory selection signal / HSEL. It is an inverter that controls the chip selection input / CE of the memories 61 and 62.

In the conventional example of FIG. 6, 1 is C of FIG.
Although the CPU corresponds to PU1, the read signal / RD synchronized with the operation clock is divided into two of / RD1 and / RD2 in response to the separation of the synchronous memory for instruction and data.
First, write signal / WR synchronized with operating clock / W
Separated into R1 and / WR2 respectively, / RD2, /
WR2 is equivalent to half the CPU operation clock cycle, / RD
1, / WR1 is caused to be displaced. Further, 13 is the logical product of the read signals / RD1 and / RD2, and the read control input of the synchronous memory controller 7 /
AND gate input to RD, 14 is a write signal / WR
AND gate for taking the logical product of 1 and / WR2 and inputting to the write control input / WR of the synchronous memory controller 1
Reference numerals 2 and 11 denote latches for holding the lower addresses of the synchronous memory output from the synchronous memory controller 7 according to the operation clock output from the CPU 1 and its inverted signal, and 10 an inverter for inverting the operation clock output from the CPU 1. Is.

According to this conventional example, since two systems for the instruction and the data are prepared as the synchronous memory, the CPU
One cycle is divided into two, the first half is allocated to the instruction access, the latter half is allocated to the data access, and the instruction address and the data address are output for each half cycle. Since data can be transferred and received via the data line every half cycle, the speed of the CPU can be increased.

FIG. 8 shows still another conventional example developed by the inventor of the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same elements.

In this conventional example, the CPU 1 receives the output of the decoder 8 and reads the cache memory 3, the cache tag memory 4 and the high speed memory 6 separately and controls the write signal. When the high-speed memory selection signal is active, the CPU activates the read / HRD signal and the write / HWR signal. When the high-speed memory selection signal is inactive, the read / CRD signal is read and the write / CWR signal is written. To activate each.

In this conventional example, the synchronous memory is always selected and waits for access when the memory is ready to output the data to some extent. Therefore, the synchronous memory is read only when the chip select signal / CE is input. As compared with the conventional example of FIG.

FIG. 9 shows still another conventional example developed by the present inventor. In this conventional example, a CPU and a synchronous memory controller are integrated into one chip (in FIG. 9, the synchronous memory controller is mounted. (A CPU chip is shown as a synchronous memory controller 7), and an address bus is shared by a low-speed memory and a synchronous memory.

In the figure, CK1 is a clock which becomes L at the time of synchronous memory write or low speed memory system read / write, and CK2 is a clock which becomes L at the time of synchronous memory read.

In this conventional example, since it is not necessary to once receive the address of the CPU by the synchronous memory controller and output it to the synchronous memory, it is possible to reduce the number of signal lines and the number of pins of the CPU chip.

[0035]

The conventional CPU system is configured as described above, and as shown in FIG. 11 (b), a normal hierarchical memory system including a cache memory and a low speed memory, and a high speed memory system. By coexisting with a memory system that does not have a hierarchy consisting of only memory,
Various problems of the hierarchical memory system as shown in FIG. 11 (a) can be solved at once.

However, the configuration of this conventional system causes the following problems in actual use.

That is, in these conventional configurations, the decoding of the high speed memory area is constant, and the cache memory, the cache tag memory, the high speed memory and the CPU are
Since the connection is fixed, the cache memory capacity and the high-speed memory capacity are fixed by hardware.

Therefore, (1) In applications requiring a large-capacity hierarchical memory system such as non-real-time calculation processing, the larger the cache capacity is, the higher the performance is, and the high-speed memory is not required. Then, it is not possible to deal with such cases.

(2) On the other hand, the cache memory is not required for applications such as real-time processing where the data and program capacities are small, whereas the high-speed memory requires sufficient capacity for storing data and programs. However, the conventional example as described above cannot handle such a case.

The present invention has been made in order to solve the above-mentioned problems of the conventional one, and an object thereof is to obtain a CPU system capable of coping with a wide range of applications with the same hardware.

[0041]

A CPU system according to the present invention has the same hardware configuration and is configured to be able to variably set a ratio of a cache memory capacity and a high speed memory capacity by designation from the outside. The setting of the capacity ratio of the cache memory and the high-speed memory is based on a signal level applied to a terminal of the system or an instruction given from the outside by a value externally set to a storage element in the system. This is done by providing a circuit for switching the selection signal and switching the high speed memory selection signal for transmitting to the CPU that the high speed memory has been selected.

Further, the CPU system according to the present invention is
The bit width of the cache tag memory and the bit width of the high speed memory are made equal.

Further, the CPU system according to the present invention is
A CPU and a synchronous memory are mounted on the same semiconductor chip to form a device.

Further, the CPU system according to the present invention is
A device is configured by incorporating a CPU and a synchronous memory in a multi-chip module.

Further, the CPU system according to the present invention is
The external instruction to the system is configured to be given by the signal level applied to the terminals of the system.

Further, the CPU system according to the present invention is
An external instruction to the system is configured to be given to a storage device in the system by a value set from the outside.

Further, the CPU system according to the present invention is configured to have the synchronous memory separately for the instruction and the data.

[0048]

According to the present invention, by configuring the apparatus as described above, the ratio of the capacity of the high speed memory area can be changed by an instruction from the outside. That is, in the case of only the cache memory, the high speed memory selection signal is not activated and the cache memory is selected by the lower address. When the high-speed memory and its capacity are determined by an external instruction, the high-speed memory selection signal is activated and output to the synchronous memory controller so that the synchronous memory operates as the high-speed memory within the range. The high-speed memory selection signal is made inactive so that it operates as a cache memory or a cache tag memory outside the high-speed memory area range. When only the high speed memory is configured by an instruction from the outside, the high speed memory selection signal is always active and the synchronous memory operates as the high speed memory.

Further, according to the present invention, since the bit width of the cache tag memory and the bit width of the high speed memory are made equal as described above, the synchronous memory used as the cache tag memory or the high speed memory is the bus. By connecting to either the data bus of the CPU or the higher-order address bus (tag bus) of the synchronous memory controller via the switch, the cache tag memory and the high-speed memory can be interchanged.

Further, the CPU system according to the present invention is
Since the device is configured by mounting the CPU and the synchronous memory on the same semiconductor chip, it is possible to obtain the one in which the roles of the cache tag memory and the high speed memory can be exchanged at low cost.

Further, the CPU system according to the present invention is
Since the device is configured by incorporating the CPU and the synchronous memory in the multi-chip module, it is difficult to realize C with a single chip.
In the PU system, one in which the roles of the cache tag memory and the high speed memory can be exchanged can be obtained.

Further, the CPU system according to the present invention is
Since the instruction to the system from the outside is given by the signal level applied to the terminals of the system, the roles of the cache tag memory and the high speed memory can be easily exchanged by simply applying the signal.

Further, the CPU system according to the present invention is
The external instruction to the system is configured to be given to the storage device in the system by the value set from the outside, and the roles of the cache tag memory and the high speed memory can be easily set by the initial setting.

Further, since the CPU system according to the present invention is configured to have the synchronous memory separately for the instruction and the data, one instruction cycle of the CPU is divided into two, and the first half is the instruction access and the latter half is the data. Even if you can speed up the CPU by assigning it to access,
The roles of cache tag memory and high-speed memory can be easily exchanged.

[0055]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a CPU system according to an embodiment of the present invention. In the figure, 81, 82, 83, 84 are CPUs 1.
Is a synchronous memory that operates in synchronization with the operation clock of No. 1, which can be used as both a cache memory and a high-speed memory, and is composed of a memory that can be accessed at high speed although the bit unit price is expensive. Reference numeral 18 is a decoder for decoding a 2-bit combination of external instruction signals SEL1 and SEL0, and 21 and 22 are bus switches, which are CP depending on the decoding result of the decoder 18.
A bus for determining which of the memories 81, 82, 83, 84 is to be assigned as a high-speed memory and the remaining memory to be assigned as a cache memory and a cache tag memory by switching which memory is connected to the U1 bus. It is a switch.

Synchronous memories capable of supplying instructions to and receiving data from the CPU in synchronization with the operating clock of the CPU are prepared as the memory 81, the memory 82, the memory 83 and the memory 84. These roles can be changed according to instruction signals SEL1 and SEL0 from the outside. As shown in Table 1, when SEL1 and SEL0 = 00, all of these memories 81 to 84 are high-speed. It is not allocated to memory and operates like a normal hierarchical memory system. That is, the memory 82 operates as the cache memory 1, the memory 81 operates as its tag memory, the memory 84 operates as the cache memory 2, and the memory 83 operates as its tag memory.

On the other hand, the instruction signal from the outside is SEL.
1, when SEL0 = 01, the memories 81 and 82 operate as the cache tag memory 1 and the cache memory 1, and the memories 83 and 84 operate as the high-speed memory 1 and the high-speed memory 2, and the normal hierarchical memory system as shown in FIG. It operates as a system with high-speed memory attached to.

Further, the external instruction signals are SEL1, S
When EL0 = 11, the memories 81, 82, 83, 84 operate as the high speed memories 1, 2, 3, 4 and operate in the same manner as the single hierarchical system configured by only the high speed memories.

The above situation is shown in Table 1.

[0060]

[Table 1]

As described above, in this embodiment, the bus switches 21 and 22 are provided and the instruction signal SEL is provided in order to exchange the roles of the cache tag memory and the high speed memory.
1, when SEL0 = 00, that is, when both the memory 81 and the memory 83 operate as a cache tag memory, the data input / output terminal D of the memory 81 and the memory 83.
Are connected to the upper address AddHi output from the synchronous memory controller 7.

The instruction signals are SEL1 and SEL0 = 0.
When 1, that is, when the memory 81 and the memory 83 operate as a cache tag memory and a high-speed memory, respectively, the data input / output terminal D of the memory 81 and the memory 83 transmits an upper address output from the synchronous memory controller 7 AddHi It is connected to the bus and the data bus of the CPU 1, respectively.

Further, the instruction signals are SEL1 and SEL0 =
In the case of 11, that is, when both the memory 81 and the memory 83 operate as a high speed memory, the data input / output terminals D of the memory 81 and the memory 83 are connected to the data bus of the CPU 1.

This state is shown in Table 2.

[0065]

[Table 2]

On the other hand, on the decoder 18 side, the instruction signal SE
If the high-speed memory is selected by L1 and SEL0 and the upper address AddHi, / HSEL is set to L (active), and otherwise set to H. / CE1, / CE2,
/ CE3 and / CE4 are memories 81, 82 and 8 respectively.
When the address area assigned to 3,84 is accessed, it becomes L (active).

This state is shown in Table 3.

[0068]

[Table 3]

That is, the address is within the address range of the memories 81 and 82, and the external instruction signals SEL1 and SE
When both L0 are 0, / CE1, / CE2, /
CE3 and / CE4 are 0, 0, 1, 1 and / HSE, respectively.
L becomes 1.

Further, the address is within the address range of the memories 83 and 84, and the external instruction signals SEL1 and SE.
When both L0 are 0, / CE1, / CE2, /
CE3 and / CE4 are 1,1,0,0 and / HSE respectively.
L becomes 1.

Further, the address is within the address range of the high speed memory 83, and the external instruction signals SEL1 and SEL.
When 0 is 0 and 1 respectively, / CE1 and / CE2
, / CE3, / CE4 are 1, 1, 0, 1, /
HSEL becomes 0.

Further, the address is within the address range of the high speed memory 84, and the instruction signals SEL1 and SEL from the outside are supplied.
When 0 is 0 and 1 respectively, / CE1 and / CE2
, / CE3, / CE4 are 1, 1, 1, 0, /
HSEL becomes 0.

Further, the address is out of the address range of the high speed memory, and external instruction signals SEL1 and SEL0.
Are 0 and 1, respectively, / CE1, / CE2,
/ CE3 and / CE4 are 0, 0, 1, 1 and / HS respectively
EL becomes 1.

Further, the address is within the address range of the high speed memory 81, and the external instruction signals SEL1 and SEL are used.
When both 0's are 1, / CE1, / CE2, / C
E3 and / CE4 are 0, 1, 1, 1 and / HSEL respectively
Is 0.

Further, the address is within the address range of the high speed memory 82, and the instruction signals SEL1 and SEL from the outside are supplied.
When both 0's are 1, / CE1, / CE2, / C
E3 and / CE4 are 1,0,1,1 and / HSEL respectively
Is 0.

Further, the address is within the address range of the high speed memory 83, and the instruction signals SEL1 and SEL from the outside are supplied.
When both 0's are 1, / CE1, / CE2, / C
E3 and / CE4 are 1,1,0,1 and / HSEL respectively
Is 0.

Further, the address is within the address range of the high speed memory 84, and the instruction signals SEL1 and SEL from the outside are supplied.
When both 0's are 1, / CE1, / CE2, / C
E3 and / CE4 are 1,1,1,0 and / HSEL respectively
Is 0.

Further, the address is out of the address range of the high speed memory, and external instruction signals SEL1 and SEL0.
If both are 1, then / CE1, / CE2, / CE
3, / CE4 is 1, 1, 1, 1 and / HSEL is 1, respectively.

As described above, according to the above-described embodiment, the synchronous memory which can be used as both the cache memory and the high speed memory is prepared, the instruction signal from the outside is decoded, and the input is input to the lower address bus of the synchronous memory controller. Since the data bus is switched to one of the CPU data buses, the capacity of the synchronous memory can be appropriately distributed to the cache memory and the high-speed memory, and the same hardware can flexibly support a wide range of applications.

In the above embodiment, four synchronous memories capable of high-speed operation and two external instruction signals are used, but the present invention is not limited to this. Also, C
It goes without saying that the present invention can be applied to the case where the connection with the PU is separated from the instruction memory and the data memory.

Example 2. FIG. 2 shows a CPU system according to another embodiment of the present invention. In the figure, 81a, 82
a, 83a, 84a are synchronous memories for data,
Reference numerals 81b, 82b, 83b and 84b are synchronous memories for instructions. These are memories that can be used as both a cache memory and a high-speed memory, and are composed of a memory such as SRAM, which has a high bit unit price but can be accessed at high speed. 18a is an instruction signal IS from the outside
A decoder that decodes a 4-bit combination of EL1, ISEL0, DSEL1, and DSEL0, and 21a and 22a are bus switches for data, and switches which memory is connected to the bus of the CPU1 according to the decoding result of the decoder 18a. As a result, the memory 81a,
This is a bus switch that determines which memory 82a, 83a, 84a is to be allocated as a high-speed memory and the remaining memory is allocated as a cache memory and a cache tag memory. Further, 21b and 22b are bus switches for instructions, and by switching which memory is connected to the bus of the CPU 1 according to the decoding result of the decoder 18a, the memories 81b, 82b, 83b and 8b.
This is a bus switch that determines which memory of 4b is to be allocated as a high speed memory and the remaining memory is allocated as a cache memory and a cache tag memory. Also,
Reference numeral 10 is an inverter that inverts the clock / CLK output from the CPU 1 and outputs it to the clock input terminals of the latches 11 and 12, and 11 is a memory 81a, 82a, 83a, which latches the lower address output by the synchronous memory controller 7.
A latch for outputting to the memory 84a, and 12 for latching the lower address output by the synchronous memory controller 7 for storing the memory 81
b, 82b, 83b, 84b, a latch, 13 is an AND gate that takes the logical product of / IRD and / DRD and outputs it to the / RD input of the synchronous memory controller 7, and 14 is the logical product of / IWD and / DWD This is an AND gate for outputting to the / RD input of the synchronous memory controller 7.

According to this embodiment, since two systems for instruction and data are prepared as the synchronous memory, the CPU
One cycle is divided into two, the first half is allocated to the instruction access and the latter half is allocated to the data access, and the instruction address and the data address are output for each half cycle. Since the data can be sent and received via the CPU, the speed of the CPU can be increased.

At this time, the instruction signal IS from the outside
By combining EL1, ISEL0, DSEL1 and DSEL0, data memories 81a, 82a, 83
It is possible to determine which of the memories a and 84a is to be allocated as the high-speed memory for data and which of the remaining memories is to be allocated as the cache memory for data and the cache tag memory for data. Independently of this, which of the instruction memories 81b, 82b, 83b, 84b is allocated as a high-speed memory for instructions, and the remaining memory is allocated as a cache memory for instructions and a cache tag memory for instructions. You can decide Therefore, in this embodiment, the memory allocation according to the instruction signal shown in Table 1 does not have the three states shown in Table 1, but has nine states for convenience.

That is, the external instruction signals DSEL1, D
When SEL0, ISEL1, ISEL0 are 0, 0, 0, 0, the memories 81a, 82a, 83a, 84a become the cache tag memory 1, the cache memory 1, the cache tag memory 2, and the cache memory 2, respectively, and the memories 81b, 82b, 83b and 84b are a cache tag memory 1, a cache memory 1, a cache tag memory 2 and a cache memory 2, respectively.

Further, external instruction signals DSEL1, D
When SEL0, ISEL1 and ISEL0 are 0, 0, 0 and 1, the memories 81a, 82a, 83a and 84a become the cache tag memory 1, the cache memory 1, the cache tag memory 2 and the cache memory 2, respectively, and the memories 81b and 82b, 83b and 84b are cache tag memory 1, cache memory 1, high speed memory 1, and
It becomes the high-speed memory 2.

In addition, external instruction signals DSEL1, D
When SEL0, ISEL1, ISEL0 are 0, 0, 1, 1, the memories 81a, 82a, 83a, 84a become the cache tag memory 1, the cache memory 1, the cache tag memory 2, the cache memory 2, respectively, and the memories 81b, 82b, 83b and 84b are a high speed memory 1, a high speed memory 2, a high speed memory 3 and a high speed memory 4, respectively.

Further, external instruction signals DSEL1, D
When SEL0, ISEL1, ISEL0 are 0, 1, 0, 0, the memories 81a, 82a, 83a, 84a become the cache tag memory 1, the cache memory 1, the high speed memory 1, the high speed memory 2, respectively, and the memories 81b, 82.
b, 83b and 84b are a cache tag memory 1, a cache memory 1, a cache tag memory 2 and a cache memory 2, respectively.

Further, external instruction signals DSEL1, D
When SEL0, ISEL1 and ISEL0 are 0, 1, 0 and 1, the memories 81a, 82a, 83a and 84a become the cache tag memory 1, the cache memory 1, the high speed memory 1 and the high speed memory 2, respectively, and the memories 81b and 82.
b, 83b and 84b are cache tag memory 1, cache memory 1, high speed memory 1 and high speed memory 2 respectively.
Becomes

In addition, external instruction signals DSEL1, D
When SEL0, ISEL1, and ISEL0 are 0, 1, 1, and 1, the memories 81a, 82a, 83a, and 84a become the cache tag memory 1, the cache memory 1, the high-speed memory 1, and the high-speed memory 2, respectively, and the memories 81b and 82.
b, 83b and 84b are a high speed memory 1, a high speed memory 2, a high speed memory 3 and a high speed memory 4, respectively.

Further, external instruction signals DSEL1, D
When SEL0, ISEL1, ISEL0 are 1, 1, 0, 0, the memories 81a, 82a, 83a, 84a become the high-speed memory 1, the high-speed memory 2, the high-speed memory 3, the high-speed memory 4, respectively, and the memories 81b, 82b, 83b, 84b
Are cache tag memory 1, cache memory 1, cache tag memory 2, and cache memory 2, respectively.

In addition, external instruction signals DSEL1, D
When SEL0, ISEL1 and ISEL0 are 1, 1, 0 and 1, the memories 81a, 82a, 83a and 84a become the high speed memory 1, the high speed memory 2, the high speed memory 3 and the high speed memory 4, respectively, and the memories 81b, 82b and 83b, 84b
Are respectively a cache tag memory 1, a cache memory 1, a high speed memory 1 and a high speed memory 2.

Further, an external instruction signal DSEL1,
DSEL0, ISEL1, and ISEL0 are 1,1,1,1
At this time, the memories 81a, 82a, 83a, 84a become the high-speed memory 1, the high-speed memory 2, the high-speed memory 3, and the high-speed memory 4, respectively, and the memories 81b, 82b, 83b, 84
b is a high speed memory 1, a high speed memory 2, a high speed memory 3 and a high speed memory 4, respectively.

As described above, in this embodiment, in order to enable the roles of the cache tag memory and the high speed memory to be exchanged,
Bus switches 21a, 22a, 21b, 22b are provided,
Indicator signals ISEL1, ISEL0, DSEL1, DSE
When L0 = 0000, that is, when the memories 81a and 81b and the memories 83a and 83b both operate as cache tag memories, the synchronous memory controller 7 outputs the data input / output terminals D of the memories 81a and 81b and the memories 83a and 83b. Connect to the upper address AddHi.

Further, the instruction signals are ISEL1 and ISEL.
0, DSEL1, DSEL0 = 0001, that is, both the memory 81a and the memory 83a operate as a cache tag memory, and the memory 81b and the memory 83b.
Of the synchronous memory controller 7 and the data input / output terminals D of the memory 81a and the memory 83a, respectively.
Connected to the upper address AddHi output by the
1b and the data input / output terminal D of the memory 83b are transmitted to the higher address output from the synchronous memory controller 7.
Connect to the AddHi bus and the data bus of the CPU1 respectively.

Further, the instruction signals are ISEL1 and ISEL.
0, DSEL1, DSEL0 = 0011, that is, both the memory 81a and the memory 83a operate as a cache tag memory, and the memory 81b and the memory 83b.
If both operate as high-speed memory, the memory 81
a and the data input / output terminal D of the memory 83a, the upper address AddHi output from the synchronous memory controller 7
And the data input / output terminals D of the memory 81b and the memory 83b are connected to the data bus of the CPU 1.

Further, the instruction signals ISEL1, ISEL0, D
When SEL1 and DSEL0 = 0100, that is, the memory 8
1a and memory 83a operate as cache tag memory and high-speed memory, respectively, and memory 81b and memory 83b both operate as cache tag memory, data input / output terminal D of memory 81a and memory 83a is connected to the data bus of CPU1. Then, the high-order address Ad output from the synchronous memory controller 7 is output to both the data input / output terminals D of the memory 81b and the memory 83b.
Connect to dHi.

Further, the instruction signals are ISEL1 and ISEL.
0, DSEL1, DSEL0 = 0101, that is, the memory 81a and the memory 83a operate as a cache tag memory and a high-speed memory, respectively, and the memory 81b
And the memory 83b operate as a cache tag memory and a high-speed memory, respectively, the data input / output terminal D of the memory 81a and the memory 83a transmits the upper address output from the synchronous memory controller 7 AddHi.
The data input / output terminals D of the memory 81b and the memory 83b are respectively connected to the bus and the data bus of the CPU1 and to the AddHi bus for transmitting the higher address output from the synchronous memory controller 7 and the data bus of the CPU1.

Further, the instruction signals are ISEL1 and ISEL.
When 0, DSEL1, DSEL0 = 0111, that is, when the memory 81a and the memory 83a operate as a cache tag memory and a high speed memory, respectively, and the memory 81b and the memory 83b both operate as a high speed memory, the memory 81a and the memory 81a The data input / output terminal D of 83a is connected to the AddHi bus for transmitting the upper address output from the synchronous memory controller 7 and the data bus of the CPU 1, respectively, and the data input / output terminal D of the memory 81b and the memory 83b is connected to the data bus of the CPU 1. To do so.

Further, the instruction signals ISEL1, ISEL0, D
When SEL1 and DSEL0 = 1100, that is, the memory 8
1a and memory 83a operate as high-speed memories, and memory 81b and memory 83b both operate as cache tag memories, data input / output terminal D of memory 81a and memory 83a is connected to the data bus of CPU1, and memory 81b is connected. And the data input / output terminal D of the memory 83b are both connected to the synchronous memory controller 7
Connect to the upper address AddHi output by.

Further, the instruction signals are ISEL1 and ISEL.
When 0, DSEL1, DSEL0 = 1101, that is, when both the memory 81a and the memory 83a operate as a high-speed memory and the memory 81b and the memory 83b operate as a cache tag memory and a high-speed memory, respectively, the memory 81a and the memory 83a The data input / output terminal D is connected to the data bus of the CPU 1, and the data input / output terminal D of the memory 81b and the memory 83b is connected to the AddHi bus for transmitting the higher address output from the synchronous memory controller 7 and the data bus of the CPU 1, respectively. To do.

The instruction signals are ISEL1 and ISEL.
When 0, DSEL1, DSEL0 = 1111, that is, when both the memory 81a and the memory 83a operate as a high-speed memory and both the memory 81b and the memory 83b operate as a high-speed memory, the data input to the memory 81a and the memory 83a is input. The output terminal D is connected to the data bus of the CPU 1, and the data input / output terminals D of the memories 81b and 83b are connected to the data bus of the CPU 1.

On the other hand, on the decoder 18a side, the instruction signal S
/ HSEL is set to L (active) when the high-speed memory is selected by EL1 and SEL0 and the upper address AddHi, and is set to H otherwise. / CE1, / CE2,
/ CE3 and / CE4 are memories 81, 82 and 8 respectively.
When the address area assigned to 3,84 is accessed, it becomes L (active). That is, the decoding logic of the decoder 18a in this case is the instruction signals ISEL1, IS
For EL0, DSEL1 and DSEL0, the operation shown in Table 3 is the same as if there are two independent systems.

As described above, according to the above-mentioned embodiment, two systems for the instruction and the data are prepared as the synchronous memory, and the CP
By dividing one cycle of U into two, assigning the first half to instruction access and the latter half to data access, and outputting the instruction address and data address in half cycles, The capacity of the synchronous memory in the one that can be transmitted and received via the line and the speed of the CPU can be increased,
Since the cache memory and the high-speed memory can be appropriately distributed, the same hardware can flexibly support a wide range of applications.

Example 3. FIG. 3 shows a CPU system according to still another embodiment of the present invention, and the same reference numerals as those in FIG. 1 denote the same parts. 23 and 24 are cache read signals / CRDs and high-speed memory read signals / H to the memories 81, 83 and 82, 84 in response to external instruction signals.
It is a selector that selects and supplies one of RD, cache write signal / CWR, and high speed memory / HWR.

In this embodiment, the CPU receives the output of the decoder and reads the cache memory, the cache tag memory and the high speed memory separately and controls the write signal. When the high-speed memory selection signal is active, the CPU 1 activates the / HRD signal during reading and the / HWR signal during writing, and when the high-speed memory selection signal is inactive, / CR during reading.
The D signal and the / CWR signal are activated during writing.

This state is shown in Table 4.

[0107]

[Table 4]

That is, the external command signal SEL1,
When SEL0 is 00, for each of the memories 81 to 84, the / CRD signal is read at the time of reading, and the / CRD signal is written at the time of writing.
Activate the CWR signals respectively.

In addition, external command signals SEL1, SE
When L0 is 01, for each of the memories 81 and 82, the / CRD signal is read when reading and the / CW signal is written when writing.
The R signal is activated and the memory 8
For each of 3 and 84, the / CRD signal is activated during reading and the / CWR signal is activated during writing.

Further, external command signals SEL1, S
When EL0 is 11, for each of the memories 81 to 84, the / HRD signal is read when reading and the / HRD signal is written when writing.
Each activates the WR signal.

According to this embodiment, the synchronous memory remains selected at all times and waits for access when the memory is ready to output data to some extent, so that the chip select signal / CE is input. Even in the case where the memory access time is longer than that in the embodiment of FIG. 1 in which reading is performed for the first time, the capacity of the synchronous memory can be appropriately distributed to the cache memory and the high-speed memory, so that the same hardware can be used. The software can flexibly support a wide range of applications.

Example 4. FIG. 4 shows still another embodiment of the present invention. In this embodiment, a CPU and a synchronous memory controller are mounted on the same chip (in FIG. 4, a CPU chip equipped with this synchronous memory controller is a synchronous memory). This is an example in which the address bus is shared by the low-speed memory and the synchronous memory.

In the figure, CK1 is a clock which becomes L at the time of synchronous memory write or low speed memory system read / write, and CK2 is a clock which becomes L at the time of synchronous memory read.

According to this embodiment, since it is not necessary to once receive the address of the CPU in the synchronous memory controller and output it to the synchronous memory, the signal line can be saved and the CP
Even if it is possible to reduce the number of U-chip pins,
Since the capacity of the synchronous memory can be appropriately distributed to the cache memory and the high-speed memory, the same hardware can flexibly support a wide range of applications.

The CPU, the synchronous memory controller, the decoder, the cache memory, the cache tag memory, the high speed memory, the low speed memory, and some or all of the inverters in each of the above embodiments may be mounted on the same semiconductor chip. It may be built in the multi-chip module, and the same effect as that of each of the above-described embodiments can be obtained. The multi-chip module is a semiconductor device configured by accommodating a plurality of semiconductor integrated circuit chips that are not packaged in the same package.

Also, only the instruction signal is shown to be input from the outside by changing the level of the signal applied to the terminal of the system, but this is set in the memory in the system from the outside. It may be given by a different value, and the same effect as each of the above-mentioned embodiments is obtained.

[0117]

As described above, according to the CPU system of the present invention, the ratio of the cache memory capacity and the high speed memory capacity can be variably set by the designation from the outside with the same hardware configuration. The setting of the capacity ratio of the cache memory and the high-speed memory is based on a signal level applied to a terminal of the system or an instruction given from the outside by a value externally set to a storage element in the system. This is done by providing a circuit for switching the selection signal and for switching the high-speed memory selection signal for transmitting to the CPU that the high-speed memory has been selected. There is an effect that it can be changed by instructions.

Further, according to the CPU system of the present invention, the bit width of the cache tag memory and the bit width of the high speed memory are made equal, so that the synchronous memory used as the cache tag memory or the high speed memory is a bus. By connecting to either the data bus of the CPU or the higher-order address bus (tag bus) of the synchronous memory controller via the switch, the cache tag memory and the high-speed memory can be interchanged.

Further, according to the CPU system of the present invention, since the CPU and the synchronous memory are mounted on the same semiconductor chip to configure the device, the roles of the cache tag memory and the high speed memory can be exchanged at low cost. There is an effect that can be obtained.

Further, according to the CPU system of the present invention, the CPU and the synchronous memory are built in the multi-chip module to configure the device. Therefore, in the CPU system which is difficult to realize with a single chip, the cache tag memory and There is an effect that the role of the high speed memory can be exchanged.

Further, according to the CPU system of the present invention, the instruction from the outside to the system is provided by the signal level applied to the terminals of the system. Therefore, the cache tag is simply applied. There is an effect that the roles of the memory and the high speed memory can be easily exchanged.

Further, according to the CPU system of the present invention, the instruction from the outside to the system is configured to be given to the storage device in the system by the value set from the outside. This has the effect of easily setting the roles of the tag memory and the high-speed memory.

Further, since the CPU system according to the present invention has the synchronous memory separately for the instruction and the data, one instruction cycle of the CPU is divided into two and the first half is the instruction access and the latter half is the data. Even if you can speed up the CPU by assigning it to access,
There is an effect that the roles of the cache tag memory and the high speed memory can be easily exchanged.

[Brief description of drawings]

FIG. 1 is a block diagram showing a CPU system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a CPU system according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a CPU system according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a CPU system according to still another embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a CPU system developed by the applicant.

FIG. 6 is a block diagram showing another example of a CPU system developed by the applicant.

7 is a time chart diagram of the CPU system of FIG. 6;

FIG. 8 is a block diagram showing still another example of a CPU system developed by the applicant.

FIG. 9 is a block diagram showing still another example of the CPU system developed by the applicant.

FIG. 10 is a block diagram showing a conventional CPU system.

FIG. 11 is a schematic view showing a memory area of a CPU system developed by the conventional and applicants, and FIG. 11 (a) is a schematic view showing the memory area of a conventional CPU system;
1 (b) is a schematic diagram showing a memory area of a CPU system developed by the applicant.

[Explanation of symbols]

 1 CPU 2 Low-speed memory system 7 Synchronous memory controller 73 Comparator 18 Decoder 21, 22 Bus switch 23, 24 Bus switch 21a, 22a Bus switch 21b, 22b Bus switch 81, 82, 83, 84 Synchronous memory 81a, 82a, 83a, 84a synchronous memory 81b, 82b, 83b, 84b synchronous memory

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 21, 1993

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Data processing device

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

This invention has a hierarchical memory.
The present invention relates to a data processing device , and more particularly, to a data processing device having an improved interface between a CPU and a memory.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

[0041]

Data processing according to the present invention
The processor is configured with the same hardware configuration so that the ratio of cache memory capacity and high-speed memory capacity can be variably set by external specification. Is to switch the selection signal of each synchronous memory based on the signal level applied to the terminal of the system or the instruction given from the outside by the value set externally to the storage element in the system, and that the high speed memory is selected. This is done by providing a circuit for switching the high-speed memory selection signal for transmitting to the CPU.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
The bit width of the cache tag memory and the bit width of the high speed memory are made equal.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
A CPU and a synchronous memory are mounted on the same semiconductor chip to form a device.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
A device is configured by incorporating a CPU and a synchronous memory in a multi-chip module.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
The external instruction to the system is configured to be given by the signal level applied to the terminals of the system.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
An external instruction to the system is configured to be given to a storage device in the system by a value set from the outside.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction content]

Further, according to the present inventionData processing device
Have separate synchronous memory for instructions and data
It is configured in.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
Since the device is configured by mounting the CPU and the synchronous memory on the same semiconductor chip, it is possible to obtain the one in which the roles of the cache tag memory and the high speed memory can be exchanged at low cost.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
Since the device is configured by incorporating the CPU and the synchronous memory in the multi-chip module, it is difficult to realize C with a single chip.
In the PU system, one in which the roles of the cache tag memory and the high speed memory can be exchanged can be obtained.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0052

[Correction method] Change

[Correction content]

Further, the data processing device according to the present invention is
Since the instruction to the system from the outside is given by the signal level applied to the terminals of the system, the roles of the cache tag memory and the high speed memory can be easily exchanged by simply applying the signal.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction content]

Further, the data processing apparatus according to the present invention is
The external instruction to the system is configured to be given to the storage device in the system by the value set from the outside, and the roles of the cache tag memory and the high speed memory can be easily set by the initial setting.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction content]

Furthermore, according to the present inventionData processing device
Have separate synchronous memory for instructions and data
Because it is configured as, 1 CPU instruction cycle is divided into 2
Assign the first half to instruction access and the second half to data access
Even if the CPU speed can be increased by doing so,
Easily swap the roles of cache tag memory and high speed memory
it can.

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0055

[Correction method] Change

[Correction content]

[0055]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a data processing device according to an embodiment of the present invention. In the figure, 81, 82, 83, 84 are CPUs 1.
Is a synchronous memory that operates in synchronization with the operation clock of No. 1, which can be used as both a cache memory and a high-speed memory, and is composed of a memory that can be accessed at high speed although the bit unit price is expensive. Reference numeral 18 is a decoder for decoding a 2-bit combination of external instruction signals SEL1 and SEL0, and 21 and 22 are bus switches, which are CP depending on the decoding result of the decoder 18.
A bus for determining which of the memories 81, 82, 83, 84 is to be assigned as a high-speed memory and the remaining memory to be assigned as a cache memory and a cache tag memory by switching which memory is connected to the U1 bus. It is a switch.

[Procedure 18]

[Document name to be amended] Statement

[Correction target item name] 0081

[Correction method] Change

[Correction content]

Example 2. FIG. 2 shows a data processing device according to another embodiment of the present invention. In the figure, 81a, 82
a, 83a, 84a are synchronous memories for data,
Reference numerals 81b, 82b, 83b and 84b are synchronous memories for instructions. These are memories that can be used as both a cache memory and a high-speed memory, and are composed of a memory such as SRAM, which has a high bit unit price but can be accessed at high speed. 18a is an instruction signal IS from the outside
A decoder that decodes a 4-bit combination of EL1, ISEL0, DSEL1, and DSEL0, and 21a and 22a are bus switches for data, and switches which memory is connected to the bus of the CPU1 according to the decoding result of the decoder 18a. As a result, the memory 81a,
This is a bus switch that determines which memory 82a, 83a, 84a is to be allocated as a high-speed memory and the remaining memory is allocated as a cache memory and a cache tag memory. Further, 21b and 22b are bus switches for instructions, and by switching which memory is connected to the bus of the CPU 1 according to the decoding result of the decoder 18a, the memories 81b, 82b, 83b and 8b.
This is a bus switch that determines which memory of 4b is to be allocated as a high speed memory and the remaining memory is allocated as a cache memory and a cache tag memory. Also,
Reference numeral 10 is an inverter that inverts the clock / CLK output from the CPU 1 and outputs it to the clock input terminals of the latches 11 and 12, and 11 is a memory 81a, 82a, 83a, which latches the lower address output by the synchronous memory controller 7.
A latch for outputting to the memory 84a, and 12 for latching the lower address output by the synchronous memory controller 7 for storing the memory 81
b, 82b, 83b, 84b, a latch, 13 is an AND gate that takes the logical product of / IRD and / DRD and outputs it to the / RD input of the synchronous memory controller 7, and 14 is the logical product of / IWD and / DWD This is an AND gate for outputting to the / RD input of the synchronous memory controller 7.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0104

[Correction method] Change

[Correction content]

Example 3. 3 shows a data processing device according to still another embodiment of the present invention, and the same reference numerals as those in FIG. 1 denote the same parts. 23 and 24 are cache read signals / CRDs and high-speed memory read signals / H to the memories 81, 83 and 82, 84 in response to external instruction signals.
It is a selector that selects and supplies one of RD, cache write signal / CWR, and high speed memory / HWR.

[Procedure amendment 20]

[Document name to be amended] Statement

[Correction target item name] 0117

[Correction method] Change

[Correction content]

[0117]

As described above, the data processing according to the present invention
According to the processing device , the ratio of cache memory capacity and high-speed memory capacity can be variably set by external specification with the same hardware configuration. , The selection signal of each synchronous memory is switched based on the signal level applied to the terminal of the system or the instruction given from the outside by the value externally set to the storage element in the system, and the high-speed memory is selected. Since this is performed by providing a circuit for switching the high speed memory selection signal transmitted to the CPU, there is an effect that the ratio of the capacity of the high speed memory area can be changed by an instruction from the outside.

[Procedure correction 21]

[Document name to be amended] Statement

[Correction target item name] 0118

[Correction method] Change

[Correction content]

Further, according to the data processing apparatus of the present invention, the bit width of the cache tag memory and the bit width of the high speed memory are made equal, so that the synchronous memory used as the cache tag memory or the high speed memory is: By connecting to either the data bus of the CPU or the higher-order address bus (tag bus) of the synchronous memory controller via the bus switch, the cache tag memory and the high-speed memory can be interchanged.

[Procedure correction 22]

[Document name to be amended] Statement

[Name of item to be corrected] 0119

[Correction method] Change

[Correction content]

Further, according to the data processor of the present invention, the CPU and the synchronous memory are mounted on the same semiconductor chip to constitute the device, so that the roles of the cache tag memory and the high speed memory can be exchanged at low cost. It has the effect of obtaining

[Procedure amendment 23]

[Document name to be amended] Statement

[Correction target item name] 0120

[Correction method] Change

[Correction content]

Further, according to the data processing device of the present invention, the CPU and the synchronous memory are built in the multi-chip module to configure the device. Therefore, in a CPU system which is difficult to realize with a single chip, a cache tag memory is provided. And the effect of being able to exchange the role of high-speed memory is obtained.

[Procedure correction 24]

[Document name to be amended] Statement

[Correction target item name] 0121

[Correction method] Change

[Correction content]

Further, according to the data processor of the present invention, the instruction to the system from the outside is given by the signal level applied to the terminal of the system. Therefore, the cache is simply applied. This has the effect of easily exchanging the roles of the tag memory and the high-speed memory.

[Procedure correction 25]

[Document name to be amended] Statement

[Name of item to be corrected] 0122

[Correction method] Change

[Correction content]

Further, according to the data processing apparatus of the present invention, the external instruction to the system is configured to be given to the storage device in the system by the value set from the outside. This has the effect of easily setting the roles of the cache tag memory and the high-speed memory.

[Procedure Amendment 26]

[Document name to be amended] Statement

[Name of item to be corrected] 0123

[Correction method] Change

[Correction content]

Furthermore, in the data processing device according to the present invention ,
According to this configuration , the synchronous memory is configured to have separate memory for instructions and data, so that one instruction cycle of the CPU is divided into two and the first half is assigned to the instruction access and the latter half is assigned to the data access, thereby speeding up the CPU. Even if it can be achieved, the roles of the cache tag memory and the high speed memory can be easily exchanged.

[Procedure Amendment 27]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a data processing device according to another embodiment of the present invention.

FIG. 3 is a data processing device according to still another embodiment of the present invention.
It is a block diagram showing an arrangement .

FIG. 4 is a data processing device according to still another embodiment of the present invention.
It is a block diagram showing an arrangement .

FIG. 5 is a block diagram showing an example of a CPU system developed by the applicant.

FIG. 6 is a block diagram showing another example of a CPU system developed by the applicant.

7 is a time chart diagram of the CPU system of FIG. 6;

FIG. 8 is a block diagram showing still another example of a CPU system developed by the applicant.

FIG. 9 is a block diagram showing still another example of the CPU system developed by the applicant.

FIG. 10 is a block diagram showing a conventional CPU system.

FIG. 11 is a schematic view showing a memory area of a CPU system developed by the conventional and applicants, and FIG. 11 (a) is a schematic view showing the memory area of a conventional CPU system;
1 (b) is a schematic diagram showing a memory area of a CPU system developed by the applicant.

[Description of Reference Signs] 1 CPU 2 Low-speed memory system 7 Synchronous memory controller 73 Comparator 18 Decoder 21, 22 Bus switch 23, 24 Bus switch 21a, 22a Bus switch 21b, 22b Bus switch 81, 82, 83, 84 Synchronous memory 81a , 82a, 83a, 84a Synchronous memory 81b, 82b, 83b, 84b Synchronous memory

Claims (7)

[Claims] 1. A system comprising a CPU for processing data in a procedure according to a program and a synchronous memory for supplying an instruction to the CPU or exchanging data with the CPU in synchronization with an operating clock of the CPU. In response to an external instruction to the above, the synchronous memory serves as a cache memory that supplies an instruction to the CPU or exchanges data with the CPU and its cache tag memory, or a high-speed memory that supplies an instruction to the CPU or exchanges data with the CPU. A CPU system comprising: a capacity switching means capable of switching so as to be operable, wherein the capacity distribution of the synchronous memory is variable between a cache memory and its cache tag memory and a high speed memory. 2. A bit width of the cache tag memory,
2. The CPU system according to claim 1, wherein the high speed memories have the same bit width. 3. The CPU system according to claim 1, wherein the CPU and the synchronous memory are mounted on the same semiconductor chip. 4. A CPU system according to claim 1, wherein said CPU and said synchronous memory are built in a multichip module. 5. The CPU system according to claim 1, wherein the external instruction to the system is given by a signal level applied to a terminal of the system. 6. The CPU system according to claim 1, wherein the external instruction to the system is given to a storage device in the system by a value set from the outside. 7. The CPU system according to claim 1, wherein the memory is separately provided for instructions and data.